2012-10-15 19:10:29 +00:00
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/*
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* (C) Copyright 2012 SAMSUNG Electronics
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* Jaehoon Chung <jh80.chung@samsung.com>
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* Rajeshawari Shinde <rajeshwari.s@samsung.com>
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*
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2013-07-08 07:37:19 +00:00
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* SPDX-License-Identifier: GPL-2.0+
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2012-10-15 19:10:29 +00:00
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*/
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2013-12-26 11:29:07 +00:00
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#include <bouncebuf.h>
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2012-10-15 19:10:29 +00:00
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#include <common.h>
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2015-08-07 02:16:27 +00:00
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#include <errno.h>
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2012-10-15 19:10:29 +00:00
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#include <malloc.h>
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2015-09-02 23:24:58 +00:00
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#include <memalign.h>
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2012-10-15 19:10:29 +00:00
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#include <mmc.h>
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#include <dwmmc.h>
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#define PAGE_SIZE 4096
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mmc: dwmmc: Add stride PIO for better burst mode support
This patch enables stride PIO for better burst mode
support on some rockchip platforms, for instance rk3128,
etc. It uses ldm and stm to make multiple accessing from
CPU under some ARM architecture.
Design Note:
1) Carefully test it beyond the armv7(m) core since I don't
test them! If you disassemble the code, dwmci_memcpy_fromio
may be changed to use ldmia.w and stmia.w, as well as some
other optimization for push/pop stack operation, but they
are all fine!
2) Do *NOT* remove noinline and __volatile attributes as
you could fall into trouble by the optimization of GCC.
And please invent new attributes if you use *OTHER* compilers
which have their own keywords claiming the function to be a
"plase don't inline the function and please don't reorder the
groups".
3) If you want to use this feature for other rockchip platforms,
you could append new config in rockchip_dw_mmc.c. But now we only
have CONFIG_ROCKCHIP_RK3128 which means we just enable it for
rk312x platforms.
4) Stride PIO is determined by both of host->stride_pio and
the data payload. The intention of it is to make the block
accessing faster. So now only enable it for who's data payload
is larger(or equal to)than 512 Bytes.
5) MAX_STRIDE means we support burst MAX_STRIDE * 4 Bytes per
stride. Of course you could change that, but please read the
comment before it in the code and do it carefully.
How to test?
1) Prepare a memory, for instance, 0x70000000 on RK3126c.
=> mw 0x70000000 0x55aa55aa 0x200
2) Check it to see if 0x70000000 ~ 0x700000200 are all 0x55aa55aa
=> md 0x70000000 0x200
70000000: 55aa55aa 55aa55aa 55aa55aa 55aa55aa .U.U.U.U.U.U.U.U
70000010: 55aa55aa 55aa55aa 55aa55aa 55aa55aa .U.U.U.U.U.U.U.U
70000020: 55aa55aa 55aa55aa 55aa55aa 55aa55aa .U.U.U.U.U.U.U.U
70000030: 55aa55aa 55aa55aa 55aa55aa 55aa55aa .U.U.U.U.U.U.U.U
....
3) Fetch data of 0x70000000 ~ 0x700000200 and wrrite them to eMMC,
for instance, LBA 0x10000, and blk count is 1 as one blk means 0x200
bytes.
=> mmc write 0x70000000 0x10000 1
MMC write: dev # 0, block # 65536, count 1 ... 1 blocks written: OK
4) Clean the merory buffer and double check it
=> mw 0x70000000 0x0 0x200
=> md 0x70000000 0x200
70000000: 00000000 00000000 00000000 00000000 ................
70000010: 00000000 00000000 00000000 00000000 ................
70000020: 00000000 00000000 00000000 00000000 ................
....
5) Well, now let's read back the data from eMMC from the LBA
we wrote before.
=> mmc read 0x70000000 0x10000 1
MMC read: dev # 0, block # 65536, count 1 ... 1 blocks read: OK
6) We expect the 0x70000000 ~ 0x700000200 should be 0x55aa55aa instead
of 0x0 which is cleared by step 4).
=> md 0x70000000 0x200
70000000: 55aa55aa 55aa55aa 55aa55aa 55aa55aa .U.U.U.U.U.U.U.U
70000010: 55aa55aa 55aa55aa 55aa55aa 55aa55aa .U.U.U.U.U.U.U.U
70000020: 55aa55aa 55aa55aa 55aa55aa 55aa55aa .U.U.U.U.U.U.U.U
70000030: 55aa55aa 55aa55aa 55aa55aa 55aa55aa .U.U.U.U.U.U.U.U
....
Great, we see that the write and read eMMC are finished well and
the data payload is correct as expected!
Change-Id: I9b68c335449550b95f1a8f5841d46821346e45af
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
2017-10-09 09:51:29 +00:00
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/*
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* Currently it supports read/write up to 8*8*4 Bytes per
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* stride as a burst mode. Please note that if you change
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* MAX_STRIDE, you should also update dwmci_memcpy_fromio
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* to augment the groups of {ldm, stm}.
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*/
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#define MAX_STRIDE 64
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#if CONFIG_ARM && CONFIG_CPU_V7
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void noinline dwmci_memcpy_fromio(void *buffer, void *fifo_addr)
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{
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__asm__ __volatile__ (
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"push {r2, r3, r4, r5, r6, r7, r8, r9}\n"
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"ldm r1, {r2,r3,r4,r5,r6,r7,r8,r9}\n"
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"stm r0!, {r2,r3,r4,r5,r6,r7,r8,r9}\n"
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"ldm r1, {r2,r3,r4,r5,r6,r7,r8,r9}\n"
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"stm r0!, {r2,r3,r4,r5,r6,r7,r8,r9}\n"
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"ldm r1, {r2,r3,r4,r5,r6,r7,r8,r9}\n"
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"stm r0!, {r2,r3,r4,r5,r6,r7,r8,r9}\n"
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"ldm r1, {r2,r3,r4,r5,r6,r7,r8,r9}\n"
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"stm r0!, {r2,r3,r4,r5,r6,r7,r8,r9}\n"
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"ldm r1, {r2,r3,r4,r5,r6,r7,r8,r9}\n"
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"stm r0!, {r2,r3,r4,r5,r6,r7,r8,r9}\n"
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"ldm r1, {r2,r3,r4,r5,r6,r7,r8,r9}\n"
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"stm r0!, {r2,r3,r4,r5,r6,r7,r8,r9}\n"
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"ldm r1, {r2,r3,r4,r5,r6,r7,r8,r9}\n"
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"stm r0!, {r2,r3,r4,r5,r6,r7,r8,r9}\n"
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"ldm r1, {r2,r3,r4,r5,r6,r7,r8,r9}\n"
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"stm r0!, {r2,r3,r4,r5,r6,r7,r8,r9}\n"
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"pop {r2, r3, r4, r5, r6,r7,r8,r9}\n"
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:::"memory"
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);
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}
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void noinline dwmci_memcpy_toio(void *buffer, void *fifo_addr)
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{
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2017-10-19 01:39:58 +00:00
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__asm__ __volatile__ (
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"push {r2, r3, r4, r5, r6, r7, r8, r9}\n"
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"ldm r0!, {r2,r3,r4,r5,r6,r7,r8,r9}\n"
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"stm r1, {r2,r3,r4,r5,r6,r7,r8,r9}\n"
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"ldm r0!, {r2,r3,r4,r5,r6,r7,r8,r9}\n"
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"stm r1, {r2,r3,r4,r5,r6,r7,r8,r9}\n"
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"ldm r0!, {r2,r3,r4,r5,r6,r7,r8,r9}\n"
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"stm r1, {r2,r3,r4,r5,r6,r7,r8,r9}\n"
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"ldm r0!, {r2,r3,r4,r5,r6,r7,r8,r9}\n"
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"stm r1, {r2,r3,r4,r5,r6,r7,r8,r9}\n"
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"ldm r0!, {r2,r3,r4,r5,r6,r7,r8,r9}\n"
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"stm r1, {r2,r3,r4,r5,r6,r7,r8,r9}\n"
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"ldm r0!, {r2,r3,r4,r5,r6,r7,r8,r9}\n"
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"stm r1, {r2,r3,r4,r5,r6,r7,r8,r9}\n"
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"ldm r0!, {r2,r3,r4,r5,r6,r7,r8,r9}\n"
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"stm r1, {r2,r3,r4,r5,r6,r7,r8,r9}\n"
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"ldm r0!, {r2,r3,r4,r5,r6,r7,r8,r9}\n"
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"stm r1, {r2,r3,r4,r5,r6,r7,r8,r9}\n"
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"pop {r2, r3, r4, r5, r6,r7,r8,r9}\n"
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:::"memory"
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);
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mmc: dwmmc: Add stride PIO for better burst mode support
This patch enables stride PIO for better burst mode
support on some rockchip platforms, for instance rk3128,
etc. It uses ldm and stm to make multiple accessing from
CPU under some ARM architecture.
Design Note:
1) Carefully test it beyond the armv7(m) core since I don't
test them! If you disassemble the code, dwmci_memcpy_fromio
may be changed to use ldmia.w and stmia.w, as well as some
other optimization for push/pop stack operation, but they
are all fine!
2) Do *NOT* remove noinline and __volatile attributes as
you could fall into trouble by the optimization of GCC.
And please invent new attributes if you use *OTHER* compilers
which have their own keywords claiming the function to be a
"plase don't inline the function and please don't reorder the
groups".
3) If you want to use this feature for other rockchip platforms,
you could append new config in rockchip_dw_mmc.c. But now we only
have CONFIG_ROCKCHIP_RK3128 which means we just enable it for
rk312x platforms.
4) Stride PIO is determined by both of host->stride_pio and
the data payload. The intention of it is to make the block
accessing faster. So now only enable it for who's data payload
is larger(or equal to)than 512 Bytes.
5) MAX_STRIDE means we support burst MAX_STRIDE * 4 Bytes per
stride. Of course you could change that, but please read the
comment before it in the code and do it carefully.
How to test?
1) Prepare a memory, for instance, 0x70000000 on RK3126c.
=> mw 0x70000000 0x55aa55aa 0x200
2) Check it to see if 0x70000000 ~ 0x700000200 are all 0x55aa55aa
=> md 0x70000000 0x200
70000000: 55aa55aa 55aa55aa 55aa55aa 55aa55aa .U.U.U.U.U.U.U.U
70000010: 55aa55aa 55aa55aa 55aa55aa 55aa55aa .U.U.U.U.U.U.U.U
70000020: 55aa55aa 55aa55aa 55aa55aa 55aa55aa .U.U.U.U.U.U.U.U
70000030: 55aa55aa 55aa55aa 55aa55aa 55aa55aa .U.U.U.U.U.U.U.U
....
3) Fetch data of 0x70000000 ~ 0x700000200 and wrrite them to eMMC,
for instance, LBA 0x10000, and blk count is 1 as one blk means 0x200
bytes.
=> mmc write 0x70000000 0x10000 1
MMC write: dev # 0, block # 65536, count 1 ... 1 blocks written: OK
4) Clean the merory buffer and double check it
=> mw 0x70000000 0x0 0x200
=> md 0x70000000 0x200
70000000: 00000000 00000000 00000000 00000000 ................
70000010: 00000000 00000000 00000000 00000000 ................
70000020: 00000000 00000000 00000000 00000000 ................
....
5) Well, now let's read back the data from eMMC from the LBA
we wrote before.
=> mmc read 0x70000000 0x10000 1
MMC read: dev # 0, block # 65536, count 1 ... 1 blocks read: OK
6) We expect the 0x70000000 ~ 0x700000200 should be 0x55aa55aa instead
of 0x0 which is cleared by step 4).
=> md 0x70000000 0x200
70000000: 55aa55aa 55aa55aa 55aa55aa 55aa55aa .U.U.U.U.U.U.U.U
70000010: 55aa55aa 55aa55aa 55aa55aa 55aa55aa .U.U.U.U.U.U.U.U
70000020: 55aa55aa 55aa55aa 55aa55aa 55aa55aa .U.U.U.U.U.U.U.U
70000030: 55aa55aa 55aa55aa 55aa55aa 55aa55aa .U.U.U.U.U.U.U.U
....
Great, we see that the write and read eMMC are finished well and
the data payload is correct as expected!
Change-Id: I9b68c335449550b95f1a8f5841d46821346e45af
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
2017-10-09 09:51:29 +00:00
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}
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#else
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void dwmci_memcpy_fromio(void *buffer, void *fifo_addr) {};
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void dwmci_memcpy_toio(void *buffer, void *fifo_addr) {};
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#endif
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2012-10-15 19:10:29 +00:00
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static int dwmci_wait_reset(struct dwmci_host *host, u32 value)
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{
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unsigned long timeout = 1000;
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u32 ctrl;
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dwmci_writel(host, DWMCI_CTRL, value);
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while (timeout--) {
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ctrl = dwmci_readl(host, DWMCI_CTRL);
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if (!(ctrl & DWMCI_RESET_ALL))
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return 1;
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}
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return 0;
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}
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static void dwmci_set_idma_desc(struct dwmci_idmac *idmac,
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u32 desc0, u32 desc1, u32 desc2)
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{
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struct dwmci_idmac *desc = idmac;
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desc->flags = desc0;
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desc->cnt = desc1;
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desc->addr = desc2;
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2015-10-25 07:48:25 +00:00
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desc->next_addr = (ulong)desc + sizeof(struct dwmci_idmac);
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2012-10-15 19:10:29 +00:00
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}
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static void dwmci_prepare_data(struct dwmci_host *host,
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2013-12-26 11:29:07 +00:00
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struct mmc_data *data,
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struct dwmci_idmac *cur_idmac,
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void *bounce_buffer)
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2012-10-15 19:10:29 +00:00
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{
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unsigned long ctrl;
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unsigned int i = 0, flags, cnt, blk_cnt;
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2013-12-26 11:29:07 +00:00
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ulong data_start, data_end;
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2012-10-15 19:10:29 +00:00
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blk_cnt = data->blocks;
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dwmci_wait_reset(host, DWMCI_CTRL_FIFO_RESET);
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data_start = (ulong)cur_idmac;
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2015-10-25 07:48:25 +00:00
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dwmci_writel(host, DWMCI_DBADDR, (ulong)cur_idmac);
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2012-10-15 19:10:29 +00:00
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do {
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flags = DWMCI_IDMAC_OWN | DWMCI_IDMAC_CH ;
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flags |= (i == 0) ? DWMCI_IDMAC_FS : 0;
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if (blk_cnt <= 8) {
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flags |= DWMCI_IDMAC_LD;
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cnt = data->blocksize * blk_cnt;
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} else
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cnt = data->blocksize * 8;
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dwmci_set_idma_desc(cur_idmac, flags, cnt,
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2015-10-25 07:48:25 +00:00
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(ulong)bounce_buffer + (i * PAGE_SIZE));
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2012-10-15 19:10:29 +00:00
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2013-07-26 14:18:40 +00:00
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if (blk_cnt <= 8)
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2012-10-15 19:10:29 +00:00
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break;
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blk_cnt -= 8;
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cur_idmac++;
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i++;
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} while(1);
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data_end = (ulong)cur_idmac;
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flush_dcache_range(data_start, data_end + ARCH_DMA_MINALIGN);
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ctrl = dwmci_readl(host, DWMCI_CTRL);
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ctrl |= DWMCI_IDMAC_EN | DWMCI_DMA_EN;
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dwmci_writel(host, DWMCI_CTRL, ctrl);
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ctrl = dwmci_readl(host, DWMCI_BMOD);
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ctrl |= DWMCI_BMOD_IDMAC_FB | DWMCI_BMOD_IDMAC_EN;
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dwmci_writel(host, DWMCI_BMOD, ctrl);
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dwmci_writel(host, DWMCI_BLKSIZ, data->blocksize);
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dwmci_writel(host, DWMCI_BYTCNT, data->blocksize * data->blocks);
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}
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2015-11-17 06:20:22 +00:00
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static int dwmci_data_transfer(struct dwmci_host *host, struct mmc_data *data)
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2015-11-17 06:20:21 +00:00
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{
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int ret = 0;
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2015-11-17 06:20:22 +00:00
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u32 timeout = 240000;
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2017-05-15 06:07:14 +00:00
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u32 status, ctrl, mask, size, i, len = 0;
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2015-11-17 06:20:22 +00:00
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u32 *buf = NULL;
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2015-11-17 06:20:21 +00:00
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ulong start = get_timer(0);
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2015-11-17 06:20:22 +00:00
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u32 fifo_depth = (((host->fifoth_val & RX_WMARK_MASK) >>
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RX_WMARK_SHIFT) + 1) * 2;
|
mmc: dwmmc: Add stride PIO for better burst mode support
This patch enables stride PIO for better burst mode
support on some rockchip platforms, for instance rk3128,
etc. It uses ldm and stm to make multiple accessing from
CPU under some ARM architecture.
Design Note:
1) Carefully test it beyond the armv7(m) core since I don't
test them! If you disassemble the code, dwmci_memcpy_fromio
may be changed to use ldmia.w and stmia.w, as well as some
other optimization for push/pop stack operation, but they
are all fine!
2) Do *NOT* remove noinline and __volatile attributes as
you could fall into trouble by the optimization of GCC.
And please invent new attributes if you use *OTHER* compilers
which have their own keywords claiming the function to be a
"plase don't inline the function and please don't reorder the
groups".
3) If you want to use this feature for other rockchip platforms,
you could append new config in rockchip_dw_mmc.c. But now we only
have CONFIG_ROCKCHIP_RK3128 which means we just enable it for
rk312x platforms.
4) Stride PIO is determined by both of host->stride_pio and
the data payload. The intention of it is to make the block
accessing faster. So now only enable it for who's data payload
is larger(or equal to)than 512 Bytes.
5) MAX_STRIDE means we support burst MAX_STRIDE * 4 Bytes per
stride. Of course you could change that, but please read the
comment before it in the code and do it carefully.
How to test?
1) Prepare a memory, for instance, 0x70000000 on RK3126c.
=> mw 0x70000000 0x55aa55aa 0x200
2) Check it to see if 0x70000000 ~ 0x700000200 are all 0x55aa55aa
=> md 0x70000000 0x200
70000000: 55aa55aa 55aa55aa 55aa55aa 55aa55aa .U.U.U.U.U.U.U.U
70000010: 55aa55aa 55aa55aa 55aa55aa 55aa55aa .U.U.U.U.U.U.U.U
70000020: 55aa55aa 55aa55aa 55aa55aa 55aa55aa .U.U.U.U.U.U.U.U
70000030: 55aa55aa 55aa55aa 55aa55aa 55aa55aa .U.U.U.U.U.U.U.U
....
3) Fetch data of 0x70000000 ~ 0x700000200 and wrrite them to eMMC,
for instance, LBA 0x10000, and blk count is 1 as one blk means 0x200
bytes.
=> mmc write 0x70000000 0x10000 1
MMC write: dev # 0, block # 65536, count 1 ... 1 blocks written: OK
4) Clean the merory buffer and double check it
=> mw 0x70000000 0x0 0x200
=> md 0x70000000 0x200
70000000: 00000000 00000000 00000000 00000000 ................
70000010: 00000000 00000000 00000000 00000000 ................
70000020: 00000000 00000000 00000000 00000000 ................
....
5) Well, now let's read back the data from eMMC from the LBA
we wrote before.
=> mmc read 0x70000000 0x10000 1
MMC read: dev # 0, block # 65536, count 1 ... 1 blocks read: OK
6) We expect the 0x70000000 ~ 0x700000200 should be 0x55aa55aa instead
of 0x0 which is cleared by step 4).
=> md 0x70000000 0x200
70000000: 55aa55aa 55aa55aa 55aa55aa 55aa55aa .U.U.U.U.U.U.U.U
70000010: 55aa55aa 55aa55aa 55aa55aa 55aa55aa .U.U.U.U.U.U.U.U
70000020: 55aa55aa 55aa55aa 55aa55aa 55aa55aa .U.U.U.U.U.U.U.U
70000030: 55aa55aa 55aa55aa 55aa55aa 55aa55aa .U.U.U.U.U.U.U.U
....
Great, we see that the write and read eMMC are finished well and
the data payload is correct as expected!
Change-Id: I9b68c335449550b95f1a8f5841d46821346e45af
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
2017-10-09 09:51:29 +00:00
|
|
|
bool stride;
|
2015-11-17 06:20:22 +00:00
|
|
|
|
|
|
|
|
size = data->blocksize * data->blocks / 4;
|
mmc: dwmmc: Add stride PIO for better burst mode support
This patch enables stride PIO for better burst mode
support on some rockchip platforms, for instance rk3128,
etc. It uses ldm and stm to make multiple accessing from
CPU under some ARM architecture.
Design Note:
1) Carefully test it beyond the armv7(m) core since I don't
test them! If you disassemble the code, dwmci_memcpy_fromio
may be changed to use ldmia.w and stmia.w, as well as some
other optimization for push/pop stack operation, but they
are all fine!
2) Do *NOT* remove noinline and __volatile attributes as
you could fall into trouble by the optimization of GCC.
And please invent new attributes if you use *OTHER* compilers
which have their own keywords claiming the function to be a
"plase don't inline the function and please don't reorder the
groups".
3) If you want to use this feature for other rockchip platforms,
you could append new config in rockchip_dw_mmc.c. But now we only
have CONFIG_ROCKCHIP_RK3128 which means we just enable it for
rk312x platforms.
4) Stride PIO is determined by both of host->stride_pio and
the data payload. The intention of it is to make the block
accessing faster. So now only enable it for who's data payload
is larger(or equal to)than 512 Bytes.
5) MAX_STRIDE means we support burst MAX_STRIDE * 4 Bytes per
stride. Of course you could change that, but please read the
comment before it in the code and do it carefully.
How to test?
1) Prepare a memory, for instance, 0x70000000 on RK3126c.
=> mw 0x70000000 0x55aa55aa 0x200
2) Check it to see if 0x70000000 ~ 0x700000200 are all 0x55aa55aa
=> md 0x70000000 0x200
70000000: 55aa55aa 55aa55aa 55aa55aa 55aa55aa .U.U.U.U.U.U.U.U
70000010: 55aa55aa 55aa55aa 55aa55aa 55aa55aa .U.U.U.U.U.U.U.U
70000020: 55aa55aa 55aa55aa 55aa55aa 55aa55aa .U.U.U.U.U.U.U.U
70000030: 55aa55aa 55aa55aa 55aa55aa 55aa55aa .U.U.U.U.U.U.U.U
....
3) Fetch data of 0x70000000 ~ 0x700000200 and wrrite them to eMMC,
for instance, LBA 0x10000, and blk count is 1 as one blk means 0x200
bytes.
=> mmc write 0x70000000 0x10000 1
MMC write: dev # 0, block # 65536, count 1 ... 1 blocks written: OK
4) Clean the merory buffer and double check it
=> mw 0x70000000 0x0 0x200
=> md 0x70000000 0x200
70000000: 00000000 00000000 00000000 00000000 ................
70000010: 00000000 00000000 00000000 00000000 ................
70000020: 00000000 00000000 00000000 00000000 ................
....
5) Well, now let's read back the data from eMMC from the LBA
we wrote before.
=> mmc read 0x70000000 0x10000 1
MMC read: dev # 0, block # 65536, count 1 ... 1 blocks read: OK
6) We expect the 0x70000000 ~ 0x700000200 should be 0x55aa55aa instead
of 0x0 which is cleared by step 4).
=> md 0x70000000 0x200
70000000: 55aa55aa 55aa55aa 55aa55aa 55aa55aa .U.U.U.U.U.U.U.U
70000010: 55aa55aa 55aa55aa 55aa55aa 55aa55aa .U.U.U.U.U.U.U.U
70000020: 55aa55aa 55aa55aa 55aa55aa 55aa55aa .U.U.U.U.U.U.U.U
70000030: 55aa55aa 55aa55aa 55aa55aa 55aa55aa .U.U.U.U.U.U.U.U
....
Great, we see that the write and read eMMC are finished well and
the data payload is correct as expected!
Change-Id: I9b68c335449550b95f1a8f5841d46821346e45af
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
2017-10-09 09:51:29 +00:00
|
|
|
/* Still use legacy PIO mode if size < 512(128 * 4) Bytes */
|
|
|
|
|
stride = host->stride_pio && size > 128;
|
2015-11-17 06:20:22 +00:00
|
|
|
if (data->flags == MMC_DATA_READ)
|
|
|
|
|
buf = (unsigned int *)data->dest;
|
|
|
|
|
else
|
|
|
|
|
buf = (unsigned int *)data->src;
|
2015-11-17 06:20:21 +00:00
|
|
|
|
|
|
|
|
for (;;) {
|
|
|
|
|
mask = dwmci_readl(host, DWMCI_RINTSTS);
|
|
|
|
|
/* Error during data transfer. */
|
|
|
|
|
if (mask & (DWMCI_DATA_ERR | DWMCI_DATA_TOUT)) {
|
|
|
|
|
debug("%s: DATA ERROR!\n", __func__);
|
2017-05-15 06:07:14 +00:00
|
|
|
|
|
|
|
|
dwmci_wait_reset(host, DWMCI_RESET_ALL);
|
|
|
|
|
dwmci_writel(host, DWMCI_CMD, DWMCI_CMD_PRV_DAT_WAIT |
|
|
|
|
|
DWMCI_CMD_UPD_CLK | DWMCI_CMD_START);
|
|
|
|
|
|
|
|
|
|
do {
|
|
|
|
|
status = dwmci_readl(host, DWMCI_CMD);
|
|
|
|
|
if (timeout-- < 0)
|
|
|
|
|
ret = -ETIMEDOUT;
|
|
|
|
|
} while (status & DWMCI_CMD_START);
|
|
|
|
|
|
|
|
|
|
if (!host->fifo_mode) {
|
|
|
|
|
ctrl = dwmci_readl(host, DWMCI_BMOD);
|
|
|
|
|
ctrl |= DWMCI_BMOD_IDMAC_RESET;
|
|
|
|
|
dwmci_writel(host, DWMCI_BMOD, ctrl);
|
|
|
|
|
}
|
|
|
|
|
|
2015-11-17 06:20:21 +00:00
|
|
|
ret = -EINVAL;
|
|
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
|
2015-11-17 06:20:22 +00:00
|
|
|
if (host->fifo_mode && size) {
|
2016-07-28 02:25:48 +00:00
|
|
|
len = 0;
|
2016-09-19 02:16:50 +00:00
|
|
|
if (data->flags == MMC_DATA_READ &&
|
|
|
|
|
(mask & DWMCI_INTMSK_RXDR)) {
|
|
|
|
|
while (size) {
|
2015-11-17 06:20:22 +00:00
|
|
|
len = dwmci_readl(host, DWMCI_STATUS);
|
|
|
|
|
len = (len >> DWMCI_FIFO_SHIFT) &
|
|
|
|
|
DWMCI_FIFO_MASK;
|
2016-07-28 02:25:47 +00:00
|
|
|
len = min(size, len);
|
mmc: dwmmc: Add stride PIO for better burst mode support
This patch enables stride PIO for better burst mode
support on some rockchip platforms, for instance rk3128,
etc. It uses ldm and stm to make multiple accessing from
CPU under some ARM architecture.
Design Note:
1) Carefully test it beyond the armv7(m) core since I don't
test them! If you disassemble the code, dwmci_memcpy_fromio
may be changed to use ldmia.w and stmia.w, as well as some
other optimization for push/pop stack operation, but they
are all fine!
2) Do *NOT* remove noinline and __volatile attributes as
you could fall into trouble by the optimization of GCC.
And please invent new attributes if you use *OTHER* compilers
which have their own keywords claiming the function to be a
"plase don't inline the function and please don't reorder the
groups".
3) If you want to use this feature for other rockchip platforms,
you could append new config in rockchip_dw_mmc.c. But now we only
have CONFIG_ROCKCHIP_RK3128 which means we just enable it for
rk312x platforms.
4) Stride PIO is determined by both of host->stride_pio and
the data payload. The intention of it is to make the block
accessing faster. So now only enable it for who's data payload
is larger(or equal to)than 512 Bytes.
5) MAX_STRIDE means we support burst MAX_STRIDE * 4 Bytes per
stride. Of course you could change that, but please read the
comment before it in the code and do it carefully.
How to test?
1) Prepare a memory, for instance, 0x70000000 on RK3126c.
=> mw 0x70000000 0x55aa55aa 0x200
2) Check it to see if 0x70000000 ~ 0x700000200 are all 0x55aa55aa
=> md 0x70000000 0x200
70000000: 55aa55aa 55aa55aa 55aa55aa 55aa55aa .U.U.U.U.U.U.U.U
70000010: 55aa55aa 55aa55aa 55aa55aa 55aa55aa .U.U.U.U.U.U.U.U
70000020: 55aa55aa 55aa55aa 55aa55aa 55aa55aa .U.U.U.U.U.U.U.U
70000030: 55aa55aa 55aa55aa 55aa55aa 55aa55aa .U.U.U.U.U.U.U.U
....
3) Fetch data of 0x70000000 ~ 0x700000200 and wrrite them to eMMC,
for instance, LBA 0x10000, and blk count is 1 as one blk means 0x200
bytes.
=> mmc write 0x70000000 0x10000 1
MMC write: dev # 0, block # 65536, count 1 ... 1 blocks written: OK
4) Clean the merory buffer and double check it
=> mw 0x70000000 0x0 0x200
=> md 0x70000000 0x200
70000000: 00000000 00000000 00000000 00000000 ................
70000010: 00000000 00000000 00000000 00000000 ................
70000020: 00000000 00000000 00000000 00000000 ................
....
5) Well, now let's read back the data from eMMC from the LBA
we wrote before.
=> mmc read 0x70000000 0x10000 1
MMC read: dev # 0, block # 65536, count 1 ... 1 blocks read: OK
6) We expect the 0x70000000 ~ 0x700000200 should be 0x55aa55aa instead
of 0x0 which is cleared by step 4).
=> md 0x70000000 0x200
70000000: 55aa55aa 55aa55aa 55aa55aa 55aa55aa .U.U.U.U.U.U.U.U
70000010: 55aa55aa 55aa55aa 55aa55aa 55aa55aa .U.U.U.U.U.U.U.U
70000020: 55aa55aa 55aa55aa 55aa55aa 55aa55aa .U.U.U.U.U.U.U.U
70000030: 55aa55aa 55aa55aa 55aa55aa 55aa55aa .U.U.U.U.U.U.U.U
....
Great, we see that the write and read eMMC are finished well and
the data payload is correct as expected!
Change-Id: I9b68c335449550b95f1a8f5841d46821346e45af
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
2017-10-09 09:51:29 +00:00
|
|
|
if (!stride) {
|
|
|
|
|
/* Legacy pio mode */
|
|
|
|
|
for (i = 0; i < len; i++)
|
|
|
|
|
*buf++ = dwmci_readl(host, DWMCI_DATA);
|
|
|
|
|
goto read_again;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* dwmci_memcpy_fromio now bursts 256 Bytes once */
|
|
|
|
|
if (len < MAX_STRIDE)
|
|
|
|
|
continue;
|
|
|
|
|
|
|
|
|
|
for (i = 0; i < len / MAX_STRIDE; i++) {
|
|
|
|
|
dwmci_memcpy_fromio(buf, host->ioaddr + DWMCI_DATA);
|
|
|
|
|
buf += MAX_STRIDE;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
len = i * MAX_STRIDE;
|
|
|
|
|
read_again:
|
2016-09-19 02:16:50 +00:00
|
|
|
size = size > len ? (size - len) : 0;
|
2015-11-17 06:20:22 +00:00
|
|
|
}
|
2016-09-19 02:16:50 +00:00
|
|
|
dwmci_writel(host, DWMCI_RINTSTS,
|
|
|
|
|
DWMCI_INTMSK_RXDR);
|
|
|
|
|
} else if (data->flags == MMC_DATA_WRITE &&
|
|
|
|
|
(mask & DWMCI_INTMSK_TXDR)) {
|
|
|
|
|
while (size) {
|
2015-11-17 06:20:22 +00:00
|
|
|
len = dwmci_readl(host, DWMCI_STATUS);
|
|
|
|
|
len = fifo_depth - ((len >>
|
|
|
|
|
DWMCI_FIFO_SHIFT) &
|
|
|
|
|
DWMCI_FIFO_MASK);
|
2016-07-28 02:25:47 +00:00
|
|
|
len = min(size, len);
|
mmc: dwmmc: Add stride PIO for better burst mode support
This patch enables stride PIO for better burst mode
support on some rockchip platforms, for instance rk3128,
etc. It uses ldm and stm to make multiple accessing from
CPU under some ARM architecture.
Design Note:
1) Carefully test it beyond the armv7(m) core since I don't
test them! If you disassemble the code, dwmci_memcpy_fromio
may be changed to use ldmia.w and stmia.w, as well as some
other optimization for push/pop stack operation, but they
are all fine!
2) Do *NOT* remove noinline and __volatile attributes as
you could fall into trouble by the optimization of GCC.
And please invent new attributes if you use *OTHER* compilers
which have their own keywords claiming the function to be a
"plase don't inline the function and please don't reorder the
groups".
3) If you want to use this feature for other rockchip platforms,
you could append new config in rockchip_dw_mmc.c. But now we only
have CONFIG_ROCKCHIP_RK3128 which means we just enable it for
rk312x platforms.
4) Stride PIO is determined by both of host->stride_pio and
the data payload. The intention of it is to make the block
accessing faster. So now only enable it for who's data payload
is larger(or equal to)than 512 Bytes.
5) MAX_STRIDE means we support burst MAX_STRIDE * 4 Bytes per
stride. Of course you could change that, but please read the
comment before it in the code and do it carefully.
How to test?
1) Prepare a memory, for instance, 0x70000000 on RK3126c.
=> mw 0x70000000 0x55aa55aa 0x200
2) Check it to see if 0x70000000 ~ 0x700000200 are all 0x55aa55aa
=> md 0x70000000 0x200
70000000: 55aa55aa 55aa55aa 55aa55aa 55aa55aa .U.U.U.U.U.U.U.U
70000010: 55aa55aa 55aa55aa 55aa55aa 55aa55aa .U.U.U.U.U.U.U.U
70000020: 55aa55aa 55aa55aa 55aa55aa 55aa55aa .U.U.U.U.U.U.U.U
70000030: 55aa55aa 55aa55aa 55aa55aa 55aa55aa .U.U.U.U.U.U.U.U
....
3) Fetch data of 0x70000000 ~ 0x700000200 and wrrite them to eMMC,
for instance, LBA 0x10000, and blk count is 1 as one blk means 0x200
bytes.
=> mmc write 0x70000000 0x10000 1
MMC write: dev # 0, block # 65536, count 1 ... 1 blocks written: OK
4) Clean the merory buffer and double check it
=> mw 0x70000000 0x0 0x200
=> md 0x70000000 0x200
70000000: 00000000 00000000 00000000 00000000 ................
70000010: 00000000 00000000 00000000 00000000 ................
70000020: 00000000 00000000 00000000 00000000 ................
....
5) Well, now let's read back the data from eMMC from the LBA
we wrote before.
=> mmc read 0x70000000 0x10000 1
MMC read: dev # 0, block # 65536, count 1 ... 1 blocks read: OK
6) We expect the 0x70000000 ~ 0x700000200 should be 0x55aa55aa instead
of 0x0 which is cleared by step 4).
=> md 0x70000000 0x200
70000000: 55aa55aa 55aa55aa 55aa55aa 55aa55aa .U.U.U.U.U.U.U.U
70000010: 55aa55aa 55aa55aa 55aa55aa 55aa55aa .U.U.U.U.U.U.U.U
70000020: 55aa55aa 55aa55aa 55aa55aa 55aa55aa .U.U.U.U.U.U.U.U
70000030: 55aa55aa 55aa55aa 55aa55aa 55aa55aa .U.U.U.U.U.U.U.U
....
Great, we see that the write and read eMMC are finished well and
the data payload is correct as expected!
Change-Id: I9b68c335449550b95f1a8f5841d46821346e45af
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
2017-10-09 09:51:29 +00:00
|
|
|
if (!stride) {
|
|
|
|
|
for (i = 0; i < len; i++)
|
|
|
|
|
dwmci_writel(host, DWMCI_DATA,
|
|
|
|
|
*buf++);
|
|
|
|
|
goto write_again;
|
|
|
|
|
}
|
|
|
|
|
/* dwmci_memcpy_toio now bursts 256 Bytes once */
|
|
|
|
|
if (len < MAX_STRIDE)
|
|
|
|
|
continue;
|
|
|
|
|
|
|
|
|
|
for (i = 0; i < len / MAX_STRIDE; i++) {
|
|
|
|
|
dwmci_memcpy_toio(buf, host->ioaddr + DWMCI_DATA);
|
|
|
|
|
buf += MAX_STRIDE;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
len = i * MAX_STRIDE;
|
|
|
|
|
write_again:
|
2016-09-19 02:16:50 +00:00
|
|
|
size = size > len ? (size - len) : 0;
|
2015-11-17 06:20:22 +00:00
|
|
|
}
|
2016-09-19 02:16:50 +00:00
|
|
|
dwmci_writel(host, DWMCI_RINTSTS,
|
|
|
|
|
DWMCI_INTMSK_TXDR);
|
2015-11-17 06:20:22 +00:00
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
2015-11-17 06:20:21 +00:00
|
|
|
/* Data arrived correctly. */
|
|
|
|
|
if (mask & DWMCI_INTMSK_DTO) {
|
|
|
|
|
ret = 0;
|
|
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* Check for timeout. */
|
|
|
|
|
if (get_timer(start) > timeout) {
|
|
|
|
|
debug("%s: Timeout waiting for data!\n",
|
|
|
|
|
__func__);
|
2016-07-19 07:33:36 +00:00
|
|
|
ret = -ETIMEDOUT;
|
2015-11-17 06:20:21 +00:00
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
dwmci_writel(host, DWMCI_RINTSTS, mask);
|
|
|
|
|
|
|
|
|
|
return ret;
|
|
|
|
|
}
|
|
|
|
|
|
2012-10-15 19:10:29 +00:00
|
|
|
static int dwmci_set_transfer_mode(struct dwmci_host *host,
|
|
|
|
|
struct mmc_data *data)
|
|
|
|
|
{
|
|
|
|
|
unsigned long mode;
|
|
|
|
|
|
|
|
|
|
mode = DWMCI_CMD_DATA_EXP;
|
|
|
|
|
if (data->flags & MMC_DATA_WRITE)
|
|
|
|
|
mode |= DWMCI_CMD_RW;
|
|
|
|
|
|
|
|
|
|
return mode;
|
|
|
|
|
}
|
|
|
|
|
|
2017-07-29 17:35:31 +00:00
|
|
|
#ifdef CONFIG_DM_MMC
|
2016-06-28 06:52:21 +00:00
|
|
|
static int dwmci_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
|
2016-06-13 05:30:23 +00:00
|
|
|
struct mmc_data *data)
|
|
|
|
|
{
|
|
|
|
|
struct mmc *mmc = mmc_get_mmc_dev(dev);
|
|
|
|
|
#else
|
2012-10-15 19:10:29 +00:00
|
|
|
static int dwmci_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
|
|
|
|
|
struct mmc_data *data)
|
|
|
|
|
{
|
2016-06-13 05:30:23 +00:00
|
|
|
#endif
|
2014-03-11 17:34:20 +00:00
|
|
|
struct dwmci_host *host = mmc->priv;
|
2013-07-26 12:08:14 +00:00
|
|
|
ALLOC_CACHE_ALIGN_BUFFER(struct dwmci_idmac, cur_idmac,
|
2013-07-26 14:18:40 +00:00
|
|
|
data ? DIV_ROUND_UP(data->blocks, 8) : 0);
|
2015-07-27 20:39:38 +00:00
|
|
|
int ret = 0, flags = 0, i;
|
2016-07-19 01:38:22 +00:00
|
|
|
unsigned int timeout = 500;
|
2016-03-04 00:09:52 +00:00
|
|
|
u32 retry = 100000;
|
2012-10-15 19:10:29 +00:00
|
|
|
u32 mask, ctrl;
|
2013-04-27 06:12:54 +00:00
|
|
|
ulong start = get_timer(0);
|
2013-12-26 11:29:07 +00:00
|
|
|
struct bounce_buffer bbstate;
|
2012-10-15 19:10:29 +00:00
|
|
|
|
|
|
|
|
while (dwmci_readl(host, DWMCI_STATUS) & DWMCI_BUSY) {
|
2013-04-27 06:12:54 +00:00
|
|
|
if (get_timer(start) > timeout) {
|
2015-08-07 02:16:27 +00:00
|
|
|
debug("%s: Timeout on data busy\n", __func__);
|
2016-07-19 07:33:36 +00:00
|
|
|
return -ETIMEDOUT;
|
2012-10-15 19:10:29 +00:00
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
dwmci_writel(host, DWMCI_RINTSTS, DWMCI_INTMSK_ALL);
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|
|
|
|
|
2013-12-26 11:29:07 +00:00
|
|
|
if (data) {
|
2015-11-17 06:20:22 +00:00
|
|
|
if (host->fifo_mode) {
|
|
|
|
|
dwmci_writel(host, DWMCI_BLKSIZ, data->blocksize);
|
|
|
|
|
dwmci_writel(host, DWMCI_BYTCNT,
|
|
|
|
|
data->blocksize * data->blocks);
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|
|
|
|
dwmci_wait_reset(host, DWMCI_CTRL_FIFO_RESET);
|
2013-12-26 11:29:07 +00:00
|
|
|
} else {
|
2015-11-17 06:20:22 +00:00
|
|
|
if (data->flags == MMC_DATA_READ) {
|
|
|
|
|
bounce_buffer_start(&bbstate, (void*)data->dest,
|
|
|
|
|
data->blocksize *
|
|
|
|
|
data->blocks, GEN_BB_WRITE);
|
|
|
|
|
} else {
|
|
|
|
|
bounce_buffer_start(&bbstate, (void*)data->src,
|
|
|
|
|
data->blocksize *
|
|
|
|
|
data->blocks, GEN_BB_READ);
|
|
|
|
|
}
|
|
|
|
|
dwmci_prepare_data(host, data, cur_idmac,
|
|
|
|
|
bbstate.bounce_buffer);
|
2013-12-26 11:29:07 +00:00
|
|
|
}
|
|
|
|
|
}
|
2012-10-15 19:10:29 +00:00
|
|
|
|
|
|
|
|
dwmci_writel(host, DWMCI_CMDARG, cmd->cmdarg);
|
|
|
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|
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|
|
|
if (data)
|
|
|
|
|
flags = dwmci_set_transfer_mode(host, data);
|
|
|
|
|
|
|
|
|
|
if ((cmd->resp_type & MMC_RSP_136) && (cmd->resp_type & MMC_RSP_BUSY))
|
|
|
|
|
return -1;
|
|
|
|
|
|
|
|
|
|
if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
|
|
|
|
|
flags |= DWMCI_CMD_ABORT_STOP;
|
|
|
|
|
else
|
|
|
|
|
flags |= DWMCI_CMD_PRV_DAT_WAIT;
|
|
|
|
|
|
|
|
|
|
if (cmd->resp_type & MMC_RSP_PRESENT) {
|
|
|
|
|
flags |= DWMCI_CMD_RESP_EXP;
|
|
|
|
|
if (cmd->resp_type & MMC_RSP_136)
|
|
|
|
|
flags |= DWMCI_CMD_RESP_LENGTH;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
if (cmd->resp_type & MMC_RSP_CRC)
|
|
|
|
|
flags |= DWMCI_CMD_CHECK_CRC;
|
|
|
|
|
|
|
|
|
|
flags |= (cmd->cmdidx | DWMCI_CMD_START | DWMCI_CMD_USE_HOLD_REG);
|
|
|
|
|
|
|
|
|
|
debug("Sending CMD%d\n",cmd->cmdidx);
|
|
|
|
|
|
|
|
|
|
dwmci_writel(host, DWMCI_CMD, flags);
|
|
|
|
|
|
|
|
|
|
for (i = 0; i < retry; i++) {
|
|
|
|
|
mask = dwmci_readl(host, DWMCI_RINTSTS);
|
|
|
|
|
if (mask & DWMCI_INTMSK_CDONE) {
|
|
|
|
|
if (!data)
|
|
|
|
|
dwmci_writel(host, DWMCI_RINTSTS, mask);
|
|
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
2014-09-05 10:49:48 +00:00
|
|
|
if (i == retry) {
|
2015-08-07 02:16:27 +00:00
|
|
|
debug("%s: Timeout.\n", __func__);
|
2016-07-19 07:33:36 +00:00
|
|
|
return -ETIMEDOUT;
|
2014-09-05 10:49:48 +00:00
|
|
|
}
|
2012-10-15 19:10:29 +00:00
|
|
|
|
|
|
|
|
if (mask & DWMCI_INTMSK_RTO) {
|
2014-09-05 10:49:48 +00:00
|
|
|
/*
|
|
|
|
|
* Timeout here is not necessarily fatal. (e)MMC cards
|
|
|
|
|
* will splat here when they receive CMD55 as they do
|
|
|
|
|
* not support this command and that is exactly the way
|
|
|
|
|
* to tell them apart from SD cards. Thus, this output
|
|
|
|
|
* below shall be debug(). eMMC cards also do not favor
|
|
|
|
|
* CMD8, please keep that in mind.
|
|
|
|
|
*/
|
|
|
|
|
debug("%s: Response Timeout.\n", __func__);
|
2016-07-19 07:33:36 +00:00
|
|
|
return -ETIMEDOUT;
|
2012-10-15 19:10:29 +00:00
|
|
|
} else if (mask & DWMCI_INTMSK_RE) {
|
2015-08-07 02:16:27 +00:00
|
|
|
debug("%s: Response Error.\n", __func__);
|
|
|
|
|
return -EIO;
|
2012-10-15 19:10:29 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
if (cmd->resp_type & MMC_RSP_PRESENT) {
|
|
|
|
|
if (cmd->resp_type & MMC_RSP_136) {
|
|
|
|
|
cmd->response[0] = dwmci_readl(host, DWMCI_RESP3);
|
|
|
|
|
cmd->response[1] = dwmci_readl(host, DWMCI_RESP2);
|
|
|
|
|
cmd->response[2] = dwmci_readl(host, DWMCI_RESP1);
|
|
|
|
|
cmd->response[3] = dwmci_readl(host, DWMCI_RESP0);
|
|
|
|
|
} else {
|
|
|
|
|
cmd->response[0] = dwmci_readl(host, DWMCI_RESP0);
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
if (data) {
|
2015-11-17 06:20:22 +00:00
|
|
|
ret = dwmci_data_transfer(host, data);
|
|
|
|
|
|
|
|
|
|
/* only dma mode need it */
|
|
|
|
|
if (!host->fifo_mode) {
|
|
|
|
|
ctrl = dwmci_readl(host, DWMCI_CTRL);
|
|
|
|
|
ctrl &= ~(DWMCI_DMA_EN);
|
|
|
|
|
dwmci_writel(host, DWMCI_CTRL, ctrl);
|
|
|
|
|
bounce_buffer_stop(&bbstate);
|
|
|
|
|
}
|
2012-10-15 19:10:29 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
udelay(100);
|
|
|
|
|
|
2015-07-27 20:39:38 +00:00
|
|
|
return ret;
|
2012-10-15 19:10:29 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static int dwmci_setup_bus(struct dwmci_host *host, u32 freq)
|
|
|
|
|
{
|
|
|
|
|
u32 div, status;
|
|
|
|
|
int timeout = 10000;
|
|
|
|
|
unsigned long sclk;
|
|
|
|
|
|
2017-05-15 06:07:16 +00:00
|
|
|
if (freq == 0)
|
2012-10-15 19:10:29 +00:00
|
|
|
return 0;
|
|
|
|
|
/*
|
2014-09-05 10:49:48 +00:00
|
|
|
* If host->get_mmc_clk isn't defined,
|
2012-10-15 19:10:29 +00:00
|
|
|
* then assume that host->bus_hz is source clock value.
|
2014-09-05 10:49:48 +00:00
|
|
|
* host->bus_hz should be set by user.
|
2012-10-15 19:10:29 +00:00
|
|
|
*/
|
2013-10-06 09:59:31 +00:00
|
|
|
if (host->get_mmc_clk)
|
2015-08-30 22:55:15 +00:00
|
|
|
sclk = host->get_mmc_clk(host, freq);
|
2012-10-15 19:10:29 +00:00
|
|
|
else if (host->bus_hz)
|
|
|
|
|
sclk = host->bus_hz;
|
|
|
|
|
else {
|
2015-08-07 02:16:27 +00:00
|
|
|
debug("%s: Didn't get source clock value.\n", __func__);
|
2012-10-15 19:10:29 +00:00
|
|
|
return -EINVAL;
|
|
|
|
|
}
|
|
|
|
|
|
2014-06-10 06:26:52 +00:00
|
|
|
if (sclk == freq)
|
|
|
|
|
div = 0; /* bypass mode */
|
|
|
|
|
else
|
|
|
|
|
div = DIV_ROUND_UP(sclk, 2 * freq);
|
2012-10-15 19:10:29 +00:00
|
|
|
|
|
|
|
|
dwmci_writel(host, DWMCI_CLKENA, 0);
|
|
|
|
|
dwmci_writel(host, DWMCI_CLKSRC, 0);
|
|
|
|
|
|
|
|
|
|
dwmci_writel(host, DWMCI_CLKDIV, div);
|
|
|
|
|
dwmci_writel(host, DWMCI_CMD, DWMCI_CMD_PRV_DAT_WAIT |
|
|
|
|
|
DWMCI_CMD_UPD_CLK | DWMCI_CMD_START);
|
|
|
|
|
|
|
|
|
|
do {
|
|
|
|
|
status = dwmci_readl(host, DWMCI_CMD);
|
|
|
|
|
if (timeout-- < 0) {
|
2015-08-07 02:16:27 +00:00
|
|
|
debug("%s: Timeout!\n", __func__);
|
2012-10-15 19:10:29 +00:00
|
|
|
return -ETIMEDOUT;
|
|
|
|
|
}
|
|
|
|
|
} while (status & DWMCI_CMD_START);
|
|
|
|
|
|
|
|
|
|
dwmci_writel(host, DWMCI_CLKENA, DWMCI_CLKEN_ENABLE |
|
|
|
|
|
DWMCI_CLKEN_LOW_PWR);
|
|
|
|
|
|
|
|
|
|
dwmci_writel(host, DWMCI_CMD, DWMCI_CMD_PRV_DAT_WAIT |
|
|
|
|
|
DWMCI_CMD_UPD_CLK | DWMCI_CMD_START);
|
|
|
|
|
|
|
|
|
|
timeout = 10000;
|
|
|
|
|
do {
|
|
|
|
|
status = dwmci_readl(host, DWMCI_CMD);
|
|
|
|
|
if (timeout-- < 0) {
|
2015-08-07 02:16:27 +00:00
|
|
|
debug("%s: Timeout!\n", __func__);
|
2012-10-15 19:10:29 +00:00
|
|
|
return -ETIMEDOUT;
|
|
|
|
|
}
|
|
|
|
|
} while (status & DWMCI_CMD_START);
|
|
|
|
|
|
|
|
|
|
host->clock = freq;
|
|
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
2017-05-15 06:07:01 +00:00
|
|
|
#ifdef CONFIG_DM_MMC
|
|
|
|
|
static bool dwmci_card_busy(struct udevice *dev)
|
|
|
|
|
{
|
|
|
|
|
struct mmc *mmc = mmc_get_mmc_dev(dev);
|
|
|
|
|
#else
|
|
|
|
|
static bool dwmci_card_busy(struct mmc *mmc)
|
|
|
|
|
{
|
|
|
|
|
#endif
|
|
|
|
|
u32 status;
|
|
|
|
|
struct dwmci_host *host = (struct dwmci_host *)mmc->priv;
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* Check the busy bit which is low when DAT[3:0]
|
|
|
|
|
* (the data lines) are 0000
|
|
|
|
|
*/
|
|
|
|
|
status = dwmci_readl(host, DWMCI_STATUS);
|
|
|
|
|
|
|
|
|
|
return !!(status & DWMCI_BUSY);
|
|
|
|
|
}
|
|
|
|
|
|
2017-05-15 06:07:12 +00:00
|
|
|
#ifdef CONFIG_DM_MMC
|
|
|
|
|
static int dwmci_execute_tuning(struct udevice *dev, u32 opcode)
|
|
|
|
|
{
|
|
|
|
|
struct mmc *mmc = mmc_get_mmc_dev(dev);
|
|
|
|
|
#else
|
|
|
|
|
static int dwmci_execute_tuning(struct mmc *mmc, u32 opcode)
|
|
|
|
|
{
|
|
|
|
|
#endif
|
|
|
|
|
struct dwmci_host *host = (struct dwmci_host *)mmc->priv;
|
|
|
|
|
|
|
|
|
|
if (!host->execute_tuning)
|
|
|
|
|
return -EIO;
|
|
|
|
|
|
|
|
|
|
return host->execute_tuning(host, opcode);
|
|
|
|
|
}
|
|
|
|
|
|
2017-07-29 17:35:31 +00:00
|
|
|
#ifdef CONFIG_DM_MMC
|
2016-06-28 06:52:21 +00:00
|
|
|
static int dwmci_set_ios(struct udevice *dev)
|
2016-06-13 05:30:23 +00:00
|
|
|
{
|
|
|
|
|
struct mmc *mmc = mmc_get_mmc_dev(dev);
|
|
|
|
|
#else
|
2016-12-30 06:30:16 +00:00
|
|
|
static int dwmci_set_ios(struct mmc *mmc)
|
2012-10-15 19:10:29 +00:00
|
|
|
{
|
2016-06-13 05:30:23 +00:00
|
|
|
#endif
|
2014-05-16 04:59:55 +00:00
|
|
|
struct dwmci_host *host = (struct dwmci_host *)mmc->priv;
|
|
|
|
|
u32 ctype, regs;
|
2012-10-15 19:10:29 +00:00
|
|
|
|
2014-09-05 10:49:48 +00:00
|
|
|
debug("Buswidth = %d, clock: %d\n", mmc->bus_width, mmc->clock);
|
2012-10-15 19:10:29 +00:00
|
|
|
|
|
|
|
|
dwmci_setup_bus(host, mmc->clock);
|
|
|
|
|
switch (mmc->bus_width) {
|
|
|
|
|
case 8:
|
|
|
|
|
ctype = DWMCI_CTYPE_8BIT;
|
|
|
|
|
break;
|
|
|
|
|
case 4:
|
|
|
|
|
ctype = DWMCI_CTYPE_4BIT;
|
|
|
|
|
break;
|
|
|
|
|
default:
|
|
|
|
|
ctype = DWMCI_CTYPE_1BIT;
|
|
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
dwmci_writel(host, DWMCI_CTYPE, ctype);
|
|
|
|
|
|
2014-05-16 04:59:55 +00:00
|
|
|
regs = dwmci_readl(host, DWMCI_UHS_REG);
|
2017-05-15 06:07:05 +00:00
|
|
|
if (mmc_card_ddr(mmc))
|
2014-05-16 04:59:55 +00:00
|
|
|
regs |= DWMCI_DDR_MODE;
|
|
|
|
|
else
|
2015-01-14 08:37:53 +00:00
|
|
|
regs &= ~DWMCI_DDR_MODE;
|
2014-05-16 04:59:55 +00:00
|
|
|
|
|
|
|
|
dwmci_writel(host, DWMCI_UHS_REG, regs);
|
|
|
|
|
|
2012-10-15 19:10:29 +00:00
|
|
|
if (host->clksel)
|
|
|
|
|
host->clksel(host);
|
2016-12-30 06:30:16 +00:00
|
|
|
|
2016-06-13 05:30:23 +00:00
|
|
|
return 0;
|
2012-10-15 19:10:29 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static int dwmci_init(struct mmc *mmc)
|
|
|
|
|
{
|
2014-03-11 17:34:20 +00:00
|
|
|
struct dwmci_host *host = mmc->priv;
|
2017-08-17 13:15:40 +00:00
|
|
|
uint32_t use_dma;
|
2012-10-15 19:10:29 +00:00
|
|
|
|
2013-11-29 11:08:57 +00:00
|
|
|
if (host->board_init)
|
|
|
|
|
host->board_init(host);
|
2013-10-29 07:23:13 +00:00
|
|
|
|
2012-10-15 19:10:29 +00:00
|
|
|
dwmci_writel(host, DWMCI_PWREN, 1);
|
|
|
|
|
|
|
|
|
|
if (!dwmci_wait_reset(host, DWMCI_RESET_ALL)) {
|
2015-08-07 02:16:27 +00:00
|
|
|
debug("%s[%d] Fail-reset!!\n", __func__, __LINE__);
|
|
|
|
|
return -EIO;
|
2012-10-15 19:10:29 +00:00
|
|
|
}
|
|
|
|
|
|
2017-08-17 13:15:40 +00:00
|
|
|
use_dma = SDMMC_GET_TRANS_MODE(dwmci_readl(host, DWMCI_HCON));
|
|
|
|
|
if (use_dma == DMA_INTERFACE_IDMA) {
|
|
|
|
|
host->fifo_mode = 0;
|
|
|
|
|
} else {
|
|
|
|
|
host->fifo_mode = 1;
|
|
|
|
|
}
|
|
|
|
|
|
2013-04-27 06:12:54 +00:00
|
|
|
/* Enumerate at 400KHz */
|
2014-03-11 17:34:20 +00:00
|
|
|
dwmci_setup_bus(host, mmc->cfg->f_min);
|
2013-04-27 06:12:54 +00:00
|
|
|
|
2012-10-15 19:10:29 +00:00
|
|
|
dwmci_writel(host, DWMCI_RINTSTS, 0xFFFFFFFF);
|
|
|
|
|
dwmci_writel(host, DWMCI_INTMASK, 0);
|
|
|
|
|
|
|
|
|
|
dwmci_writel(host, DWMCI_TMOUT, 0xFFFFFFFF);
|
|
|
|
|
|
|
|
|
|
dwmci_writel(host, DWMCI_IDINTEN, 0);
|
|
|
|
|
dwmci_writel(host, DWMCI_BMOD, 1);
|
|
|
|
|
|
2015-08-07 02:16:29 +00:00
|
|
|
if (!host->fifoth_val) {
|
|
|
|
|
uint32_t fifo_size;
|
|
|
|
|
|
|
|
|
|
fifo_size = dwmci_readl(host, DWMCI_FIFOTH);
|
|
|
|
|
fifo_size = ((fifo_size & RX_WMARK_MASK) >> RX_WMARK_SHIFT) + 1;
|
|
|
|
|
host->fifoth_val = MSIZE(0x2) | RX_WMARK(fifo_size / 2 - 1) |
|
|
|
|
|
TX_WMARK(fifo_size / 2);
|
2013-04-27 06:12:54 +00:00
|
|
|
}
|
2015-08-07 02:16:29 +00:00
|
|
|
dwmci_writel(host, DWMCI_FIFOTH, host->fifoth_val);
|
2012-10-15 19:10:29 +00:00
|
|
|
|
|
|
|
|
dwmci_writel(host, DWMCI_CLKENA, 0);
|
|
|
|
|
dwmci_writel(host, DWMCI_CLKSRC, 0);
|
|
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
2017-07-29 17:35:31 +00:00
|
|
|
#ifdef CONFIG_DM_MMC
|
2016-06-13 05:30:23 +00:00
|
|
|
int dwmci_probe(struct udevice *dev)
|
|
|
|
|
{
|
|
|
|
|
struct mmc *mmc = mmc_get_mmc_dev(dev);
|
|
|
|
|
|
|
|
|
|
return dwmci_init(mmc);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
const struct dm_mmc_ops dm_dwmci_ops = {
|
2017-05-15 06:07:01 +00:00
|
|
|
.card_busy = dwmci_card_busy,
|
2016-06-13 05:30:23 +00:00
|
|
|
.send_cmd = dwmci_send_cmd,
|
|
|
|
|
.set_ios = dwmci_set_ios,
|
2017-05-15 06:07:12 +00:00
|
|
|
.execute_tuning = dwmci_execute_tuning,
|
2016-06-13 05:30:23 +00:00
|
|
|
};
|
|
|
|
|
|
|
|
|
|
#else
|
2014-02-26 17:28:45 +00:00
|
|
|
static const struct mmc_ops dwmci_ops = {
|
2017-05-15 06:07:01 +00:00
|
|
|
.card_busy = dwmci_card_busy,
|
2014-02-26 17:28:45 +00:00
|
|
|
.send_cmd = dwmci_send_cmd,
|
|
|
|
|
.set_ios = dwmci_set_ios,
|
|
|
|
|
.init = dwmci_init,
|
2017-05-15 06:07:12 +00:00
|
|
|
.execute_tuning = dwmci_execute_tuning,
|
2014-02-26 17:28:45 +00:00
|
|
|
};
|
2016-06-13 05:30:23 +00:00
|
|
|
#endif
|
2014-02-26 17:28:45 +00:00
|
|
|
|
2016-09-23 10:13:16 +00:00
|
|
|
void dwmci_setup_cfg(struct mmc_config *cfg, struct dwmci_host *host,
|
|
|
|
|
u32 max_clk, u32 min_clk)
|
2012-10-15 19:10:29 +00:00
|
|
|
{
|
2016-09-23 10:13:16 +00:00
|
|
|
cfg->name = host->name;
|
2017-07-29 17:35:31 +00:00
|
|
|
#ifndef CONFIG_DM_MMC
|
2016-05-14 20:03:07 +00:00
|
|
|
cfg->ops = &dwmci_ops;
|
2016-06-13 05:30:23 +00:00
|
|
|
#endif
|
2016-05-14 20:03:07 +00:00
|
|
|
cfg->f_min = min_clk;
|
|
|
|
|
cfg->f_max = max_clk;
|
2012-10-15 19:10:29 +00:00
|
|
|
|
2016-05-14 20:03:07 +00:00
|
|
|
cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
|
2012-10-15 19:10:29 +00:00
|
|
|
|
2016-09-23 10:13:16 +00:00
|
|
|
cfg->host_caps = host->caps;
|
2012-10-15 19:10:29 +00:00
|
|
|
|
2016-09-23 10:13:16 +00:00
|
|
|
if (host->buswidth == 8) {
|
2017-05-15 06:07:17 +00:00
|
|
|
cfg->host_caps |= MMC_MODE_8BIT | MMC_MODE_4BIT;
|
2012-10-15 19:10:29 +00:00
|
|
|
} else {
|
2016-05-14 20:03:07 +00:00
|
|
|
cfg->host_caps |= MMC_MODE_4BIT;
|
|
|
|
|
cfg->host_caps &= ~MMC_MODE_8BIT;
|
2012-10-15 19:10:29 +00:00
|
|
|
}
|
2016-05-14 20:03:07 +00:00
|
|
|
cfg->host_caps |= MMC_MODE_HS | MMC_MODE_HS_52MHz;
|
|
|
|
|
|
|
|
|
|
cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
|
|
|
|
|
}
|
2014-03-11 17:34:20 +00:00
|
|
|
|
2016-05-14 20:03:07 +00:00
|
|
|
#ifdef CONFIG_BLK
|
|
|
|
|
int dwmci_bind(struct udevice *dev, struct mmc *mmc, struct mmc_config *cfg)
|
|
|
|
|
{
|
|
|
|
|
return mmc_bind(dev, mmc, cfg);
|
|
|
|
|
}
|
|
|
|
|
#else
|
|
|
|
|
int add_dwmci(struct dwmci_host *host, u32 max_clk, u32 min_clk)
|
|
|
|
|
{
|
2016-09-23 10:13:16 +00:00
|
|
|
dwmci_setup_cfg(&host->cfg, host, max_clk, min_clk);
|
2012-10-15 19:10:29 +00:00
|
|
|
|
2014-03-11 17:34:20 +00:00
|
|
|
host->mmc = mmc_create(&host->cfg, host);
|
|
|
|
|
if (host->mmc == NULL)
|
|
|
|
|
return -1;
|
2012-10-15 19:10:29 +00:00
|
|
|
|
2014-03-11 17:34:20 +00:00
|
|
|
return 0;
|
2012-10-15 19:10:29 +00:00
|
|
|
}
|
2016-05-14 20:03:07 +00:00
|
|
|
#endif
|
