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https://git.openwrt.org/openwrt/openwrt.git
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Daniel Golle
18cbd83a14
Import pending series introducing support for standalone PCS drivers. This has previously already been used by the airoha target, and is also the base for the closer-to-upstream patches for MediaTek MT7988 10G SerDes support. In order to not having to diverge from upstream also backport series for standardized handling for PHY and PCS SerDes pair polarity. Signed-off-by: Daniel Golle <daniel@makrotopia.org>
124 lines
4.0 KiB
Diff
124 lines
4.0 KiB
Diff
From 8871389da15165198c3407584d40e7295bceaca5 Mon Sep 17 00:00:00 2001
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From: Vladimir Oltean <vladimir.oltean@nxp.com>
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Date: Mon, 19 Jan 2026 11:12:20 +0200
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Subject: [PATCH 3/3] net: pcs: pcs-mtk-lynxi: deprecate "mediatek,pnswap"
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Prefer the new "rx-polarity" and "tx-polarity" properties, which in this
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case have the advantage that polarity inversion can be specified per
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direction (and per protocol, although this isn't useful here).
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We use the vendor specific ones as fallback if the standard description
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doesn't exist.
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Daniel, referring to the Mediatek SDK, clarifies that the combined
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SGMII_PN_SWAP_TX_RX register field should be split like this: bit 0 is
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TX and bit 1 is RX:
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https://lore.kernel.org/linux-phy/aSW--slbJWpXK0nv@makrotopia.org/
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Suggested-by: Daniel Golle <daniel@makrotopia.org>
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Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
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Link: https://patch.msgid.link/20260119091220.1493761-6-vladimir.oltean@nxp.com
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Signed-off-by: Jakub Kicinski <kuba@kernel.org>
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---
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drivers/net/pcs/Kconfig | 1 +
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drivers/net/pcs/pcs-mtk-lynxi.c | 50 +++++++++++++++++++++++++++++----
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2 files changed, 45 insertions(+), 6 deletions(-)
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--- a/drivers/net/pcs/Kconfig
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+++ b/drivers/net/pcs/Kconfig
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@@ -20,6 +20,7 @@ config PCS_LYNX
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config PCS_MTK_LYNXI
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tristate
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+ select PHY_COMMON_PROPS
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select REGMAP
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help
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This module provides helpers to phylink for managing the LynxI PCS
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--- a/drivers/net/pcs/pcs-mtk-lynxi.c
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+++ b/drivers/net/pcs/pcs-mtk-lynxi.c
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@@ -11,6 +11,7 @@
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#include <linux/mdio.h>
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#include <linux/of.h>
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#include <linux/pcs/pcs-mtk-lynxi.h>
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+#include <linux/phy/phy-common-props.h>
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#include <linux/phylink.h>
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#include <linux/regmap.h>
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@@ -62,8 +63,9 @@
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/* Register to QPHY wrapper control */
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#define SGMSYS_QPHY_WRAP_CTRL 0xec
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-#define SGMII_PN_SWAP_MASK GENMASK(1, 0)
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-#define SGMII_PN_SWAP_TX_RX (BIT(0) | BIT(1))
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+#define SGMII_PN_SWAP_RX BIT(1)
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+#define SGMII_PN_SWAP_TX BIT(0)
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+
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/* struct mtk_pcs_lynxi - This structure holds each sgmii regmap andassociated
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* data
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@@ -119,6 +121,42 @@ static void mtk_pcs_lynxi_get_state(stru
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FIELD_GET(SGMII_LPA, adv));
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}
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+static int mtk_pcs_config_polarity(struct mtk_pcs_lynxi *mpcs,
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+ phy_interface_t interface)
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+{
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+ struct fwnode_handle *fwnode = mpcs->fwnode, *pcs_fwnode;
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+ unsigned int pol, default_pol = PHY_POL_NORMAL;
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+ unsigned int val = 0;
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+ int ret;
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+
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+ if (fwnode_property_read_bool(fwnode, "mediatek,pnswap"))
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+ default_pol = PHY_POL_INVERT;
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+
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+ pcs_fwnode = fwnode_get_named_child_node(fwnode, "pcs");
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+
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+ ret = phy_get_rx_polarity(pcs_fwnode, phy_modes(interface),
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+ BIT(PHY_POL_NORMAL) | BIT(PHY_POL_INVERT),
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+ default_pol, &pol);
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+ if (ret) {
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+ fwnode_handle_put(pcs_fwnode);
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+ return ret;
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+ }
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+ if (pol == PHY_POL_INVERT)
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+ val |= SGMII_PN_SWAP_RX;
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+
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+ ret = phy_get_tx_polarity(pcs_fwnode, phy_modes(interface),
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+ BIT(PHY_POL_NORMAL) | BIT(PHY_POL_INVERT),
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+ default_pol, &pol);
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+ fwnode_handle_put(pcs_fwnode);
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+ if (ret)
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+ return ret;
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+ if (pol == PHY_POL_INVERT)
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+ val |= SGMII_PN_SWAP_TX;
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+
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+ return regmap_update_bits(mpcs->regmap, SGMSYS_QPHY_WRAP_CTRL,
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+ SGMII_PN_SWAP_RX | SGMII_PN_SWAP_TX, val);
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+}
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+
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static int mtk_pcs_lynxi_config(struct phylink_pcs *pcs, unsigned int neg_mode,
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phy_interface_t interface,
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const unsigned long *advertising,
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@@ -128,6 +166,7 @@ static int mtk_pcs_lynxi_config(struct p
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bool mode_changed = false, changed;
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unsigned int rgc3, sgm_mode, bmcr;
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int advertise, link_timer;
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+ int ret;
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advertise = phylink_mii_c22_pcs_encode_advertisement(interface,
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advertising);
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@@ -167,10 +206,9 @@ static int mtk_pcs_lynxi_config(struct p
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regmap_set_bits(mpcs->regmap, SGMSYS_RESERVED_0,
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SGMII_SW_RESET);
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- if (fwnode_property_read_bool(mpcs->fwnode, "mediatek,pnswap"))
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- regmap_update_bits(mpcs->regmap, SGMSYS_QPHY_WRAP_CTRL,
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- SGMII_PN_SWAP_MASK,
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- SGMII_PN_SWAP_TX_RX);
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+ ret = mtk_pcs_config_polarity(mpcs, interface);
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+ if (ret)
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+ return ret;
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if (interface == PHY_INTERFACE_MODE_2500BASEX)
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rgc3 = SGMII_PHY_SPEED_3_125G;
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