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Robert Marko
73c6d07df9
The CPPE buffer manager TDM table contains 98 entries, while the SSDK cppe_port_tdm0_tbl has 96. The first 96 entries match exactly; the trailing CPU ingress and egress pair duplicates the beginning of the circular schedule and makes ARRAY_SIZE program a depth of 98. Drop the duplicate pair so the schedule and depth match SSDK. Link: https://github.com/openwrt/openwrt/pull/24203#issuecomment-5446469623 Signed-off-by: Robert Marko <robimarko@gmail.com>