realtek: dts: rearrange mdio-bus below mdio-controller
The mdio controller got its own dts node with a dedicated bus node.
Until now it still searches the phy nodes in the ethernet node.
Change the driver so it searches the nodes at the right location.
For this to work move the phy nodes in all dts/dtsi over to the new
bus node. Use the following replacement rule:
Replace old full declaration
ðernet0 {
mdio-bus {
...
};
};
and old abbreviated declaration
&mdio {
...
};
simply with the new declaration
&mdio_bus0 {
...
};
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/19986
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
This commit is contained in:
Markus Stockhausen
Hauke Mehrtens
parent
616559b6d3
commit
57b2706845
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@ -75,25 +75,18 @@
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status = "okay";
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};
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ðernet0 {
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mdio: mdio-bus {
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compatible = "realtek,rtl838x-mdio";
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regmap = <ðernet0>;
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#address-cells = <1>;
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#size-cells = <0>;
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&mdio_bus0 {
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INTERNAL_PHY(8)
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INTERNAL_PHY(9)
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INTERNAL_PHY(10)
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INTERNAL_PHY(11)
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INTERNAL_PHY(12)
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INTERNAL_PHY(13)
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INTERNAL_PHY(14)
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INTERNAL_PHY(15)
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INTERNAL_PHY(8)
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INTERNAL_PHY(9)
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INTERNAL_PHY(10)
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INTERNAL_PHY(11)
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INTERNAL_PHY(12)
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INTERNAL_PHY(13)
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INTERNAL_PHY(14)
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INTERNAL_PHY(15)
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INTERNAL_PHY_SDS(24, 4)
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INTERNAL_PHY_SDS(26, 5)
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};
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INTERNAL_PHY_SDS(24, 4)
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INTERNAL_PHY_SDS(26, 5)
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};
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&switch0 {
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@ -174,25 +174,18 @@
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};
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};
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ðernet0 {
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mdio: mdio-bus {
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compatible = "realtek,rtl838x-mdio";
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regmap = <ðernet0>;
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#address-cells = <1>;
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#size-cells = <0>;
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&mdio_bus0 {
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INTERNAL_PHY(8)
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INTERNAL_PHY(9)
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INTERNAL_PHY(10)
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INTERNAL_PHY(11)
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INTERNAL_PHY(12)
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INTERNAL_PHY(13)
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INTERNAL_PHY(14)
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INTERNAL_PHY(15)
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INTERNAL_PHY(8)
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INTERNAL_PHY(9)
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INTERNAL_PHY(10)
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INTERNAL_PHY(11)
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INTERNAL_PHY(12)
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INTERNAL_PHY(13)
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INTERNAL_PHY(14)
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INTERNAL_PHY(15)
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INTERNAL_PHY_SDS(24, 4)
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INTERNAL_PHY_SDS(26, 5)
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};
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INTERNAL_PHY_SDS(24, 4)
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INTERNAL_PHY_SDS(26, 5)
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};
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&switch0 {
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@ -57,25 +57,18 @@
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};
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};
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ðernet0 {
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mdio: mdio-bus {
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compatible = "realtek,rtl838x-mdio";
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regmap = <ðernet0>;
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#address-cells = <1>;
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#size-cells = <0>;
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&mdio_bus0 {
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INTERNAL_PHY(8)
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INTERNAL_PHY(9)
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INTERNAL_PHY(10)
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INTERNAL_PHY(11)
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INTERNAL_PHY(12)
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INTERNAL_PHY(13)
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INTERNAL_PHY(14)
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INTERNAL_PHY(15)
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INTERNAL_PHY(8)
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INTERNAL_PHY(9)
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INTERNAL_PHY(10)
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INTERNAL_PHY(11)
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INTERNAL_PHY(12)
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INTERNAL_PHY(13)
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INTERNAL_PHY(14)
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INTERNAL_PHY(15)
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INTERNAL_PHY_SDS(24, 4)
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INTERNAL_PHY_SDS(26, 5)
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};
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INTERNAL_PHY_SDS(24, 4)
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INTERNAL_PHY_SDS(26, 5)
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};
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&switch0 {
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@ -148,24 +148,17 @@
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status = "okay";
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};
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ðernet0 {
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mdio: mdio-bus {
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compatible = "realtek,rtl838x-mdio";
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regmap = <ðernet0>;
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#address-cells = <1>;
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#size-cells = <0>;
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INTERNAL_PHY(8)
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INTERNAL_PHY(9)
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INTERNAL_PHY(10)
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INTERNAL_PHY(11)
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INTERNAL_PHY(12)
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INTERNAL_PHY(13)
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INTERNAL_PHY(14)
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INTERNAL_PHY(15)
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INTERNAL_PHY_SDS(24, 4)
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INTERNAL_PHY_SDS(26, 5)
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};
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&mdio_bus0 {
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INTERNAL_PHY(8)
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INTERNAL_PHY(9)
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INTERNAL_PHY(10)
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INTERNAL_PHY(11)
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INTERNAL_PHY(12)
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INTERNAL_PHY(13)
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INTERNAL_PHY(14)
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INTERNAL_PHY(15)
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INTERNAL_PHY_SDS(24, 4)
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INTERNAL_PHY_SDS(26, 5)
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};
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&switch0 {
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@ -51,22 +51,15 @@
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};
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};
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ðernet0 {
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mdio: mdio-bus {
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compatible = "realtek,rtl838x-mdio";
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regmap = <ðernet0>;
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#address-cells = <1>;
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#size-cells = <0>;
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INTERNAL_PHY(8)
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INTERNAL_PHY(9)
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INTERNAL_PHY(10)
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INTERNAL_PHY(11)
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INTERNAL_PHY(12)
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INTERNAL_PHY(13)
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INTERNAL_PHY(14)
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INTERNAL_PHY(15)
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};
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&mdio_bus0 {
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INTERNAL_PHY(8)
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INTERNAL_PHY(9)
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INTERNAL_PHY(10)
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INTERNAL_PHY(11)
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INTERNAL_PHY(12)
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INTERNAL_PHY(13)
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INTERNAL_PHY(14)
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INTERNAL_PHY(15)
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};
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&spi0 {
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@ -54,7 +54,7 @@
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status = "okay";
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};
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&mdio {
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&mdio_bus0 {
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EXTERNAL_PHY(16)
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EXTERNAL_PHY(17)
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};
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@ -45,7 +45,7 @@
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status = "okay";
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};
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&mdio {
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&mdio_bus0 {
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EXTERNAL_PHY(16)
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EXTERNAL_PHY(24)
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};
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@ -49,7 +49,7 @@
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status = "okay";
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};
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&mdio {
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&mdio_bus0 {
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INTERNAL_PHY_SDS(24, 4)
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INTERNAL_PHY_SDS(26, 5)
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};
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@ -74,24 +74,17 @@
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};
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};
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ðernet0 {
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mdio-bus {
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compatible = "realtek,rtl838x-mdio";
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regmap = <ðernet0>;
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#address-cells = <1>;
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#size-cells = <0>;
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&mdio_bus0 {
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INTERNAL_PHY(8)
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INTERNAL_PHY(9)
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INTERNAL_PHY(10)
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INTERNAL_PHY(11)
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INTERNAL_PHY(12)
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INTERNAL_PHY(13)
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INTERNAL_PHY(14)
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INTERNAL_PHY(15)
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INTERNAL_PHY(8)
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INTERNAL_PHY(9)
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INTERNAL_PHY(10)
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INTERNAL_PHY(11)
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INTERNAL_PHY(12)
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INTERNAL_PHY(13)
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INTERNAL_PHY(14)
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INTERNAL_PHY(15)
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INTERNAL_PHY_SDS(24, 4)
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};
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INTERNAL_PHY_SDS(24, 4)
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};
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&switch0 {
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@ -52,7 +52,7 @@
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status = "okay";
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};
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&mdio {
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&mdio_bus0 {
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INTERNAL_PHY_SDS(24, 4)
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INTERNAL_PHY_SDS(26, 5)
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};
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@ -87,22 +87,15 @@
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};
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};
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ðernet0 {
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mdio: mdio-bus {
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compatible = "realtek,rtl838x-mdio";
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regmap = <ðernet0>;
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#address-cells = <1>;
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#size-cells = <0>;
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INTERNAL_PHY(8)
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INTERNAL_PHY(9)
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INTERNAL_PHY(10)
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INTERNAL_PHY(11)
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INTERNAL_PHY(12)
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INTERNAL_PHY(13)
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INTERNAL_PHY(14)
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INTERNAL_PHY(15)
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};
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&mdio_bus0 {
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INTERNAL_PHY(8)
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INTERNAL_PHY(9)
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INTERNAL_PHY(10)
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INTERNAL_PHY(11)
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INTERNAL_PHY(12)
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INTERNAL_PHY(13)
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INTERNAL_PHY(14)
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INTERNAL_PHY(15)
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};
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&switch0 {
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@ -96,22 +96,15 @@
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};
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};
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ðernet0 {
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mdio: mdio-bus {
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compatible = "realtek,rtl838x-mdio";
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regmap = <ðernet0>;
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#address-cells = <1>;
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#size-cells = <0>;
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INTERNAL_PHY(8)
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INTERNAL_PHY(9)
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INTERNAL_PHY(10)
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INTERNAL_PHY(11)
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INTERNAL_PHY(12)
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INTERNAL_PHY(13)
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INTERNAL_PHY(14)
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INTERNAL_PHY(15)
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};
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&mdio_bus0 {
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INTERNAL_PHY(8)
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INTERNAL_PHY(9)
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INTERNAL_PHY(10)
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INTERNAL_PHY(11)
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INTERNAL_PHY(12)
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INTERNAL_PHY(13)
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INTERNAL_PHY(14)
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INTERNAL_PHY(15)
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};
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&switch0 {
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@ -199,36 +199,29 @@
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};
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};
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ðernet0 {
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mdio-bus {
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compatible = "realtek,rtl838x-mdio";
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regmap = <ðernet0>;
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#address-cells = <1>;
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#size-cells = <0>;
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&mdio_bus0 {
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EXTERNAL_PHY(0)
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EXTERNAL_PHY(1)
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EXTERNAL_PHY(2)
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EXTERNAL_PHY(3)
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EXTERNAL_PHY(4)
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EXTERNAL_PHY(5)
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EXTERNAL_PHY(6)
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EXTERNAL_PHY(7)
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EXTERNAL_PHY(0)
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EXTERNAL_PHY(1)
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EXTERNAL_PHY(2)
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EXTERNAL_PHY(3)
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EXTERNAL_PHY(4)
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EXTERNAL_PHY(5)
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EXTERNAL_PHY(6)
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EXTERNAL_PHY(7)
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INTERNAL_PHY(8)
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INTERNAL_PHY(9)
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INTERNAL_PHY(10)
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INTERNAL_PHY(11)
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INTERNAL_PHY(12)
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INTERNAL_PHY(13)
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INTERNAL_PHY(14)
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INTERNAL_PHY(15)
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INTERNAL_PHY(8)
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INTERNAL_PHY(9)
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INTERNAL_PHY(10)
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INTERNAL_PHY(11)
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INTERNAL_PHY(12)
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INTERNAL_PHY(13)
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INTERNAL_PHY(14)
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INTERNAL_PHY(15)
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EXTERNAL_SFP_PHY_FULL(24, 0)
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EXTERNAL_SFP_PHY_FULL(25, 1)
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EXTERNAL_SFP_PHY_FULL(26, 2)
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EXTERNAL_SFP_PHY_FULL(27, 3)
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};
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EXTERNAL_SFP_PHY_FULL(24, 0)
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EXTERNAL_SFP_PHY_FULL(25, 1)
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EXTERNAL_SFP_PHY_FULL(26, 2)
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EXTERNAL_SFP_PHY_FULL(27, 3)
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};
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&switch0 {
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@ -74,25 +74,18 @@
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status = "okay";
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};
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ðernet0 {
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mdio: mdio-bus {
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compatible = "realtek,rtl838x-mdio";
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regmap = <ðernet0>;
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#address-cells = <1>;
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#size-cells = <0>;
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&mdio_bus0 {
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INTERNAL_PHY(8)
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INTERNAL_PHY(9)
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INTERNAL_PHY(10)
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INTERNAL_PHY(11)
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INTERNAL_PHY(12)
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INTERNAL_PHY(13)
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INTERNAL_PHY(14)
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INTERNAL_PHY(15)
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INTERNAL_PHY(8)
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INTERNAL_PHY(9)
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INTERNAL_PHY(10)
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INTERNAL_PHY(11)
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INTERNAL_PHY(12)
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INTERNAL_PHY(13)
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INTERNAL_PHY(14)
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INTERNAL_PHY(15)
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INTERNAL_PHY_SDS(24, 4)
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INTERNAL_PHY_SDS(26, 5)
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};
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INTERNAL_PHY_SDS(24, 4)
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INTERNAL_PHY_SDS(26, 5)
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};
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&switch0 {
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@ -9,36 +9,29 @@
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model = "D-Link DGS-1210-16";
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};
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ðernet0 {
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mdio: mdio-bus {
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compatible = "realtek,rtl838x-mdio";
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regmap = <ðernet0>;
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#address-cells = <1>;
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#size-cells = <0>;
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&mdio_bus0 {
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EXTERNAL_PHY(0)
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EXTERNAL_PHY(1)
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EXTERNAL_PHY(2)
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EXTERNAL_PHY(3)
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EXTERNAL_PHY(4)
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EXTERNAL_PHY(5)
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EXTERNAL_PHY(6)
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EXTERNAL_PHY(7)
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EXTERNAL_PHY(0)
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EXTERNAL_PHY(1)
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EXTERNAL_PHY(2)
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EXTERNAL_PHY(3)
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EXTERNAL_PHY(4)
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EXTERNAL_PHY(5)
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EXTERNAL_PHY(6)
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EXTERNAL_PHY(7)
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INTERNAL_PHY(8)
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INTERNAL_PHY(9)
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INTERNAL_PHY(10)
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INTERNAL_PHY(11)
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INTERNAL_PHY(12)
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INTERNAL_PHY(13)
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INTERNAL_PHY(14)
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INTERNAL_PHY(15)
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INTERNAL_PHY(8)
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INTERNAL_PHY(9)
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INTERNAL_PHY(10)
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INTERNAL_PHY(11)
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INTERNAL_PHY(12)
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INTERNAL_PHY(13)
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INTERNAL_PHY(14)
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INTERNAL_PHY(15)
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EXTERNAL_SFP_PHY(24)
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EXTERNAL_SFP_PHY(25)
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EXTERNAL_SFP_PHY(26)
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EXTERNAL_SFP_PHY(27)
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};
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EXTERNAL_SFP_PHY(24)
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EXTERNAL_SFP_PHY(25)
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EXTERNAL_SFP_PHY(26)
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EXTERNAL_SFP_PHY(27)
|
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};
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&switch0 {
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|
|
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|||
|
|
@ -9,36 +9,29 @@
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model = "D-Link DGS-1210-20";
|
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};
|
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|
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ðernet0 {
|
||||
mdio: mdio-bus {
|
||||
compatible = "realtek,rtl838x-mdio";
|
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regmap = <ðernet0>;
|
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#address-cells = <1>;
|
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#size-cells = <0>;
|
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&mdio_bus0 {
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EXTERNAL_PHY(0)
|
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EXTERNAL_PHY(1)
|
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EXTERNAL_PHY(2)
|
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EXTERNAL_PHY(3)
|
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EXTERNAL_PHY(4)
|
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EXTERNAL_PHY(5)
|
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EXTERNAL_PHY(6)
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EXTERNAL_PHY(7)
|
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EXTERNAL_PHY(0)
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EXTERNAL_PHY(1)
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EXTERNAL_PHY(2)
|
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EXTERNAL_PHY(3)
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EXTERNAL_PHY(4)
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EXTERNAL_PHY(5)
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EXTERNAL_PHY(6)
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EXTERNAL_PHY(7)
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INTERNAL_PHY(8)
|
||||
INTERNAL_PHY(9)
|
||||
INTERNAL_PHY(10)
|
||||
INTERNAL_PHY(11)
|
||||
INTERNAL_PHY(12)
|
||||
INTERNAL_PHY(13)
|
||||
INTERNAL_PHY(14)
|
||||
INTERNAL_PHY(15)
|
||||
|
||||
INTERNAL_PHY(8)
|
||||
INTERNAL_PHY(9)
|
||||
INTERNAL_PHY(10)
|
||||
INTERNAL_PHY(11)
|
||||
INTERNAL_PHY(12)
|
||||
INTERNAL_PHY(13)
|
||||
INTERNAL_PHY(14)
|
||||
INTERNAL_PHY(15)
|
||||
|
||||
EXTERNAL_SFP_PHY(24)
|
||||
EXTERNAL_SFP_PHY(25)
|
||||
EXTERNAL_SFP_PHY(26)
|
||||
EXTERNAL_SFP_PHY(27)
|
||||
};
|
||||
EXTERNAL_SFP_PHY(24)
|
||||
EXTERNAL_SFP_PHY(25)
|
||||
EXTERNAL_SFP_PHY(26)
|
||||
EXTERNAL_SFP_PHY(27)
|
||||
};
|
||||
|
||||
&switch0 {
|
||||
|
|
|
|||
|
|
@ -45,43 +45,36 @@
|
|||
};
|
||||
};
|
||||
|
||||
ðernet0 {
|
||||
mdio: mdio-bus {
|
||||
compatible = "realtek,rtl838x-mdio";
|
||||
regmap = <ðernet0>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
&mdio_bus0 {
|
||||
EXTERNAL_PHY(0)
|
||||
EXTERNAL_PHY(1)
|
||||
EXTERNAL_PHY(2)
|
||||
EXTERNAL_PHY(3)
|
||||
EXTERNAL_PHY(4)
|
||||
EXTERNAL_PHY(5)
|
||||
EXTERNAL_PHY(6)
|
||||
EXTERNAL_PHY(7)
|
||||
|
||||
EXTERNAL_PHY(0)
|
||||
EXTERNAL_PHY(1)
|
||||
EXTERNAL_PHY(2)
|
||||
EXTERNAL_PHY(3)
|
||||
EXTERNAL_PHY(4)
|
||||
EXTERNAL_PHY(5)
|
||||
EXTERNAL_PHY(6)
|
||||
EXTERNAL_PHY(7)
|
||||
INTERNAL_PHY(8)
|
||||
INTERNAL_PHY(9)
|
||||
INTERNAL_PHY(10)
|
||||
INTERNAL_PHY(11)
|
||||
INTERNAL_PHY(12)
|
||||
INTERNAL_PHY(13)
|
||||
INTERNAL_PHY(14)
|
||||
INTERNAL_PHY(15)
|
||||
|
||||
INTERNAL_PHY(8)
|
||||
INTERNAL_PHY(9)
|
||||
INTERNAL_PHY(10)
|
||||
INTERNAL_PHY(11)
|
||||
INTERNAL_PHY(12)
|
||||
INTERNAL_PHY(13)
|
||||
INTERNAL_PHY(14)
|
||||
INTERNAL_PHY(15)
|
||||
EXTERNAL_PHY(16)
|
||||
EXTERNAL_PHY(17)
|
||||
EXTERNAL_PHY(18)
|
||||
EXTERNAL_PHY(19)
|
||||
EXTERNAL_PHY(20)
|
||||
EXTERNAL_PHY(21)
|
||||
EXTERNAL_PHY(22)
|
||||
EXTERNAL_PHY(23)
|
||||
|
||||
EXTERNAL_PHY(16)
|
||||
EXTERNAL_PHY(17)
|
||||
EXTERNAL_PHY(18)
|
||||
EXTERNAL_PHY(19)
|
||||
EXTERNAL_PHY(20)
|
||||
EXTERNAL_PHY(21)
|
||||
EXTERNAL_PHY(22)
|
||||
EXTERNAL_PHY(23)
|
||||
|
||||
INTERNAL_PHY_SDS(24, 4)
|
||||
INTERNAL_PHY_SDS(26, 5)
|
||||
};
|
||||
INTERNAL_PHY_SDS(24, 4)
|
||||
INTERNAL_PHY_SDS(26, 5)
|
||||
};
|
||||
|
||||
&switch0 {
|
||||
|
|
|
|||
|
|
@ -1,45 +1,38 @@
|
|||
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
|
||||
|
||||
ðernet0 {
|
||||
mdio: mdio-bus {
|
||||
compatible = "realtek,rtl838x-mdio";
|
||||
regmap = <ðernet0>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
&mdio_bus0 {
|
||||
EXTERNAL_PHY(0)
|
||||
EXTERNAL_PHY(1)
|
||||
EXTERNAL_PHY(2)
|
||||
EXTERNAL_PHY(3)
|
||||
EXTERNAL_PHY(4)
|
||||
EXTERNAL_PHY(5)
|
||||
EXTERNAL_PHY(6)
|
||||
EXTERNAL_PHY(7)
|
||||
|
||||
EXTERNAL_PHY(0)
|
||||
EXTERNAL_PHY(1)
|
||||
EXTERNAL_PHY(2)
|
||||
EXTERNAL_PHY(3)
|
||||
EXTERNAL_PHY(4)
|
||||
EXTERNAL_PHY(5)
|
||||
EXTERNAL_PHY(6)
|
||||
EXTERNAL_PHY(7)
|
||||
INTERNAL_PHY(8)
|
||||
INTERNAL_PHY(9)
|
||||
INTERNAL_PHY(10)
|
||||
INTERNAL_PHY(11)
|
||||
INTERNAL_PHY(12)
|
||||
INTERNAL_PHY(13)
|
||||
INTERNAL_PHY(14)
|
||||
INTERNAL_PHY(15)
|
||||
|
||||
INTERNAL_PHY(8)
|
||||
INTERNAL_PHY(9)
|
||||
INTERNAL_PHY(10)
|
||||
INTERNAL_PHY(11)
|
||||
INTERNAL_PHY(12)
|
||||
INTERNAL_PHY(13)
|
||||
INTERNAL_PHY(14)
|
||||
INTERNAL_PHY(15)
|
||||
EXTERNAL_PHY(16)
|
||||
EXTERNAL_PHY(17)
|
||||
EXTERNAL_PHY(18)
|
||||
EXTERNAL_PHY(19)
|
||||
EXTERNAL_PHY(20)
|
||||
EXTERNAL_PHY(21)
|
||||
EXTERNAL_PHY(22)
|
||||
EXTERNAL_PHY(23)
|
||||
|
||||
EXTERNAL_PHY(16)
|
||||
EXTERNAL_PHY(17)
|
||||
EXTERNAL_PHY(18)
|
||||
EXTERNAL_PHY(19)
|
||||
EXTERNAL_PHY(20)
|
||||
EXTERNAL_PHY(21)
|
||||
EXTERNAL_PHY(22)
|
||||
EXTERNAL_PHY(23)
|
||||
|
||||
/* External phy RTL8214FC */
|
||||
EXTERNAL_SFP_PHY_FULL(24, 0)
|
||||
EXTERNAL_SFP_PHY_FULL(25, 1)
|
||||
EXTERNAL_SFP_PHY_FULL(26, 2)
|
||||
EXTERNAL_SFP_PHY_FULL(27, 3)
|
||||
};
|
||||
/* External phy RTL8214FC */
|
||||
EXTERNAL_SFP_PHY_FULL(24, 0)
|
||||
EXTERNAL_SFP_PHY_FULL(25, 1)
|
||||
EXTERNAL_SFP_PHY_FULL(26, 2)
|
||||
EXTERNAL_SFP_PHY_FULL(27, 3)
|
||||
};
|
||||
|
||||
&switch0 {
|
||||
|
|
|
|||
|
|
@ -7,7 +7,7 @@
|
|||
model = "HPE 1920-24G (JG924A)";
|
||||
};
|
||||
|
||||
&mdio {
|
||||
&mdio_bus0 {
|
||||
EXTERNAL_PHY(0)
|
||||
EXTERNAL_PHY(1)
|
||||
EXTERNAL_PHY(2)
|
||||
|
|
|
|||
|
|
@ -96,34 +96,27 @@
|
|||
};
|
||||
};
|
||||
|
||||
ðernet0 {
|
||||
mdio: mdio-bus {
|
||||
compatible = "realtek,rtl838x-mdio";
|
||||
regmap = <ðernet0>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
&mdio_bus0 {
|
||||
INTERNAL_PHY(8)
|
||||
INTERNAL_PHY(9)
|
||||
INTERNAL_PHY(10)
|
||||
INTERNAL_PHY(11)
|
||||
INTERNAL_PHY(12)
|
||||
INTERNAL_PHY(13)
|
||||
INTERNAL_PHY(14)
|
||||
INTERNAL_PHY(15)
|
||||
|
||||
INTERNAL_PHY(8)
|
||||
INTERNAL_PHY(9)
|
||||
INTERNAL_PHY(10)
|
||||
INTERNAL_PHY(11)
|
||||
INTERNAL_PHY(12)
|
||||
INTERNAL_PHY(13)
|
||||
INTERNAL_PHY(14)
|
||||
INTERNAL_PHY(15)
|
||||
EXTERNAL_PHY(16)
|
||||
EXTERNAL_PHY(17)
|
||||
EXTERNAL_PHY(18)
|
||||
EXTERNAL_PHY(19)
|
||||
EXTERNAL_PHY(20)
|
||||
EXTERNAL_PHY(21)
|
||||
EXTERNAL_PHY(22)
|
||||
EXTERNAL_PHY(23)
|
||||
|
||||
EXTERNAL_PHY(16)
|
||||
EXTERNAL_PHY(17)
|
||||
EXTERNAL_PHY(18)
|
||||
EXTERNAL_PHY(19)
|
||||
EXTERNAL_PHY(20)
|
||||
EXTERNAL_PHY(21)
|
||||
EXTERNAL_PHY(22)
|
||||
EXTERNAL_PHY(23)
|
||||
|
||||
EXTERNAL_SFP_PHY_FULL(24, 0)
|
||||
EXTERNAL_SFP_PHY_FULL(25, 1)
|
||||
EXTERNAL_SFP_PHY_FULL(26, 2)
|
||||
EXTERNAL_SFP_PHY_FULL(27, 3)
|
||||
};
|
||||
EXTERNAL_SFP_PHY_FULL(24, 0)
|
||||
EXTERNAL_SFP_PHY_FULL(25, 1)
|
||||
EXTERNAL_SFP_PHY_FULL(26, 2)
|
||||
EXTERNAL_SFP_PHY_FULL(27, 3)
|
||||
};
|
||||
|
|
|
|||
|
|
@ -85,33 +85,26 @@
|
|||
};
|
||||
};
|
||||
|
||||
ðernet0 {
|
||||
mdio-bus {
|
||||
compatible = "realtek,rtl838x-mdio";
|
||||
regmap = <ðernet0>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
&mdio_bus0 {
|
||||
INTERNAL_PHY(8)
|
||||
INTERNAL_PHY(9)
|
||||
INTERNAL_PHY(10)
|
||||
INTERNAL_PHY(11)
|
||||
INTERNAL_PHY(12)
|
||||
INTERNAL_PHY(13)
|
||||
INTERNAL_PHY(14)
|
||||
INTERNAL_PHY(15)
|
||||
|
||||
INTERNAL_PHY(8)
|
||||
INTERNAL_PHY(9)
|
||||
INTERNAL_PHY(10)
|
||||
INTERNAL_PHY(11)
|
||||
INTERNAL_PHY(12)
|
||||
INTERNAL_PHY(13)
|
||||
INTERNAL_PHY(14)
|
||||
INTERNAL_PHY(15)
|
||||
EXTERNAL_PHY(16)
|
||||
EXTERNAL_PHY(17)
|
||||
EXTERNAL_PHY(18)
|
||||
EXTERNAL_PHY(19)
|
||||
EXTERNAL_PHY(20)
|
||||
EXTERNAL_PHY(21)
|
||||
EXTERNAL_PHY(22)
|
||||
EXTERNAL_PHY(23)
|
||||
|
||||
EXTERNAL_PHY(16)
|
||||
EXTERNAL_PHY(17)
|
||||
EXTERNAL_PHY(18)
|
||||
EXTERNAL_PHY(19)
|
||||
EXTERNAL_PHY(20)
|
||||
EXTERNAL_PHY(21)
|
||||
EXTERNAL_PHY(22)
|
||||
EXTERNAL_PHY(23)
|
||||
|
||||
EXTERNAL_PHY(24)
|
||||
};
|
||||
EXTERNAL_PHY(24)
|
||||
};
|
||||
|
||||
&switch0 {
|
||||
|
|
|
|||
|
|
@ -121,40 +121,33 @@
|
|||
};
|
||||
};
|
||||
|
||||
ðernet0 {
|
||||
mdio-bus {
|
||||
compatible = "realtek,rtl838x-mdio";
|
||||
regmap = <ðernet0>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
&mdio_bus0 {
|
||||
EXTERNAL_PHY(0)
|
||||
EXTERNAL_PHY(1)
|
||||
EXTERNAL_PHY(2)
|
||||
EXTERNAL_PHY(3)
|
||||
EXTERNAL_PHY(4)
|
||||
EXTERNAL_PHY(5)
|
||||
EXTERNAL_PHY(6)
|
||||
EXTERNAL_PHY(7)
|
||||
|
||||
EXTERNAL_PHY(0)
|
||||
EXTERNAL_PHY(1)
|
||||
EXTERNAL_PHY(2)
|
||||
EXTERNAL_PHY(3)
|
||||
EXTERNAL_PHY(4)
|
||||
EXTERNAL_PHY(5)
|
||||
EXTERNAL_PHY(6)
|
||||
EXTERNAL_PHY(7)
|
||||
INTERNAL_PHY(8)
|
||||
INTERNAL_PHY(9)
|
||||
INTERNAL_PHY(10)
|
||||
INTERNAL_PHY(11)
|
||||
INTERNAL_PHY(12)
|
||||
INTERNAL_PHY(13)
|
||||
INTERNAL_PHY(14)
|
||||
INTERNAL_PHY(15)
|
||||
|
||||
INTERNAL_PHY(8)
|
||||
INTERNAL_PHY(9)
|
||||
INTERNAL_PHY(10)
|
||||
INTERNAL_PHY(11)
|
||||
INTERNAL_PHY(12)
|
||||
INTERNAL_PHY(13)
|
||||
INTERNAL_PHY(14)
|
||||
INTERNAL_PHY(15)
|
||||
|
||||
EXTERNAL_PHY(16)
|
||||
EXTERNAL_PHY(17)
|
||||
EXTERNAL_PHY(18)
|
||||
EXTERNAL_PHY(19)
|
||||
EXTERNAL_PHY(20)
|
||||
EXTERNAL_PHY(21)
|
||||
EXTERNAL_PHY(22)
|
||||
EXTERNAL_PHY(23)
|
||||
};
|
||||
EXTERNAL_PHY(16)
|
||||
EXTERNAL_PHY(17)
|
||||
EXTERNAL_PHY(18)
|
||||
EXTERNAL_PHY(19)
|
||||
EXTERNAL_PHY(20)
|
||||
EXTERNAL_PHY(21)
|
||||
EXTERNAL_PHY(22)
|
||||
EXTERNAL_PHY(23)
|
||||
};
|
||||
|
||||
&switch0 {
|
||||
|
|
|
|||
|
|
@ -105,31 +105,25 @@
|
|||
};
|
||||
};
|
||||
|
||||
ðernet0 {
|
||||
mdio-bus {
|
||||
compatible = "realtek,rtl838x-mdio";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
&mdio_bus0 {
|
||||
INTERNAL_PHY(8)
|
||||
INTERNAL_PHY(9)
|
||||
INTERNAL_PHY(10)
|
||||
INTERNAL_PHY(11)
|
||||
INTERNAL_PHY(12)
|
||||
INTERNAL_PHY(13)
|
||||
INTERNAL_PHY(14)
|
||||
INTERNAL_PHY(15)
|
||||
|
||||
INTERNAL_PHY(8)
|
||||
INTERNAL_PHY(9)
|
||||
INTERNAL_PHY(10)
|
||||
INTERNAL_PHY(11)
|
||||
INTERNAL_PHY(12)
|
||||
INTERNAL_PHY(13)
|
||||
INTERNAL_PHY(14)
|
||||
INTERNAL_PHY(15)
|
||||
|
||||
/* RTL8218FB */
|
||||
EXTERNAL_PHY(16)
|
||||
EXTERNAL_PHY(17)
|
||||
EXTERNAL_PHY(18)
|
||||
EXTERNAL_PHY(19)
|
||||
EXTERNAL_PHY(20)
|
||||
EXTERNAL_PHY(21)
|
||||
EXTERNAL_PHY(22)
|
||||
EXTERNAL_PHY(23)
|
||||
};
|
||||
/* RTL8218FB */
|
||||
EXTERNAL_PHY(16)
|
||||
EXTERNAL_PHY(17)
|
||||
EXTERNAL_PHY(18)
|
||||
EXTERNAL_PHY(19)
|
||||
EXTERNAL_PHY(20)
|
||||
EXTERNAL_PHY(21)
|
||||
EXTERNAL_PHY(22)
|
||||
EXTERNAL_PHY(23)
|
||||
};
|
||||
|
||||
&switch0 {
|
||||
|
|
|
|||
|
|
@ -106,40 +106,34 @@
|
|||
};
|
||||
};
|
||||
|
||||
ðernet0 {
|
||||
mdio-bus {
|
||||
compatible = "realtek,rtl838x-mdio";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
&mdio_bus0 {
|
||||
EXTERNAL_PHY(0)
|
||||
EXTERNAL_PHY(1)
|
||||
EXTERNAL_PHY(2)
|
||||
EXTERNAL_PHY(3)
|
||||
EXTERNAL_PHY(4)
|
||||
EXTERNAL_PHY(5)
|
||||
EXTERNAL_PHY(6)
|
||||
EXTERNAL_PHY(7)
|
||||
|
||||
EXTERNAL_PHY(0)
|
||||
EXTERNAL_PHY(1)
|
||||
EXTERNAL_PHY(2)
|
||||
EXTERNAL_PHY(3)
|
||||
EXTERNAL_PHY(4)
|
||||
EXTERNAL_PHY(5)
|
||||
EXTERNAL_PHY(6)
|
||||
EXTERNAL_PHY(7)
|
||||
INTERNAL_PHY(8)
|
||||
INTERNAL_PHY(9)
|
||||
INTERNAL_PHY(10)
|
||||
INTERNAL_PHY(11)
|
||||
INTERNAL_PHY(12)
|
||||
INTERNAL_PHY(13)
|
||||
INTERNAL_PHY(14)
|
||||
INTERNAL_PHY(15)
|
||||
|
||||
INTERNAL_PHY(8)
|
||||
INTERNAL_PHY(9)
|
||||
INTERNAL_PHY(10)
|
||||
INTERNAL_PHY(11)
|
||||
INTERNAL_PHY(12)
|
||||
INTERNAL_PHY(13)
|
||||
INTERNAL_PHY(14)
|
||||
INTERNAL_PHY(15)
|
||||
|
||||
/* RTL8218FB */
|
||||
EXTERNAL_PHY(16)
|
||||
EXTERNAL_PHY(17)
|
||||
EXTERNAL_PHY(18)
|
||||
EXTERNAL_PHY(19)
|
||||
EXTERNAL_PHY(20)
|
||||
EXTERNAL_PHY(21)
|
||||
EXTERNAL_PHY(22)
|
||||
EXTERNAL_PHY(23)
|
||||
};
|
||||
/* RTL8218FB */
|
||||
EXTERNAL_PHY(16)
|
||||
EXTERNAL_PHY(17)
|
||||
EXTERNAL_PHY(18)
|
||||
EXTERNAL_PHY(19)
|
||||
EXTERNAL_PHY(20)
|
||||
EXTERNAL_PHY(21)
|
||||
EXTERNAL_PHY(22)
|
||||
EXTERNAL_PHY(23)
|
||||
};
|
||||
|
||||
&switch0 {
|
||||
|
|
|
|||
|
|
@ -92,40 +92,35 @@
|
|||
ðernet0 {
|
||||
nvmem-cells = <&factory_macaddr>;
|
||||
nvmem-cell-names = "mac-address";
|
||||
};
|
||||
|
||||
mdio-bus {
|
||||
compatible = "realtek,rtl838x-mdio";
|
||||
regmap = <ðernet0>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
&mdio_bus0 {
|
||||
EXTERNAL_PHY(0)
|
||||
EXTERNAL_PHY(1)
|
||||
EXTERNAL_PHY(2)
|
||||
EXTERNAL_PHY(3)
|
||||
EXTERNAL_PHY(4)
|
||||
EXTERNAL_PHY(5)
|
||||
EXTERNAL_PHY(6)
|
||||
EXTERNAL_PHY(7)
|
||||
|
||||
EXTERNAL_PHY(0)
|
||||
EXTERNAL_PHY(1)
|
||||
EXTERNAL_PHY(2)
|
||||
EXTERNAL_PHY(3)
|
||||
EXTERNAL_PHY(4)
|
||||
EXTERNAL_PHY(5)
|
||||
EXTERNAL_PHY(6)
|
||||
EXTERNAL_PHY(7)
|
||||
INTERNAL_PHY(8)
|
||||
INTERNAL_PHY(9)
|
||||
INTERNAL_PHY(10)
|
||||
INTERNAL_PHY(11)
|
||||
INTERNAL_PHY(12)
|
||||
INTERNAL_PHY(13)
|
||||
INTERNAL_PHY(14)
|
||||
INTERNAL_PHY(15)
|
||||
|
||||
INTERNAL_PHY(8)
|
||||
INTERNAL_PHY(9)
|
||||
INTERNAL_PHY(10)
|
||||
INTERNAL_PHY(11)
|
||||
INTERNAL_PHY(12)
|
||||
INTERNAL_PHY(13)
|
||||
INTERNAL_PHY(14)
|
||||
INTERNAL_PHY(15)
|
||||
|
||||
EXTERNAL_PHY(16)
|
||||
EXTERNAL_PHY(17)
|
||||
EXTERNAL_PHY(18)
|
||||
EXTERNAL_PHY(19)
|
||||
EXTERNAL_PHY(20)
|
||||
EXTERNAL_PHY(21)
|
||||
EXTERNAL_PHY(22)
|
||||
EXTERNAL_PHY(23)
|
||||
};
|
||||
EXTERNAL_PHY(16)
|
||||
EXTERNAL_PHY(17)
|
||||
EXTERNAL_PHY(18)
|
||||
EXTERNAL_PHY(19)
|
||||
EXTERNAL_PHY(20)
|
||||
EXTERNAL_PHY(21)
|
||||
EXTERNAL_PHY(22)
|
||||
EXTERNAL_PHY(23)
|
||||
};
|
||||
|
||||
&switch0 {
|
||||
|
|
|
|||
|
|
@ -8,7 +8,7 @@
|
|||
model = "Zyxel GS1900-16";
|
||||
};
|
||||
|
||||
&mdio {
|
||||
&mdio_bus0 {
|
||||
EXTERNAL_PHY(16)
|
||||
EXTERNAL_PHY(17)
|
||||
EXTERNAL_PHY(18)
|
||||
|
|
|
|||
|
|
@ -54,7 +54,7 @@
|
|||
status = "okay";
|
||||
};
|
||||
|
||||
&mdio {
|
||||
&mdio_bus0 {
|
||||
EXTERNAL_PHY(0)
|
||||
EXTERNAL_PHY(1)
|
||||
EXTERNAL_PHY(2)
|
||||
|
|
|
|||
|
|
@ -8,7 +8,7 @@
|
|||
model = "Zyxel GS1900-24E";
|
||||
};
|
||||
|
||||
&mdio {
|
||||
&mdio_bus0 {
|
||||
EXTERNAL_PHY(0)
|
||||
EXTERNAL_PHY(1)
|
||||
EXTERNAL_PHY(2)
|
||||
|
|
|
|||
|
|
@ -12,7 +12,7 @@
|
|||
status = "okay";
|
||||
};
|
||||
|
||||
&mdio {
|
||||
&mdio_bus0 {
|
||||
EXTERNAL_PHY(0)
|
||||
EXTERNAL_PHY(1)
|
||||
EXTERNAL_PHY(2)
|
||||
|
|
|
|||
|
|
@ -54,7 +54,7 @@
|
|||
status = "okay";
|
||||
};
|
||||
|
||||
&mdio {
|
||||
&mdio_bus0 {
|
||||
EXTERNAL_PHY(0)
|
||||
EXTERNAL_PHY(1)
|
||||
EXTERNAL_PHY(2)
|
||||
|
|
|
|||
|
|
@ -50,7 +50,7 @@
|
|||
status = "okay";
|
||||
};
|
||||
|
||||
&mdio {
|
||||
&mdio_bus0 {
|
||||
EXTERNAL_PHY(0)
|
||||
EXTERNAL_PHY(1)
|
||||
EXTERNAL_PHY(2)
|
||||
|
|
|
|||
|
|
@ -10,79 +10,72 @@
|
|||
model = "D-Link DGS-1210-52";
|
||||
};
|
||||
|
||||
ðernet0 {
|
||||
mdio: mdio-bus {
|
||||
compatible = "realtek,rtl838x-mdio";
|
||||
regmap = <ðernet0>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
&mdio_bus0 {
|
||||
/* External phy RTL8218B #1 */
|
||||
EXTERNAL_PHY(0)
|
||||
EXTERNAL_PHY(1)
|
||||
EXTERNAL_PHY(2)
|
||||
EXTERNAL_PHY(3)
|
||||
EXTERNAL_PHY(4)
|
||||
EXTERNAL_PHY(5)
|
||||
EXTERNAL_PHY(6)
|
||||
EXTERNAL_PHY(7)
|
||||
|
||||
/* External phy RTL8218B #1 */
|
||||
EXTERNAL_PHY(0)
|
||||
EXTERNAL_PHY(1)
|
||||
EXTERNAL_PHY(2)
|
||||
EXTERNAL_PHY(3)
|
||||
EXTERNAL_PHY(4)
|
||||
EXTERNAL_PHY(5)
|
||||
EXTERNAL_PHY(6)
|
||||
EXTERNAL_PHY(7)
|
||||
/* External phy RTL8218B #2 */
|
||||
EXTERNAL_PHY(8)
|
||||
EXTERNAL_PHY(9)
|
||||
EXTERNAL_PHY(10)
|
||||
EXTERNAL_PHY(11)
|
||||
EXTERNAL_PHY(12)
|
||||
EXTERNAL_PHY(13)
|
||||
EXTERNAL_PHY(14)
|
||||
EXTERNAL_PHY(15)
|
||||
|
||||
/* External phy RTL8218B #2 */
|
||||
EXTERNAL_PHY(8)
|
||||
EXTERNAL_PHY(9)
|
||||
EXTERNAL_PHY(10)
|
||||
EXTERNAL_PHY(11)
|
||||
EXTERNAL_PHY(12)
|
||||
EXTERNAL_PHY(13)
|
||||
EXTERNAL_PHY(14)
|
||||
EXTERNAL_PHY(15)
|
||||
/* External phy RTL8218B #3 */
|
||||
EXTERNAL_PHY(16)
|
||||
EXTERNAL_PHY(17)
|
||||
EXTERNAL_PHY(18)
|
||||
EXTERNAL_PHY(19)
|
||||
EXTERNAL_PHY(20)
|
||||
EXTERNAL_PHY(21)
|
||||
EXTERNAL_PHY(22)
|
||||
EXTERNAL_PHY(23)
|
||||
|
||||
/* External phy RTL8218B #3 */
|
||||
EXTERNAL_PHY(16)
|
||||
EXTERNAL_PHY(17)
|
||||
EXTERNAL_PHY(18)
|
||||
EXTERNAL_PHY(19)
|
||||
EXTERNAL_PHY(20)
|
||||
EXTERNAL_PHY(21)
|
||||
EXTERNAL_PHY(22)
|
||||
EXTERNAL_PHY(23)
|
||||
/* External phy RTL8218B #4 */
|
||||
EXTERNAL_PHY(24)
|
||||
EXTERNAL_PHY(25)
|
||||
EXTERNAL_PHY(26)
|
||||
EXTERNAL_PHY(27)
|
||||
EXTERNAL_PHY(28)
|
||||
EXTERNAL_PHY(29)
|
||||
EXTERNAL_PHY(30)
|
||||
EXTERNAL_PHY(31)
|
||||
|
||||
/* External phy RTL8218B #4 */
|
||||
EXTERNAL_PHY(24)
|
||||
EXTERNAL_PHY(25)
|
||||
EXTERNAL_PHY(26)
|
||||
EXTERNAL_PHY(27)
|
||||
EXTERNAL_PHY(28)
|
||||
EXTERNAL_PHY(29)
|
||||
EXTERNAL_PHY(30)
|
||||
EXTERNAL_PHY(31)
|
||||
/* External phy RTL8218B #5 */
|
||||
EXTERNAL_PHY(32)
|
||||
EXTERNAL_PHY(33)
|
||||
EXTERNAL_PHY(34)
|
||||
EXTERNAL_PHY(35)
|
||||
EXTERNAL_PHY(36)
|
||||
EXTERNAL_PHY(37)
|
||||
EXTERNAL_PHY(38)
|
||||
EXTERNAL_PHY(39)
|
||||
|
||||
/* External phy RTL8218B #5 */
|
||||
EXTERNAL_PHY(32)
|
||||
EXTERNAL_PHY(33)
|
||||
EXTERNAL_PHY(34)
|
||||
EXTERNAL_PHY(35)
|
||||
EXTERNAL_PHY(36)
|
||||
EXTERNAL_PHY(37)
|
||||
EXTERNAL_PHY(38)
|
||||
EXTERNAL_PHY(39)
|
||||
/* External phy RTL8218B #6 */
|
||||
EXTERNAL_PHY(40)
|
||||
EXTERNAL_PHY(41)
|
||||
EXTERNAL_PHY(42)
|
||||
EXTERNAL_PHY(43)
|
||||
EXTERNAL_PHY(44)
|
||||
EXTERNAL_PHY(45)
|
||||
EXTERNAL_PHY(46)
|
||||
EXTERNAL_PHY(47)
|
||||
|
||||
/* External phy RTL8218B #6 */
|
||||
EXTERNAL_PHY(40)
|
||||
EXTERNAL_PHY(41)
|
||||
EXTERNAL_PHY(42)
|
||||
EXTERNAL_PHY(43)
|
||||
EXTERNAL_PHY(44)
|
||||
EXTERNAL_PHY(45)
|
||||
EXTERNAL_PHY(46)
|
||||
EXTERNAL_PHY(47)
|
||||
|
||||
/* External phy RTL8214FC */
|
||||
EXTERNAL_SFP_PHY_FULL(48, 0)
|
||||
EXTERNAL_SFP_PHY_FULL(49, 1)
|
||||
EXTERNAL_SFP_PHY_FULL(50, 2)
|
||||
EXTERNAL_SFP_PHY_FULL(51, 3)
|
||||
};
|
||||
/* External phy RTL8214FC */
|
||||
EXTERNAL_SFP_PHY_FULL(48, 0)
|
||||
EXTERNAL_SFP_PHY_FULL(49, 1)
|
||||
EXTERNAL_SFP_PHY_FULL(50, 2)
|
||||
EXTERNAL_SFP_PHY_FULL(51, 3)
|
||||
};
|
||||
|
||||
&switch0 {
|
||||
|
|
|
|||
|
|
@ -90,16 +90,13 @@
|
|||
};
|
||||
};
|
||||
|
||||
ðernet0 {
|
||||
mdio: mdio-bus {
|
||||
EXTERNAL_SFP_PHY_FULL(48, 0)
|
||||
EXTERNAL_SFP_PHY_FULL(49, 1)
|
||||
EXTERNAL_SFP_PHY_FULL(50, 2)
|
||||
EXTERNAL_SFP_PHY_FULL(51, 3)
|
||||
};
|
||||
&mdio_bus0 {
|
||||
EXTERNAL_SFP_PHY_FULL(48, 0)
|
||||
EXTERNAL_SFP_PHY_FULL(49, 1)
|
||||
EXTERNAL_SFP_PHY_FULL(50, 2)
|
||||
EXTERNAL_SFP_PHY_FULL(51, 3)
|
||||
};
|
||||
|
||||
|
||||
&switch0 {
|
||||
ports {
|
||||
SWITCH_PORT(48, 49, qsgmii)
|
||||
|
|
|
|||
|
|
@ -80,13 +80,11 @@
|
|||
|
||||
};
|
||||
|
||||
ðernet0 {
|
||||
mdio: mdio-bus {
|
||||
EXTERNAL_SFP_PHY_FULL(48, 1)
|
||||
EXTERNAL_SFP_PHY_FULL(49, 3)
|
||||
EXTERNAL_SFP_PHY_FULL(50, 0)
|
||||
EXTERNAL_SFP_PHY_FULL(51, 2)
|
||||
};
|
||||
&mdio_bus0 {
|
||||
EXTERNAL_SFP_PHY_FULL(48, 1)
|
||||
EXTERNAL_SFP_PHY_FULL(49, 3)
|
||||
EXTERNAL_SFP_PHY_FULL(50, 0)
|
||||
EXTERNAL_SFP_PHY_FULL(51, 2)
|
||||
};
|
||||
|
||||
|
||||
|
|
|
|||
|
|
@ -24,67 +24,60 @@
|
|||
};
|
||||
};
|
||||
|
||||
ðernet0 {
|
||||
mdio: mdio-bus {
|
||||
compatible = "realtek,rtl838x-mdio";
|
||||
regmap = <ðernet0>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
&mdio_bus0 {
|
||||
EXTERNAL_PHY(0)
|
||||
EXTERNAL_PHY(1)
|
||||
EXTERNAL_PHY(2)
|
||||
EXTERNAL_PHY(3)
|
||||
EXTERNAL_PHY(4)
|
||||
EXTERNAL_PHY(5)
|
||||
EXTERNAL_PHY(6)
|
||||
EXTERNAL_PHY(7)
|
||||
|
||||
EXTERNAL_PHY(0)
|
||||
EXTERNAL_PHY(1)
|
||||
EXTERNAL_PHY(2)
|
||||
EXTERNAL_PHY(3)
|
||||
EXTERNAL_PHY(4)
|
||||
EXTERNAL_PHY(5)
|
||||
EXTERNAL_PHY(6)
|
||||
EXTERNAL_PHY(7)
|
||||
EXTERNAL_PHY(8)
|
||||
EXTERNAL_PHY(9)
|
||||
EXTERNAL_PHY(10)
|
||||
EXTERNAL_PHY(11)
|
||||
EXTERNAL_PHY(12)
|
||||
EXTERNAL_PHY(13)
|
||||
EXTERNAL_PHY(14)
|
||||
EXTERNAL_PHY(15)
|
||||
|
||||
EXTERNAL_PHY(8)
|
||||
EXTERNAL_PHY(9)
|
||||
EXTERNAL_PHY(10)
|
||||
EXTERNAL_PHY(11)
|
||||
EXTERNAL_PHY(12)
|
||||
EXTERNAL_PHY(13)
|
||||
EXTERNAL_PHY(14)
|
||||
EXTERNAL_PHY(15)
|
||||
EXTERNAL_PHY(16)
|
||||
EXTERNAL_PHY(17)
|
||||
EXTERNAL_PHY(18)
|
||||
EXTERNAL_PHY(19)
|
||||
EXTERNAL_PHY(20)
|
||||
EXTERNAL_PHY(21)
|
||||
EXTERNAL_PHY(22)
|
||||
EXTERNAL_PHY(23)
|
||||
|
||||
EXTERNAL_PHY(16)
|
||||
EXTERNAL_PHY(17)
|
||||
EXTERNAL_PHY(18)
|
||||
EXTERNAL_PHY(19)
|
||||
EXTERNAL_PHY(20)
|
||||
EXTERNAL_PHY(21)
|
||||
EXTERNAL_PHY(22)
|
||||
EXTERNAL_PHY(23)
|
||||
EXTERNAL_PHY(24)
|
||||
EXTERNAL_PHY(25)
|
||||
EXTERNAL_PHY(26)
|
||||
EXTERNAL_PHY(27)
|
||||
EXTERNAL_PHY(28)
|
||||
EXTERNAL_PHY(29)
|
||||
EXTERNAL_PHY(30)
|
||||
EXTERNAL_PHY(31)
|
||||
|
||||
EXTERNAL_PHY(24)
|
||||
EXTERNAL_PHY(25)
|
||||
EXTERNAL_PHY(26)
|
||||
EXTERNAL_PHY(27)
|
||||
EXTERNAL_PHY(28)
|
||||
EXTERNAL_PHY(29)
|
||||
EXTERNAL_PHY(30)
|
||||
EXTERNAL_PHY(31)
|
||||
EXTERNAL_PHY(32)
|
||||
EXTERNAL_PHY(33)
|
||||
EXTERNAL_PHY(34)
|
||||
EXTERNAL_PHY(35)
|
||||
EXTERNAL_PHY(36)
|
||||
EXTERNAL_PHY(37)
|
||||
EXTERNAL_PHY(38)
|
||||
EXTERNAL_PHY(39)
|
||||
|
||||
EXTERNAL_PHY(32)
|
||||
EXTERNAL_PHY(33)
|
||||
EXTERNAL_PHY(34)
|
||||
EXTERNAL_PHY(35)
|
||||
EXTERNAL_PHY(36)
|
||||
EXTERNAL_PHY(37)
|
||||
EXTERNAL_PHY(38)
|
||||
EXTERNAL_PHY(39)
|
||||
|
||||
EXTERNAL_PHY(40)
|
||||
EXTERNAL_PHY(41)
|
||||
EXTERNAL_PHY(42)
|
||||
EXTERNAL_PHY(43)
|
||||
EXTERNAL_PHY(44)
|
||||
EXTERNAL_PHY(45)
|
||||
EXTERNAL_PHY(46)
|
||||
EXTERNAL_PHY(47)
|
||||
};
|
||||
EXTERNAL_PHY(40)
|
||||
EXTERNAL_PHY(41)
|
||||
EXTERNAL_PHY(42)
|
||||
EXTERNAL_PHY(43)
|
||||
EXTERNAL_PHY(44)
|
||||
EXTERNAL_PHY(45)
|
||||
EXTERNAL_PHY(46)
|
||||
EXTERNAL_PHY(47)
|
||||
};
|
||||
|
||||
&switch0 {
|
||||
|
|
|
|||
|
|
@ -102,78 +102,73 @@
|
|||
};
|
||||
};
|
||||
|
||||
ðernet0 {
|
||||
mdio: mdio-bus {
|
||||
compatible = "realtek,rtl838x-mdio";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
// Switch doesn't come back properly after a reset so don't.
|
||||
// reset-gpios = <&gpio0 23 GPIO_ACTIVE_LOW>;
|
||||
&mdio_bus0 {
|
||||
// Switch doesn't come back properly after a reset so don't.
|
||||
// reset-gpios = <&gpio0 23 GPIO_ACTIVE_LOW>;
|
||||
|
||||
/* External phy RTL8218B #1 */
|
||||
EXTERNAL_PHY(0)
|
||||
EXTERNAL_PHY(1)
|
||||
EXTERNAL_PHY(2)
|
||||
EXTERNAL_PHY(3)
|
||||
EXTERNAL_PHY(4)
|
||||
EXTERNAL_PHY(5)
|
||||
EXTERNAL_PHY(6)
|
||||
EXTERNAL_PHY(7)
|
||||
/* External phy RTL8218B #1 */
|
||||
EXTERNAL_PHY(0)
|
||||
EXTERNAL_PHY(1)
|
||||
EXTERNAL_PHY(2)
|
||||
EXTERNAL_PHY(3)
|
||||
EXTERNAL_PHY(4)
|
||||
EXTERNAL_PHY(5)
|
||||
EXTERNAL_PHY(6)
|
||||
EXTERNAL_PHY(7)
|
||||
|
||||
/* External phy RTL8218B #2 */
|
||||
EXTERNAL_PHY(8)
|
||||
EXTERNAL_PHY(9)
|
||||
EXTERNAL_PHY(10)
|
||||
EXTERNAL_PHY(11)
|
||||
EXTERNAL_PHY(12)
|
||||
EXTERNAL_PHY(13)
|
||||
EXTERNAL_PHY(14)
|
||||
EXTERNAL_PHY(15)
|
||||
/* External phy RTL8218B #2 */
|
||||
EXTERNAL_PHY(8)
|
||||
EXTERNAL_PHY(9)
|
||||
EXTERNAL_PHY(10)
|
||||
EXTERNAL_PHY(11)
|
||||
EXTERNAL_PHY(12)
|
||||
EXTERNAL_PHY(13)
|
||||
EXTERNAL_PHY(14)
|
||||
EXTERNAL_PHY(15)
|
||||
|
||||
/* External phy RTL8218B #3 */
|
||||
EXTERNAL_PHY(16)
|
||||
EXTERNAL_PHY(17)
|
||||
EXTERNAL_PHY(18)
|
||||
EXTERNAL_PHY(19)
|
||||
EXTERNAL_PHY(20)
|
||||
EXTERNAL_PHY(21)
|
||||
EXTERNAL_PHY(22)
|
||||
EXTERNAL_PHY(23)
|
||||
/* External phy RTL8218B #3 */
|
||||
EXTERNAL_PHY(16)
|
||||
EXTERNAL_PHY(17)
|
||||
EXTERNAL_PHY(18)
|
||||
EXTERNAL_PHY(19)
|
||||
EXTERNAL_PHY(20)
|
||||
EXTERNAL_PHY(21)
|
||||
EXTERNAL_PHY(22)
|
||||
EXTERNAL_PHY(23)
|
||||
|
||||
/* External phy RTL8218B #4 */
|
||||
EXTERNAL_PHY(24)
|
||||
EXTERNAL_PHY(25)
|
||||
EXTERNAL_PHY(26)
|
||||
EXTERNAL_PHY(27)
|
||||
EXTERNAL_PHY(28)
|
||||
EXTERNAL_PHY(29)
|
||||
EXTERNAL_PHY(30)
|
||||
EXTERNAL_PHY(31)
|
||||
/* External phy RTL8218B #4 */
|
||||
EXTERNAL_PHY(24)
|
||||
EXTERNAL_PHY(25)
|
||||
EXTERNAL_PHY(26)
|
||||
EXTERNAL_PHY(27)
|
||||
EXTERNAL_PHY(28)
|
||||
EXTERNAL_PHY(29)
|
||||
EXTERNAL_PHY(30)
|
||||
EXTERNAL_PHY(31)
|
||||
|
||||
/* External phy RTL8218B #5 */
|
||||
EXTERNAL_PHY(32)
|
||||
EXTERNAL_PHY(33)
|
||||
EXTERNAL_PHY(34)
|
||||
EXTERNAL_PHY(35)
|
||||
EXTERNAL_PHY(36)
|
||||
EXTERNAL_PHY(37)
|
||||
EXTERNAL_PHY(38)
|
||||
EXTERNAL_PHY(39)
|
||||
/* External phy RTL8218B #5 */
|
||||
EXTERNAL_PHY(32)
|
||||
EXTERNAL_PHY(33)
|
||||
EXTERNAL_PHY(34)
|
||||
EXTERNAL_PHY(35)
|
||||
EXTERNAL_PHY(36)
|
||||
EXTERNAL_PHY(37)
|
||||
EXTERNAL_PHY(38)
|
||||
EXTERNAL_PHY(39)
|
||||
|
||||
/* External phy RTL8218B #6 */
|
||||
EXTERNAL_PHY(40)
|
||||
EXTERNAL_PHY(41)
|
||||
EXTERNAL_PHY(42)
|
||||
EXTERNAL_PHY(43)
|
||||
EXTERNAL_PHY(44)
|
||||
EXTERNAL_PHY(45)
|
||||
EXTERNAL_PHY(46)
|
||||
EXTERNAL_PHY(47)
|
||||
/* External phy RTL8218B #6 */
|
||||
EXTERNAL_PHY(40)
|
||||
EXTERNAL_PHY(41)
|
||||
EXTERNAL_PHY(42)
|
||||
EXTERNAL_PHY(43)
|
||||
EXTERNAL_PHY(44)
|
||||
EXTERNAL_PHY(45)
|
||||
EXTERNAL_PHY(46)
|
||||
EXTERNAL_PHY(47)
|
||||
|
||||
/* RTL8393 Internal SerDes */
|
||||
INTERNAL_PHY(48)
|
||||
INTERNAL_PHY(49)
|
||||
};
|
||||
/* RTL8393 Internal SerDes */
|
||||
INTERNAL_PHY(48)
|
||||
INTERNAL_PHY(49)
|
||||
};
|
||||
|
||||
&switch0 {
|
||||
|
|
|
|||
|
|
@ -242,67 +242,61 @@
|
|||
};
|
||||
};
|
||||
|
||||
ðernet0 {
|
||||
mdio-bus {
|
||||
compatible = "realtek,rtl838x-mdio";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
&mdio_bus0 {
|
||||
EXTERNAL_PHY(0)
|
||||
EXTERNAL_PHY(1)
|
||||
EXTERNAL_PHY(2)
|
||||
EXTERNAL_PHY(3)
|
||||
EXTERNAL_PHY(4)
|
||||
EXTERNAL_PHY(5)
|
||||
EXTERNAL_PHY(6)
|
||||
EXTERNAL_PHY(7)
|
||||
|
||||
EXTERNAL_PHY(0)
|
||||
EXTERNAL_PHY(1)
|
||||
EXTERNAL_PHY(2)
|
||||
EXTERNAL_PHY(3)
|
||||
EXTERNAL_PHY(4)
|
||||
EXTERNAL_PHY(5)
|
||||
EXTERNAL_PHY(6)
|
||||
EXTERNAL_PHY(7)
|
||||
EXTERNAL_PHY(8)
|
||||
EXTERNAL_PHY(9)
|
||||
EXTERNAL_PHY(10)
|
||||
EXTERNAL_PHY(11)
|
||||
EXTERNAL_PHY(12)
|
||||
EXTERNAL_PHY(13)
|
||||
EXTERNAL_PHY(14)
|
||||
EXTERNAL_PHY(15)
|
||||
|
||||
EXTERNAL_PHY(8)
|
||||
EXTERNAL_PHY(9)
|
||||
EXTERNAL_PHY(10)
|
||||
EXTERNAL_PHY(11)
|
||||
EXTERNAL_PHY(12)
|
||||
EXTERNAL_PHY(13)
|
||||
EXTERNAL_PHY(14)
|
||||
EXTERNAL_PHY(15)
|
||||
EXTERNAL_PHY(16)
|
||||
EXTERNAL_PHY(17)
|
||||
EXTERNAL_PHY(18)
|
||||
EXTERNAL_PHY(19)
|
||||
EXTERNAL_PHY(20)
|
||||
EXTERNAL_PHY(21)
|
||||
EXTERNAL_PHY(22)
|
||||
EXTERNAL_PHY(23)
|
||||
|
||||
EXTERNAL_PHY(16)
|
||||
EXTERNAL_PHY(17)
|
||||
EXTERNAL_PHY(18)
|
||||
EXTERNAL_PHY(19)
|
||||
EXTERNAL_PHY(20)
|
||||
EXTERNAL_PHY(21)
|
||||
EXTERNAL_PHY(22)
|
||||
EXTERNAL_PHY(23)
|
||||
EXTERNAL_PHY(24)
|
||||
EXTERNAL_PHY(25)
|
||||
EXTERNAL_PHY(26)
|
||||
EXTERNAL_PHY(27)
|
||||
EXTERNAL_PHY(28)
|
||||
EXTERNAL_PHY(29)
|
||||
EXTERNAL_PHY(30)
|
||||
EXTERNAL_PHY(31)
|
||||
|
||||
EXTERNAL_PHY(24)
|
||||
EXTERNAL_PHY(25)
|
||||
EXTERNAL_PHY(26)
|
||||
EXTERNAL_PHY(27)
|
||||
EXTERNAL_PHY(28)
|
||||
EXTERNAL_PHY(29)
|
||||
EXTERNAL_PHY(30)
|
||||
EXTERNAL_PHY(31)
|
||||
EXTERNAL_PHY(32)
|
||||
EXTERNAL_PHY(33)
|
||||
EXTERNAL_PHY(34)
|
||||
EXTERNAL_PHY(35)
|
||||
EXTERNAL_PHY(36)
|
||||
EXTERNAL_PHY(37)
|
||||
EXTERNAL_PHY(38)
|
||||
EXTERNAL_PHY(39)
|
||||
|
||||
EXTERNAL_PHY(32)
|
||||
EXTERNAL_PHY(33)
|
||||
EXTERNAL_PHY(34)
|
||||
EXTERNAL_PHY(35)
|
||||
EXTERNAL_PHY(36)
|
||||
EXTERNAL_PHY(37)
|
||||
EXTERNAL_PHY(38)
|
||||
EXTERNAL_PHY(39)
|
||||
|
||||
/* RTL8218FB */
|
||||
EXTERNAL_PHY(40)
|
||||
EXTERNAL_PHY(41)
|
||||
EXTERNAL_PHY(42)
|
||||
EXTERNAL_PHY(43)
|
||||
EXTERNAL_PHY(44)
|
||||
EXTERNAL_PHY(45)
|
||||
EXTERNAL_PHY(46)
|
||||
EXTERNAL_PHY(47)
|
||||
};
|
||||
/* RTL8218FB */
|
||||
EXTERNAL_PHY(40)
|
||||
EXTERNAL_PHY(41)
|
||||
EXTERNAL_PHY(42)
|
||||
EXTERNAL_PHY(43)
|
||||
EXTERNAL_PHY(44)
|
||||
EXTERNAL_PHY(45)
|
||||
EXTERNAL_PHY(46)
|
||||
EXTERNAL_PHY(47)
|
||||
};
|
||||
|
||||
&switch0 {
|
||||
|
|
|
|||
|
|
@ -144,77 +144,70 @@
|
|||
};
|
||||
};
|
||||
|
||||
ðernet0 {
|
||||
mdio: mdio-bus {
|
||||
compatible = "realtek,rtl838x-mdio";
|
||||
regmap = <ðernet0>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
&mdio_bus0 {
|
||||
/* External phy RTL8218B #1 */
|
||||
EXTERNAL_PHY(0)
|
||||
EXTERNAL_PHY(1)
|
||||
EXTERNAL_PHY(2)
|
||||
EXTERNAL_PHY(3)
|
||||
EXTERNAL_PHY(4)
|
||||
EXTERNAL_PHY(5)
|
||||
EXTERNAL_PHY(6)
|
||||
EXTERNAL_PHY(7)
|
||||
|
||||
/* External phy RTL8218B #1 */
|
||||
EXTERNAL_PHY(0)
|
||||
EXTERNAL_PHY(1)
|
||||
EXTERNAL_PHY(2)
|
||||
EXTERNAL_PHY(3)
|
||||
EXTERNAL_PHY(4)
|
||||
EXTERNAL_PHY(5)
|
||||
EXTERNAL_PHY(6)
|
||||
EXTERNAL_PHY(7)
|
||||
/* External phy RTL8218B #2 */
|
||||
EXTERNAL_PHY(8)
|
||||
EXTERNAL_PHY(9)
|
||||
EXTERNAL_PHY(10)
|
||||
EXTERNAL_PHY(11)
|
||||
EXTERNAL_PHY(12)
|
||||
EXTERNAL_PHY(13)
|
||||
EXTERNAL_PHY(14)
|
||||
EXTERNAL_PHY(15)
|
||||
|
||||
/* External phy RTL8218B #2 */
|
||||
EXTERNAL_PHY(8)
|
||||
EXTERNAL_PHY(9)
|
||||
EXTERNAL_PHY(10)
|
||||
EXTERNAL_PHY(11)
|
||||
EXTERNAL_PHY(12)
|
||||
EXTERNAL_PHY(13)
|
||||
EXTERNAL_PHY(14)
|
||||
EXTERNAL_PHY(15)
|
||||
/* External phy RTL8218B #3 */
|
||||
EXTERNAL_PHY(16)
|
||||
EXTERNAL_PHY(17)
|
||||
EXTERNAL_PHY(18)
|
||||
EXTERNAL_PHY(19)
|
||||
EXTERNAL_PHY(20)
|
||||
EXTERNAL_PHY(21)
|
||||
EXTERNAL_PHY(22)
|
||||
EXTERNAL_PHY(23)
|
||||
|
||||
/* External phy RTL8218B #3 */
|
||||
EXTERNAL_PHY(16)
|
||||
EXTERNAL_PHY(17)
|
||||
EXTERNAL_PHY(18)
|
||||
EXTERNAL_PHY(19)
|
||||
EXTERNAL_PHY(20)
|
||||
EXTERNAL_PHY(21)
|
||||
EXTERNAL_PHY(22)
|
||||
EXTERNAL_PHY(23)
|
||||
/* External phy RTL8218B #4 */
|
||||
EXTERNAL_PHY(24)
|
||||
EXTERNAL_PHY(25)
|
||||
EXTERNAL_PHY(26)
|
||||
EXTERNAL_PHY(27)
|
||||
EXTERNAL_PHY(28)
|
||||
EXTERNAL_PHY(29)
|
||||
EXTERNAL_PHY(30)
|
||||
EXTERNAL_PHY(31)
|
||||
|
||||
/* External phy RTL8218B #4 */
|
||||
EXTERNAL_PHY(24)
|
||||
EXTERNAL_PHY(25)
|
||||
EXTERNAL_PHY(26)
|
||||
EXTERNAL_PHY(27)
|
||||
EXTERNAL_PHY(28)
|
||||
EXTERNAL_PHY(29)
|
||||
EXTERNAL_PHY(30)
|
||||
EXTERNAL_PHY(31)
|
||||
/* External phy RTL8218B #5 */
|
||||
EXTERNAL_PHY(32)
|
||||
EXTERNAL_PHY(33)
|
||||
EXTERNAL_PHY(34)
|
||||
EXTERNAL_PHY(35)
|
||||
EXTERNAL_PHY(36)
|
||||
EXTERNAL_PHY(37)
|
||||
EXTERNAL_PHY(38)
|
||||
EXTERNAL_PHY(39)
|
||||
|
||||
/* External phy RTL8218B #5 */
|
||||
EXTERNAL_PHY(32)
|
||||
EXTERNAL_PHY(33)
|
||||
EXTERNAL_PHY(34)
|
||||
EXTERNAL_PHY(35)
|
||||
EXTERNAL_PHY(36)
|
||||
EXTERNAL_PHY(37)
|
||||
EXTERNAL_PHY(38)
|
||||
EXTERNAL_PHY(39)
|
||||
/* External phy RTL8218B #6 */
|
||||
EXTERNAL_PHY(40)
|
||||
EXTERNAL_PHY(41)
|
||||
EXTERNAL_PHY(42)
|
||||
EXTERNAL_PHY(43)
|
||||
EXTERNAL_PHY(44)
|
||||
EXTERNAL_PHY(45)
|
||||
EXTERNAL_PHY(46)
|
||||
EXTERNAL_PHY(47)
|
||||
|
||||
/* External phy RTL8218B #6 */
|
||||
EXTERNAL_PHY(40)
|
||||
EXTERNAL_PHY(41)
|
||||
EXTERNAL_PHY(42)
|
||||
EXTERNAL_PHY(43)
|
||||
EXTERNAL_PHY(44)
|
||||
EXTERNAL_PHY(45)
|
||||
EXTERNAL_PHY(46)
|
||||
EXTERNAL_PHY(47)
|
||||
|
||||
/* RTL8393 Internal SerDes */
|
||||
INTERNAL_PHY_SDS(48, 12)
|
||||
INTERNAL_PHY_SDS(49, 13)
|
||||
};
|
||||
/* RTL8393 Internal SerDes */
|
||||
INTERNAL_PHY_SDS(48, 12)
|
||||
INTERNAL_PHY_SDS(49, 13)
|
||||
};
|
||||
|
||||
&switch0 {
|
||||
|
|
|
|||
|
|
@ -131,69 +131,64 @@
|
|||
ðernet0 {
|
||||
nvmem-cells = <&macaddr_ubootenv_ethaddr 0>;
|
||||
nvmem-cell-names = "mac-address";
|
||||
};
|
||||
|
||||
mdio: mdio-bus {
|
||||
compatible = "realtek,rtl838x-mdio";
|
||||
regmap = <ðernet0>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
&mdio_bus0 {
|
||||
/* External RTL8224 PHY */
|
||||
phy0: ethernet-phy@0 {
|
||||
reg = <0>;
|
||||
compatible = "ethernet-phy-ieee802.3-c45";
|
||||
rtl9300,smi-address = <0 0>;
|
||||
sds = < 2 >;
|
||||
};
|
||||
|
||||
/* External RTL8224 PHY */
|
||||
phy0: ethernet-phy@0 {
|
||||
reg = <0>;
|
||||
compatible = "ethernet-phy-ieee802.3-c45";
|
||||
rtl9300,smi-address = <0 0>;
|
||||
sds = < 2 >;
|
||||
};
|
||||
phy1: ethernet-phy@1 {
|
||||
reg = <1>;
|
||||
compatible = "ethernet-phy-ieee802.3-c45";
|
||||
rtl9300,smi-address = <0 1>;
|
||||
sds = < 2 >;
|
||||
};
|
||||
|
||||
phy1: ethernet-phy@1 {
|
||||
reg = <1>;
|
||||
compatible = "ethernet-phy-ieee802.3-c45";
|
||||
rtl9300,smi-address = <0 1>;
|
||||
sds = < 2 >;
|
||||
};
|
||||
phy2: ethernet-phy@2 {
|
||||
reg = <2>;
|
||||
compatible = "ethernet-phy-ieee802.3-c45";
|
||||
rtl9300,smi-address = <0 2>;
|
||||
sds = < 2 >;
|
||||
};
|
||||
|
||||
phy2: ethernet-phy@2 {
|
||||
reg = <2>;
|
||||
compatible = "ethernet-phy-ieee802.3-c45";
|
||||
rtl9300,smi-address = <0 2>;
|
||||
sds = < 2 >;
|
||||
};
|
||||
phy3: ethernet-phy@3 {
|
||||
reg = <3>;
|
||||
compatible = "ethernet-phy-ieee802.3-c45";
|
||||
rtl9300,smi-address = <0 3>;
|
||||
sds = < 2 >;
|
||||
};
|
||||
|
||||
phy3: ethernet-phy@3 {
|
||||
reg = <3>;
|
||||
compatible = "ethernet-phy-ieee802.3-c45";
|
||||
rtl9300,smi-address = <0 3>;
|
||||
sds = < 2 >;
|
||||
};
|
||||
phy8: ethernet-phy@8 {
|
||||
reg = <8>;
|
||||
compatible = "ethernet-phy-ieee802.3-c45";
|
||||
rtl9300,smi-address = <0 4>;
|
||||
sds = < 3 >;
|
||||
};
|
||||
|
||||
phy8: ethernet-phy@8 {
|
||||
reg = <8>;
|
||||
compatible = "ethernet-phy-ieee802.3-c45";
|
||||
rtl9300,smi-address = <0 4>;
|
||||
sds = < 3 >;
|
||||
};
|
||||
phy9: ethernet-phy@9 {
|
||||
reg = <9>;
|
||||
compatible = "ethernet-phy-ieee802.3-c45";
|
||||
rtl9300,smi-address = <0 5>;
|
||||
sds = < 3 >;
|
||||
};
|
||||
|
||||
phy9: ethernet-phy@9 {
|
||||
reg = <9>;
|
||||
compatible = "ethernet-phy-ieee802.3-c45";
|
||||
rtl9300,smi-address = <0 5>;
|
||||
sds = < 3 >;
|
||||
};
|
||||
phy10: ethernet-phy@10 {
|
||||
reg = <10>;
|
||||
compatible = "ethernet-phy-ieee802.3-c45";
|
||||
rtl9300,smi-address = <0 6>;
|
||||
sds = < 3 >;
|
||||
};
|
||||
|
||||
phy10: ethernet-phy@10 {
|
||||
reg = <10>;
|
||||
compatible = "ethernet-phy-ieee802.3-c45";
|
||||
rtl9300,smi-address = <0 6>;
|
||||
sds = < 3 >;
|
||||
};
|
||||
|
||||
phy11: ethernet-phy@11 {
|
||||
reg = <11>;
|
||||
compatible = "ethernet-phy-ieee802.3-c45";
|
||||
rtl9300,smi-address = <0 7>;
|
||||
sds = < 3 >;
|
||||
};
|
||||
phy11: ethernet-phy@11 {
|
||||
reg = <11>;
|
||||
compatible = "ethernet-phy-ieee802.3-c45";
|
||||
rtl9300,smi-address = <0 7>;
|
||||
sds = < 3 >;
|
||||
};
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -35,7 +35,7 @@
|
|||
};
|
||||
};
|
||||
|
||||
&mdio {
|
||||
&mdio_bus0 {
|
||||
INTERNAL_PHY_SDS(26, 8)
|
||||
INTERNAL_PHY_SDS(27, 9)
|
||||
};
|
||||
|
|
|
|||
|
|
@ -8,7 +8,7 @@
|
|||
model = "Zyxel XGS1210-12 A1 Switch";
|
||||
};
|
||||
|
||||
&mdio {
|
||||
&mdio_bus0 {
|
||||
phy24: ethernet-phy@24 {
|
||||
reg = <24>;
|
||||
compatible = "ethernet-phy-ieee802.3-c45";
|
||||
|
|
|
|||
|
|
@ -146,61 +146,54 @@
|
|||
};
|
||||
};
|
||||
|
||||
ðernet0 {
|
||||
mdio: mdio-bus {
|
||||
compatible = "realtek,rtl838x-mdio";
|
||||
regmap = <ðernet0>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
/* External RTL8218D PHY */
|
||||
phy0: ethernet-phy@0 {
|
||||
reg = <0>;
|
||||
compatible = "ethernet-phy-ieee802.3-c22";
|
||||
rtl9300,smi-address = <0 0>;
|
||||
sds = < 2 >;
|
||||
// Disabled because we do not know how to bring up again
|
||||
// reset-gpios = <&gpio0 21 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
phy1: ethernet-phy@1 {
|
||||
reg = <1>;
|
||||
compatible = "ethernet-phy-ieee802.3-c22";
|
||||
rtl9300,smi-address = <0 1>;
|
||||
};
|
||||
phy2: ethernet-phy@2 {
|
||||
reg = <2>;
|
||||
compatible = "ethernet-phy-ieee802.3-c22";
|
||||
rtl9300,smi-address = <0 2>;
|
||||
};
|
||||
phy3: ethernet-phy@3 {
|
||||
reg = <3>;
|
||||
compatible = "ethernet-phy-ieee802.3-c22";
|
||||
rtl9300,smi-address = <0 3>;
|
||||
};
|
||||
phy4: ethernet-phy@4 {
|
||||
reg = <4>;
|
||||
compatible = "ethernet-phy-ieee802.3-c22";
|
||||
rtl9300,smi-address = <0 4>;
|
||||
};
|
||||
phy5: ethernet-phy@5 {
|
||||
reg = <5>;
|
||||
compatible = "ethernet-phy-ieee802.3-c22";
|
||||
rtl9300,smi-address = <0 5>;
|
||||
};
|
||||
phy6: ethernet-phy@6 {
|
||||
reg = <6>;
|
||||
compatible = "ethernet-phy-ieee802.3-c22";
|
||||
rtl9300,smi-address = <0 6>;
|
||||
};
|
||||
phy7: ethernet-phy@7 {
|
||||
reg = <7>;
|
||||
compatible = "ethernet-phy-ieee802.3-c22";
|
||||
rtl9300,smi-address = <0 7>;
|
||||
};
|
||||
|
||||
INTERNAL_PHY_SDS(26, 8)
|
||||
INTERNAL_PHY_SDS(27, 9)
|
||||
&mdio_bus0 {
|
||||
/* External RTL8218D PHY */
|
||||
phy0: ethernet-phy@0 {
|
||||
reg = <0>;
|
||||
compatible = "ethernet-phy-ieee802.3-c22";
|
||||
rtl9300,smi-address = <0 0>;
|
||||
sds = < 2 >;
|
||||
// Disabled because we do not know how to bring up again
|
||||
// reset-gpios = <&gpio0 21 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
phy1: ethernet-phy@1 {
|
||||
reg = <1>;
|
||||
compatible = "ethernet-phy-ieee802.3-c22";
|
||||
rtl9300,smi-address = <0 1>;
|
||||
};
|
||||
phy2: ethernet-phy@2 {
|
||||
reg = <2>;
|
||||
compatible = "ethernet-phy-ieee802.3-c22";
|
||||
rtl9300,smi-address = <0 2>;
|
||||
};
|
||||
phy3: ethernet-phy@3 {
|
||||
reg = <3>;
|
||||
compatible = "ethernet-phy-ieee802.3-c22";
|
||||
rtl9300,smi-address = <0 3>;
|
||||
};
|
||||
phy4: ethernet-phy@4 {
|
||||
reg = <4>;
|
||||
compatible = "ethernet-phy-ieee802.3-c22";
|
||||
rtl9300,smi-address = <0 4>;
|
||||
};
|
||||
phy5: ethernet-phy@5 {
|
||||
reg = <5>;
|
||||
compatible = "ethernet-phy-ieee802.3-c22";
|
||||
rtl9300,smi-address = <0 5>;
|
||||
};
|
||||
phy6: ethernet-phy@6 {
|
||||
reg = <6>;
|
||||
compatible = "ethernet-phy-ieee802.3-c22";
|
||||
rtl9300,smi-address = <0 6>;
|
||||
};
|
||||
phy7: ethernet-phy@7 {
|
||||
reg = <7>;
|
||||
compatible = "ethernet-phy-ieee802.3-c22";
|
||||
rtl9300,smi-address = <0 7>;
|
||||
};
|
||||
|
||||
INTERNAL_PHY_SDS(26, 8)
|
||||
INTERNAL_PHY_SDS(27, 9)
|
||||
};
|
||||
|
||||
&switch0 {
|
||||
|
|
|
|||
|
|
@ -220,91 +220,84 @@
|
|||
};
|
||||
};
|
||||
|
||||
ðernet0 {
|
||||
mdio: mdio-bus {
|
||||
compatible = "realtek,rtl838x-mdio";
|
||||
regmap = <ðernet0>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
/* External RTL8218D PHY */
|
||||
phy0: ethernet-phy@0 {
|
||||
reg = <0>;
|
||||
compatible = "ethernet-phy-ieee802.3-c22";
|
||||
rtl9300,smi-address = <0 0>;
|
||||
sds = < 2 >;
|
||||
// Disabled because we do not know how to bring up again
|
||||
// reset-gpios = <&gpio0 21 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
phy1: ethernet-phy@1 {
|
||||
reg = <1>;
|
||||
compatible = "ethernet-phy-ieee802.3-c22";
|
||||
rtl9300,smi-address = <0 1>;
|
||||
};
|
||||
phy2: ethernet-phy@2 {
|
||||
reg = <2>;
|
||||
compatible = "ethernet-phy-ieee802.3-c22";
|
||||
rtl9300,smi-address = <0 2>;
|
||||
};
|
||||
phy3: ethernet-phy@3 {
|
||||
reg = <3>;
|
||||
compatible = "ethernet-phy-ieee802.3-c22";
|
||||
rtl9300,smi-address = <0 3>;
|
||||
};
|
||||
phy4: ethernet-phy@4 {
|
||||
reg = <4>;
|
||||
compatible = "ethernet-phy-ieee802.3-c22";
|
||||
rtl9300,smi-address = <0 4>;
|
||||
};
|
||||
phy5: ethernet-phy@5 {
|
||||
reg = <5>;
|
||||
compatible = "ethernet-phy-ieee802.3-c22";
|
||||
rtl9300,smi-address = <0 5>;
|
||||
};
|
||||
phy6: ethernet-phy@6 {
|
||||
reg = <6>;
|
||||
compatible = "ethernet-phy-ieee802.3-c22";
|
||||
rtl9300,smi-address = <0 6>;
|
||||
};
|
||||
phy7: ethernet-phy@7 {
|
||||
reg = <7>;
|
||||
compatible = "ethernet-phy-ieee802.3-c22";
|
||||
rtl9300,smi-address = <0 7>;
|
||||
};
|
||||
|
||||
/* External Aquantia 113C PHYs */
|
||||
phy24: ethernet-phy@24 {
|
||||
reg = <24>;
|
||||
compatible = "ethernet-phy-ieee802.3-c45";
|
||||
rtl9300,smi-address = <1 8>;
|
||||
sds = < 6 >;
|
||||
// Disabled because we do not know how to bring up again
|
||||
// reset-gpios = <&gpio0 21 GPIO_ACTIVE_LOW>;
|
||||
#thermal-sensor-cells = <0>;
|
||||
};
|
||||
|
||||
phy25: ethernet-phy@25 {
|
||||
reg = <25>;
|
||||
compatible = "ethernet-phy-ieee802.3-c45";
|
||||
rtl9300,smi-address = <2 8>;
|
||||
sds = < 7 >;
|
||||
// Disabled because we do not know how to bring up again
|
||||
// reset-gpios = <&gpio0 21 GPIO_ACTIVE_LOW>;
|
||||
#thermal-sensor-cells = <0>;
|
||||
};
|
||||
|
||||
phy26: ethernet-phy@26 {
|
||||
reg = <26>;
|
||||
compatible = "ethernet-phy-ieee802.3-c45";
|
||||
rtl9300,smi-address = <3 8>;
|
||||
sds = < 8 >;
|
||||
// Disabled because we do not know how to bring up again
|
||||
// reset-gpios = <&gpio0 21 GPIO_ACTIVE_LOW>;
|
||||
#thermal-sensor-cells = <0>;
|
||||
};
|
||||
|
||||
INTERNAL_PHY_SDS(27, 9)
|
||||
&mdio_bus0 {
|
||||
/* External RTL8218D PHY */
|
||||
phy0: ethernet-phy@0 {
|
||||
reg = <0>;
|
||||
compatible = "ethernet-phy-ieee802.3-c22";
|
||||
rtl9300,smi-address = <0 0>;
|
||||
sds = < 2 >;
|
||||
// Disabled because we do not know how to bring up again
|
||||
// reset-gpios = <&gpio0 21 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
phy1: ethernet-phy@1 {
|
||||
reg = <1>;
|
||||
compatible = "ethernet-phy-ieee802.3-c22";
|
||||
rtl9300,smi-address = <0 1>;
|
||||
};
|
||||
phy2: ethernet-phy@2 {
|
||||
reg = <2>;
|
||||
compatible = "ethernet-phy-ieee802.3-c22";
|
||||
rtl9300,smi-address = <0 2>;
|
||||
};
|
||||
phy3: ethernet-phy@3 {
|
||||
reg = <3>;
|
||||
compatible = "ethernet-phy-ieee802.3-c22";
|
||||
rtl9300,smi-address = <0 3>;
|
||||
};
|
||||
phy4: ethernet-phy@4 {
|
||||
reg = <4>;
|
||||
compatible = "ethernet-phy-ieee802.3-c22";
|
||||
rtl9300,smi-address = <0 4>;
|
||||
};
|
||||
phy5: ethernet-phy@5 {
|
||||
reg = <5>;
|
||||
compatible = "ethernet-phy-ieee802.3-c22";
|
||||
rtl9300,smi-address = <0 5>;
|
||||
};
|
||||
phy6: ethernet-phy@6 {
|
||||
reg = <6>;
|
||||
compatible = "ethernet-phy-ieee802.3-c22";
|
||||
rtl9300,smi-address = <0 6>;
|
||||
};
|
||||
phy7: ethernet-phy@7 {
|
||||
reg = <7>;
|
||||
compatible = "ethernet-phy-ieee802.3-c22";
|
||||
rtl9300,smi-address = <0 7>;
|
||||
};
|
||||
|
||||
/* External Aquantia 113C PHYs */
|
||||
phy24: ethernet-phy@24 {
|
||||
reg = <24>;
|
||||
compatible = "ethernet-phy-ieee802.3-c45";
|
||||
rtl9300,smi-address = <1 8>;
|
||||
sds = < 6 >;
|
||||
// Disabled because we do not know how to bring up again
|
||||
// reset-gpios = <&gpio0 21 GPIO_ACTIVE_LOW>;
|
||||
#thermal-sensor-cells = <0>;
|
||||
};
|
||||
|
||||
phy25: ethernet-phy@25 {
|
||||
reg = <25>;
|
||||
compatible = "ethernet-phy-ieee802.3-c45";
|
||||
rtl9300,smi-address = <2 8>;
|
||||
sds = < 7 >;
|
||||
// Disabled because we do not know how to bring up again
|
||||
// reset-gpios = <&gpio0 21 GPIO_ACTIVE_LOW>;
|
||||
#thermal-sensor-cells = <0>;
|
||||
};
|
||||
|
||||
phy26: ethernet-phy@26 {
|
||||
reg = <26>;
|
||||
compatible = "ethernet-phy-ieee802.3-c45";
|
||||
rtl9300,smi-address = <3 8>;
|
||||
sds = < 8 >;
|
||||
// Disabled because we do not know how to bring up again
|
||||
// reset-gpios = <&gpio0 21 GPIO_ACTIVE_LOW>;
|
||||
#thermal-sensor-cells = <0>;
|
||||
};
|
||||
|
||||
INTERNAL_PHY_SDS(27, 9)
|
||||
};
|
||||
|
||||
&switch0 {
|
||||
|
|
|
|||
|
|
@ -126,68 +126,61 @@
|
|||
};
|
||||
};
|
||||
|
||||
ðernet0 {
|
||||
mdio: mdio-bus {
|
||||
compatible = "realtek,rtl838x-mdio";
|
||||
regmap = <ðernet0>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
&mdio_bus0 {
|
||||
phy0: ethernet-phy@0 {
|
||||
compatible = "ethernet-phy-ieee802.3-c45";
|
||||
rtl9300,smi-address = <0 0>;
|
||||
reg = <0>;
|
||||
sds = <2>;
|
||||
};
|
||||
|
||||
phy0: ethernet-phy@0 {
|
||||
compatible = "ethernet-phy-ieee802.3-c45";
|
||||
rtl9300,smi-address = <0 0>;
|
||||
reg = <0>;
|
||||
sds = <2>;
|
||||
};
|
||||
phy8: ethernet-phy@8 {
|
||||
compatible = "ethernet-phy-ieee802.3-c45";
|
||||
rtl9300,smi-address = <0 1>;
|
||||
reg = <8>;
|
||||
sds = <3>;
|
||||
};
|
||||
|
||||
phy8: ethernet-phy@8 {
|
||||
compatible = "ethernet-phy-ieee802.3-c45";
|
||||
rtl9300,smi-address = <0 1>;
|
||||
reg = <8>;
|
||||
sds = <3>;
|
||||
};
|
||||
phy16: ethernet-phy@16 {
|
||||
compatible = "ethernet-phy-ieee802.3-c45";
|
||||
rtl9300,smi-address = <0 2>;
|
||||
reg = <16>;
|
||||
sds = <4>;
|
||||
};
|
||||
|
||||
phy16: ethernet-phy@16 {
|
||||
compatible = "ethernet-phy-ieee802.3-c45";
|
||||
rtl9300,smi-address = <0 2>;
|
||||
reg = <16>;
|
||||
sds = <4>;
|
||||
};
|
||||
phy20: ethernet-phy@20 {
|
||||
compatible = "ethernet-phy-ieee802.3-c45";
|
||||
rtl9300,smi-address = <0 3>;
|
||||
reg = <20>;
|
||||
sds = <5>;
|
||||
};
|
||||
|
||||
phy20: ethernet-phy@20 {
|
||||
compatible = "ethernet-phy-ieee802.3-c45";
|
||||
rtl9300,smi-address = <0 3>;
|
||||
reg = <20>;
|
||||
sds = <5>;
|
||||
};
|
||||
phy24: ethernet-phy@24 {
|
||||
compatible = "ethernet-phy-ieee802.3-c45";
|
||||
rtl9300,smi-address = <3 16>;
|
||||
reg = <24>;
|
||||
sds = <6>;
|
||||
};
|
||||
|
||||
phy24: ethernet-phy@24 {
|
||||
compatible = "ethernet-phy-ieee802.3-c45";
|
||||
rtl9300,smi-address = <3 16>;
|
||||
reg = <24>;
|
||||
sds = <6>;
|
||||
};
|
||||
phy25: ethernet-phy@25 {
|
||||
compatible = "ethernet-phy-ieee802.3-c45";
|
||||
rtl9300,smi-address = <3 17>;
|
||||
reg = <25>;
|
||||
sds = <7>;
|
||||
};
|
||||
|
||||
phy25: ethernet-phy@25 {
|
||||
compatible = "ethernet-phy-ieee802.3-c45";
|
||||
rtl9300,smi-address = <3 17>;
|
||||
reg = <25>;
|
||||
sds = <7>;
|
||||
};
|
||||
phy26: ethernet-phy@26 {
|
||||
compatible = "ethernet-phy-ieee802.3-c45";
|
||||
rtl9300,smi-address = <3 18>;
|
||||
reg = <26>;
|
||||
sds = <8>;
|
||||
};
|
||||
|
||||
phy26: ethernet-phy@26 {
|
||||
compatible = "ethernet-phy-ieee802.3-c45";
|
||||
rtl9300,smi-address = <3 18>;
|
||||
reg = <26>;
|
||||
sds = <8>;
|
||||
};
|
||||
|
||||
phy27: ethernet-phy@27 {
|
||||
compatible = "ethernet-phy-ieee802.3-c45";
|
||||
rtl9300,smi-address = <3 19>;
|
||||
reg = <27>;
|
||||
sds = <9>;
|
||||
};
|
||||
phy27: ethernet-phy@27 {
|
||||
compatible = "ethernet-phy-ieee802.3-c45";
|
||||
rtl9300,smi-address = <3 19>;
|
||||
reg = <27>;
|
||||
sds = <9>;
|
||||
};
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -232,22 +232,15 @@
|
|||
};
|
||||
};
|
||||
|
||||
ðernet0 {
|
||||
mdio: mdio-bus {
|
||||
compatible = "realtek,rtl838x-mdio";
|
||||
regmap = <ðernet0>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
INTERNAL_PHY_SDS(0, 2)
|
||||
INTERNAL_PHY_SDS(8, 3)
|
||||
INTERNAL_PHY_SDS(16, 4)
|
||||
INTERNAL_PHY_SDS(20, 5)
|
||||
INTERNAL_PHY_SDS(24, 6)
|
||||
INTERNAL_PHY_SDS(25, 7)
|
||||
INTERNAL_PHY_SDS(26, 8)
|
||||
INTERNAL_PHY_SDS(27, 9)
|
||||
};
|
||||
&mdio_bus0 {
|
||||
INTERNAL_PHY_SDS(0, 2)
|
||||
INTERNAL_PHY_SDS(8, 3)
|
||||
INTERNAL_PHY_SDS(16, 4)
|
||||
INTERNAL_PHY_SDS(20, 5)
|
||||
INTERNAL_PHY_SDS(24, 6)
|
||||
INTERNAL_PHY_SDS(25, 7)
|
||||
INTERNAL_PHY_SDS(26, 8)
|
||||
INTERNAL_PHY_SDS(27, 9)
|
||||
};
|
||||
|
||||
&switch0 {
|
||||
|
|
|
|||
|
|
@ -221,22 +221,15 @@
|
|||
};
|
||||
};
|
||||
|
||||
ðernet0 {
|
||||
mdio: mdio-bus {
|
||||
compatible = "realtek,rtl838x-mdio";
|
||||
regmap = <ðernet0>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
INTERNAL_PHY_SDS(0, 2)
|
||||
INTERNAL_PHY_SDS(8, 3)
|
||||
INTERNAL_PHY_SDS(16, 4)
|
||||
INTERNAL_PHY_SDS(20, 5)
|
||||
INTERNAL_PHY_SDS(24, 6)
|
||||
INTERNAL_PHY_SDS(25, 7)
|
||||
INTERNAL_PHY_SDS(26, 8)
|
||||
INTERNAL_PHY_SDS(27, 9)
|
||||
};
|
||||
&mdio_bus0 {
|
||||
INTERNAL_PHY_SDS(0, 2)
|
||||
INTERNAL_PHY_SDS(8, 3)
|
||||
INTERNAL_PHY_SDS(16, 4)
|
||||
INTERNAL_PHY_SDS(20, 5)
|
||||
INTERNAL_PHY_SDS(24, 6)
|
||||
INTERNAL_PHY_SDS(25, 7)
|
||||
INTERNAL_PHY_SDS(26, 8)
|
||||
INTERNAL_PHY_SDS(27, 9)
|
||||
};
|
||||
|
||||
&switch0 {
|
||||
|
|
|
|||
|
|
@ -243,22 +243,15 @@
|
|||
};
|
||||
};
|
||||
|
||||
ðernet0 {
|
||||
mdio: mdio-bus {
|
||||
compatible = "realtek,rtl838x-mdio";
|
||||
regmap = <ðernet0>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
INTERNAL_PHY_SDS(0, 2)
|
||||
INTERNAL_PHY_SDS(8, 3)
|
||||
INTERNAL_PHY_SDS(16, 4)
|
||||
INTERNAL_PHY_SDS(20, 5)
|
||||
INTERNAL_PHY_SDS(24, 6)
|
||||
INTERNAL_PHY_SDS(25, 7)
|
||||
INTERNAL_PHY_SDS(26, 8)
|
||||
INTERNAL_PHY_SDS(27, 9)
|
||||
};
|
||||
&mdio_bus0 {
|
||||
INTERNAL_PHY_SDS(0, 2)
|
||||
INTERNAL_PHY_SDS(8, 3)
|
||||
INTERNAL_PHY_SDS(16, 4)
|
||||
INTERNAL_PHY_SDS(20, 5)
|
||||
INTERNAL_PHY_SDS(24, 6)
|
||||
INTERNAL_PHY_SDS(25, 7)
|
||||
INTERNAL_PHY_SDS(26, 8)
|
||||
INTERNAL_PHY_SDS(27, 9)
|
||||
};
|
||||
|
||||
&switch0 {
|
||||
|
|
|
|||
|
|
@ -240,22 +240,15 @@
|
|||
};
|
||||
};
|
||||
|
||||
ðernet0 {
|
||||
mdio: mdio-bus {
|
||||
compatible = "realtek,rtl838x-mdio";
|
||||
regmap = <ðernet0>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
INTERNAL_PHY_SDS(0, 2)
|
||||
INTERNAL_PHY_SDS(8, 3)
|
||||
INTERNAL_PHY_SDS(16, 4)
|
||||
INTERNAL_PHY_SDS(20, 5)
|
||||
INTERNAL_PHY_SDS(24, 6)
|
||||
INTERNAL_PHY_SDS(25, 7)
|
||||
INTERNAL_PHY_SDS(26, 8)
|
||||
INTERNAL_PHY_SDS(27, 9)
|
||||
};
|
||||
&mdio_bus0 {
|
||||
INTERNAL_PHY_SDS(0, 2)
|
||||
INTERNAL_PHY_SDS(8, 3)
|
||||
INTERNAL_PHY_SDS(16, 4)
|
||||
INTERNAL_PHY_SDS(20, 5)
|
||||
INTERNAL_PHY_SDS(24, 6)
|
||||
INTERNAL_PHY_SDS(25, 7)
|
||||
INTERNAL_PHY_SDS(26, 8)
|
||||
INTERNAL_PHY_SDS(27, 9)
|
||||
};
|
||||
|
||||
&switch0 {
|
||||
|
|
|
|||
|
|
@ -274,9 +274,9 @@ static int __init rtl83xx_mdio_probe(struct rtl838x_switch_priv *priv)
|
|||
int ret;
|
||||
u32 pn;
|
||||
|
||||
np = of_find_compatible_node(NULL, NULL, "realtek,rtl838x-eth");
|
||||
np = of_find_compatible_node(NULL, NULL, "realtek,otto-mdio");
|
||||
if (!np) {
|
||||
dev_err(priv->dev, "ethernet node not found");
|
||||
dev_err(priv->dev, "mdio controller node not found");
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -1397,7 +1397,7 @@ static int rtmdio_get_family(void)
|
|||
|
||||
static int rtmdio_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct device_node *dn, *np, *mii_np;
|
||||
struct device_node *dn, *mii_np;
|
||||
struct device *dev = &pdev->dev;
|
||||
struct rtmdio_bus_priv *priv;
|
||||
struct mii_bus *bus;
|
||||
|
|
@ -1407,11 +1407,7 @@ static int rtmdio_probe(struct platform_device *pdev)
|
|||
family = rtmdio_get_family();
|
||||
dev_info(dev, "probing RTL%04x family mdio bus\n", family);
|
||||
|
||||
np = of_find_compatible_node(NULL, NULL, "realtek,rtl838x-eth");
|
||||
if (!np)
|
||||
return -ENODEV;
|
||||
|
||||
mii_np = of_get_child_by_name(np, "mdio-bus");
|
||||
mii_np = of_get_child_by_name(dev->of_node, "mdio-bus");
|
||||
if (!mii_np)
|
||||
return -ENODEV;
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue