From 82f05bc48821f3709f22f3d1f6e45290547f74be Mon Sep 17 00:00:00 2001
From: Weijie Gao <weijie.gao@mediatek.com>
Date: Tue, 17 Dec 2024 16:39:41 +0800
Subject: [PATCH 05/10] net: mediatek: fix sgmii selection for mt7622

Unlike other platforms, mt7622 has only one SGMII and it can be
attached to either gmac1 or gmac2. So the register field of the
sgmii selection differs from other platforms as newer platforms can
control each sgmii individually.

This patch adds a new capability for mt7622 to handle this case.

Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
---
 drivers/net/mtk_eth.c | 10 ++++++++--
 drivers/net/mtk_eth.h |  8 ++++++--
 2 files changed, 14 insertions(+), 4 deletions(-)

--- a/drivers/net/mtk_eth.c
+++ b/drivers/net/mtk_eth.c
@@ -1434,7 +1434,7 @@ static void mtk_usxgmii_an_init(struct m
 
 static void mtk_mac_init(struct mtk_eth_priv *priv)
 {
-	int i, ge_mode = 0;
+	int i, sgmii_sel_mask = 0, ge_mode = 0;
 	u32 mcr;
 
 	switch (priv->phy_interface) {
@@ -1450,8 +1450,13 @@ static void mtk_mac_init(struct mtk_eth_
 		}
 
 		ge_mode = GE_MODE_RGMII;
-		mtk_ethsys_rmw(priv, ETHSYS_SYSCFG1_REG, SYSCFG1_SGMII_SEL_M,
+
+		if (MTK_HAS_CAPS(priv->soc->caps, MTK_ETH_PATH_MT7622_SGMII))
+			sgmii_sel_mask = SYSCFG1_SGMII_SEL_M;
+
+		mtk_ethsys_rmw(priv, ETHSYS_SYSCFG1_REG, sgmii_sel_mask,
 			       SYSCFG1_SGMII_SEL(priv->gmac_id));
+
 		if (priv->phy_interface == PHY_INTERFACE_MODE_SGMII)
 			mtk_sgmii_an_init(priv);
 		else
@@ -2112,6 +2117,7 @@ static const struct mtk_soc_data mt7623_
 };
 
 static const struct mtk_soc_data mt7622_data = {
+	.caps = MT7622_CAPS,
 	.ana_rgc3 = 0x2028,
 	.gdma_count = 2,
 	.pdma_base = PDMA_V1_BASE,
--- a/drivers/net/mtk_eth.h
+++ b/drivers/net/mtk_eth.h
@@ -23,6 +23,7 @@ enum mkt_eth_capabilities {
 	/* PATH BITS */
 	MTK_ETH_PATH_GMAC1_TRGMII_BIT,
 	MTK_ETH_PATH_GMAC2_SGMII_BIT,
+	MTK_ETH_PATH_MT7622_SGMII_BIT,
 };
 
 #define MTK_TRGMII			BIT(MTK_TRGMII_BIT)
@@ -36,6 +37,7 @@ enum mkt_eth_capabilities {
 #define MTK_ETH_PATH_GMAC1_TRGMII	BIT(MTK_ETH_PATH_GMAC1_TRGMII_BIT)
 
 #define MTK_ETH_PATH_GMAC2_SGMII	BIT(MTK_ETH_PATH_GMAC2_SGMII_BIT)
+#define MTK_ETH_PATH_MT7622_SGMII	BIT(MTK_ETH_PATH_MT7622_SGMII_BIT)
 
 #define MTK_GMAC1_TRGMII	(MTK_ETH_PATH_GMAC1_TRGMII | MTK_TRGMII)
 
@@ -45,6 +47,8 @@ enum mkt_eth_capabilities {
 
 #define MT7621_CAPS  (MTK_GMAC1_TRGMII | MTK_TRGMII_MT7621_CLK)
 
+#define MT7622_CAPS  (MTK_ETH_PATH_MT7622_SGMII)
+
 #define MT7623_CAPS  (MTK_GMAC1_TRGMII)
 
 #define MT7981_CAPS  (MTK_GMAC2_U3_QPHY | MTK_NETSYS_V2)
@@ -68,8 +72,8 @@ enum mkt_eth_capabilities {
 #define ETHSYS_SYSCFG1_REG		0x14
 #define SYSCFG1_GE_MODE_S(n)		(12 + ((n) * 2))
 #define SYSCFG1_GE_MODE_M		0x3
-#define SYSCFG1_SGMII_SEL_M		(0x3 << 8)
-#define SYSCFG1_SGMII_SEL(gmac)		((!(gmac)) ? BIT(9) : BIT(8))
+#define SYSCFG1_SGMII_SEL_M		GENMASK(9, 8)
+#define SYSCFG1_SGMII_SEL(gmac)		BIT(9 - (gmac))
 
 #define ETHSYS_CLKCFG0_REG		0x2c
 #define ETHSYS_TRGMII_CLK_SEL362_5	BIT(11)
