3b64ea4768
This phy supports both 24MHz and 100MHz clock inputs. By default it's using XTAL 24MHz and the 100MHz clock is a alternate reference clock. Add supports to use alternate reference clock in case 24MHz clock can't work well. Reviewed-by: Frank Li <Frank.Li@nxp.com> Signed-off-by: Xu Yang <xu.yang_2@nxp.com> Link: https://patch.msgid.link/20251118071947.2504789-2-xu.yang_2@nxp.com Signed-off-by: Vinod Koul <vkoul@kernel.org> |
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| .. | ||
| allwinner | ||
| amlogic | ||
| broadcom | ||
| cadence | ||
| freescale | ||
| hisilicon | ||
| ingenic | ||
| intel | ||
| lantiq | ||
| marvell | ||
| mediatek | ||
| microchip | ||
| motorola | ||
| mscc | ||
| nuvoton | ||
| qualcomm | ||
| ralink | ||
| realtek | ||
| renesas | ||
| rockchip | ||
| samsung | ||
| socionext | ||
| sophgo | ||
| st | ||
| starfive | ||
| sunplus | ||
| tegra | ||
| ti | ||
| xilinx | ||
| Kconfig | ||
| Makefile | ||
| phy-airoha-pcie-regs.h | ||
| phy-airoha-pcie.c | ||
| phy-can-transceiver.c | ||
| phy-core-mipi-dphy.c | ||
| phy-core.c | ||
| phy-lgm-usb.c | ||
| phy-lpc18xx-usb-otg.c | ||
| phy-nxp-ptn3222.c | ||
| phy-pistachio-usb.c | ||
| phy-snps-eusb2.c | ||
| phy-xgene.c | ||