178 lines
7.4 KiB
ReStructuredText
178 lines
7.4 KiB
ReStructuredText
======================================================
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HiSilicon SoC uncore Performance Monitoring Unit (PMU)
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======================================================
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The HiSilicon SoC chip includes various independent system device PMUs
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such as L3 cache (L3C), Hydra Home Agent (HHA) and DDRC. These PMUs are
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independent and have hardware logic to gather statistics and performance
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information.
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The HiSilicon SoC encapsulates multiple CPU and IO dies. Each CPU cluster
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(CCL) is made up of 4 cpu cores sharing one L3 cache; each CPU die is
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called Super CPU cluster (SCCL) and is made up of 6 CCLs. Each SCCL has
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two HHAs (0 - 1) and four DDRCs (0 - 3), respectively.
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HiSilicon SoC uncore PMU driver
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-------------------------------
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Each device PMU has separate registers for event counting, control and
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interrupt, and the PMU driver shall register perf PMU drivers like L3C,
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HHA and DDRC etc. The available events and configuration options shall
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be described in the sysfs, see::
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/sys/bus/event_source/devices/hisi_sccl{X}_<l3c{Y}/hha{Y}/ddrc{Y}>
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The "perf list" command shall list the available events from sysfs.
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Each L3C, HHA and DDRC is registered as a separate PMU with perf. The PMU
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name will appear in event listing as hisi_sccl<sccl-id>_module<index-id>.
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where "sccl-id" is the identifier of the SCCL and "index-id" is the index of
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module.
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e.g. hisi_sccl3_l3c0/rd_hit_cpipe is READ_HIT_CPIPE event of L3C index #0 in
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SCCL ID #3.
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e.g. hisi_sccl1_hha0/rx_operations is RX_OPERATIONS event of HHA index #0 in
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SCCL ID #1.
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The driver also provides a "cpumask" sysfs attribute, which shows the CPU core
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ID used to count the uncore PMU event. An "associated_cpus" sysfs attribute is
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also provided to show the CPUs associated with this PMU. The "cpumask" indicates
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the CPUs to open the events, usually as a hint for userspaces tools like perf.
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It only contains one associated CPU from the "associated_cpus".
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Example usage of perf::
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$# perf list
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hisi_sccl3_l3c0/rd_hit_cpipe/ [kernel PMU event]
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------------------------------------------
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hisi_sccl3_l3c0/wr_hit_cpipe/ [kernel PMU event]
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------------------------------------------
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hisi_sccl1_l3c0/rd_hit_cpipe/ [kernel PMU event]
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------------------------------------------
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hisi_sccl1_l3c0/wr_hit_cpipe/ [kernel PMU event]
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------------------------------------------
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$# perf stat -a -e hisi_sccl3_l3c0/rd_hit_cpipe/ sleep 5
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$# perf stat -a -e hisi_sccl3_l3c0/config=0x02/ sleep 5
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For HiSilicon uncore PMU v2 whose identifier is 0x30, the topology is the same
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as PMU v1, but some new functions are added to the hardware.
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1. L3C PMU supports filtering by core/thread within the cluster which can be
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specified as a bitmap::
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$# perf stat -a -e hisi_sccl3_l3c0/config=0x02,tt_core=0x3/ sleep 5
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This will only count the operations from core/thread 0 and 1 in this cluster.
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User should not use tt_core_deprecated to specify the core/thread filtering.
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This option is provided for backward compatiblility and only support 8bit
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which may not cover all the core/thread sharing L3C.
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2. Tracetag allow the user to chose to count only read, write or atomic
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operations via the tt_req parameeter in perf. The default value counts all
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operations. tt_req is 3bits, 3'b100 represents read operations, 3'b101
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represents write operations, 3'b110 represents atomic store operations and
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3'b111 represents atomic non-store operations, other values are reserved::
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$# perf stat -a -e hisi_sccl3_l3c0/config=0x02,tt_req=0x4/ sleep 5
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This will only count the read operations in this cluster.
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3. Datasrc allows the user to check where the data comes from. It is 5 bits.
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Some important codes are as follows:
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- 5'b00001: comes from L3C in this die;
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- 5'b01000: comes from L3C in the cross-die;
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- 5'b01001: comes from L3C which is in another socket;
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- 5'b01110: comes from the local DDR;
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- 5'b01111: comes from the cross-die DDR;
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- 5'b10000: comes from cross-socket DDR;
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etc, it is mainly helpful to find that the data source is nearest from the CPU
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cores. If datasrc_cfg is used in the multi-chips, the datasrc_skt shall be
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configured in perf command::
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$# perf stat -a -e hisi_sccl3_l3c0/config=0xb9,datasrc_cfg=0xE/,
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hisi_sccl3_l3c0/config=0xb9,datasrc_cfg=0xF/ sleep 5
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4. Some HiSilicon SoCs encapsulate multiple CPU and IO dies. Each CPU die
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contains several Compute Clusters (CCLs). The I/O dies are called Super I/O
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clusters (SICL) containing multiple I/O clusters (ICLs). Each CCL/ICL in the
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SoC has a unique ID. Each ID is 11bits, include a 6-bit SCCL-ID and 5-bit
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CCL/ICL-ID. For I/O die, the ICL-ID is followed by:
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- 5'b00000: I/O_MGMT_ICL;
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- 5'b00001: Network_ICL;
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- 5'b00011: HAC_ICL;
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- 5'b10000: PCIe_ICL;
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5. uring_channel: UC PMU events 0x47~0x59 supports filtering by tx request
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uring channel. It is 2 bits. Some important codes are as follows:
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- 2'b11: count the events which sent to the uring_ext (MATA) channel;
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- 2'b01: is the same as 2'b11;
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- 2'b10: count the events which sent to the uring (non-MATA) channel;
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- 2'b00: default value, count the events which sent to both uring and
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uring_ext channels;
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6. ch: NoC PMU supports filtering the event counts of certain transaction
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channel with this option. The current supported channels are as follows:
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- 3'b010: Request channel
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- 3'b100: Snoop channel
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- 3'b110: Response channel
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- 3'b111: Data channel
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7. tt_en: NoC PMU supports counting only transactions that have tracetag set
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if this option is set. See the 2nd list for more information about tracetag.
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For HiSilicon uncore PMU v3 whose identifier is 0x40, some uncore PMUs are
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further divided into parts for finer granularity of tracing, each part has its
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own dedicated PMU, and all such PMUs together cover the monitoring job of events
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on particular uncore device. Such PMUs are described in sysfs with name format
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slightly changed::
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/sys/bus/event_source/devices/hisi_sccl{X}_<l3c{Y}_{Z}/ddrc{Y}_{Z}/noc{Y}_{Z}>
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Z is the sub-id, indicating different PMUs for part of hardware device.
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Usage of most PMUs with different sub-ids are identical. Specially, L3C PMU
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provides ``ext`` option to allow exploration of even finer granual statistics
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of L3C PMU. L3C PMU driver uses that as hint of termination when delivering
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perf command to hardware:
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- ext=0: Default, could be used with event names.
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- ext=1 and ext=2: Must be used with event codes, event names are not supported.
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An example of perf command could be::
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$# perf stat -a -e hisi_sccl0_l3c1_0/rd_spipe/ sleep 5
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or::
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$# perf stat -a -e hisi_sccl0_l3c1_0/event=0x1,ext=1/ sleep 5
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As above, ``hisi_sccl0_l3c1_0`` locates PMU of Super CPU CLuster 0, L3 cache 1
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pipe0.
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First command locates the first part of L3C since ``ext=0`` is implied by
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default. Second command issues the counting on another part of L3C with the
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event ``0x1``.
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Users could configure IDs to count data come from specific CCL/ICL, by setting
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srcid_cmd & srcid_msk, and data desitined for specific CCL/ICL by setting
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tgtid_cmd & tgtid_msk. A set bit in srcid_msk/tgtid_msk means the PMU will not
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check the bit when matching against the srcid_cmd/tgtid_cmd.
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If all of these options are disabled, it can works by the default value that
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doesn't distinguish the filter condition and ID information and will return
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the total counter values in the PMU counters.
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The current driver does not support sampling. So "perf record" is unsupported.
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Also attach to a task is unsupported as the events are all uncore.
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Note: Please contact the maintainer for a complete list of events supported for
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the PMU devices in the SoC and its information if needed.
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