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phy: qcom-qmp: pcs: Add v8.50 register offsets 

The new Glymur SoC bumps up the HW version of QMP phy to v8.50 for PCIE
g5x4. Add the new PCS offsets in a dedicated header file.

Signed-off-by: Prudhvi Yarlagadda <quic_pyarlaga@quicinc.com>
Signed-off-by: Wenbin Yao <wenbin.yao@oss.qualcomm.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Signed-off-by: Qiang Yu <qiang.yu@oss.qualcomm.com>
Link: https://patch.msgid.link/20251103-glymur-pcie-upstream-v6-2-18a5e0a538dc@oss.qualcomm.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
This commit is contained in:
Prudhvi Yarlagadda 2025-11-03 23:56:25 -08:00 committed by Vinod Koul
parent d877f881ce
commit bc2ba6e3fb
2 changed files with 15 additions and 0 deletions
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13
drivers/phy/qualcomm/phy-qcom-qmp-pcs-v8_50.h Normal file
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@ -0,0 +1,13 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
*/
#ifndef QCOM_PHY_QMP_PCS_V8_50_H_
#define QCOM_PHY_QMP_PCS_V8_50_H_
#define QPHY_V8_50_PCS_STATUS1 0x010
#define QPHY_V8_50_PCS_START_CONTROL 0x05c
#define QPHY_V8_50_PCS_POWER_DOWN_CONTROL 0x64
#endif

2
drivers/phy/qualcomm/phy-qcom-qmp.h
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@ -58,6 +58,8 @@
#include "phy-qcom-qmp-pcs-v8.h"
#include "phy-qcom-qmp-pcs-v8_50.h"
/* QPHY_SW_RESET bit */
#define SW_RESET BIT(0)
/* QPHY_POWER_DOWN_CONTROL */