clk: amlogic: use the common pclk definition
Replace marcros defining pclks with the common one, reducing code duplication. Link: https://lore.kernel.org/r/20250825-meson-clk-cleanup-24-v2-9-0f402f01e117@baylibre.com Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
This commit is contained in:
Jerome Brunet
parent
aaee6f3bce
commit
b7358d14f1
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@ -34,30 +34,19 @@
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#define AO_RTC_ALT_CLK_CNTL0 0x94
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#define AO_RTC_ALT_CLK_CNTL1 0x98
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#define AXG_AO_GATE(_name, _bit, _flags) \
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static struct clk_regmap axg_ao_##_name = { \
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.data = &(struct clk_regmap_gate_data) { \
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.offset = (AO_RTI_GEN_CNTL_REG0), \
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.bit_idx = (_bit), \
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}, \
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.hw.init = &(struct clk_init_data) { \
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.name = "axg_ao_" #_name, \
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.ops = &clk_regmap_gate_ops, \
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.parent_data = &(const struct clk_parent_data) { \
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.fw_name = "mpeg-clk", \
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}, \
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.num_parents = 1, \
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.flags = (_flags), \
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}, \
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}
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static const struct clk_parent_data axg_ao_pclk_parents = { .fw_name = "mpeg-clk" };
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AXG_AO_GATE(remote, 0, CLK_IGNORE_UNUSED);
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AXG_AO_GATE(i2c_master, 1, CLK_IGNORE_UNUSED);
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AXG_AO_GATE(i2c_slave, 2, CLK_IGNORE_UNUSED);
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AXG_AO_GATE(uart1, 3, CLK_IGNORE_UNUSED);
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AXG_AO_GATE(uart2, 5, CLK_IGNORE_UNUSED);
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AXG_AO_GATE(ir_blaster, 6, CLK_IGNORE_UNUSED);
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AXG_AO_GATE(saradc, 7, CLK_IGNORE_UNUSED);
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#define AXG_AO_GATE(_name, _bit, _flags) \
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MESON_PCLK(axg_ao_##_name, AO_RTI_GEN_CNTL_REG0, _bit, \
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&axg_ao_pclk_parents, _flags)
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static AXG_AO_GATE(remote, 0, CLK_IGNORE_UNUSED);
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static AXG_AO_GATE(i2c_master, 1, CLK_IGNORE_UNUSED);
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static AXG_AO_GATE(i2c_slave, 2, CLK_IGNORE_UNUSED);
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static AXG_AO_GATE(uart1, 3, CLK_IGNORE_UNUSED);
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static AXG_AO_GATE(uart2, 5, CLK_IGNORE_UNUSED);
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static AXG_AO_GATE(ir_blaster, 6, CLK_IGNORE_UNUSED);
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static AXG_AO_GATE(saradc, 7, CLK_IGNORE_UNUSED);
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static struct clk_regmap axg_ao_cts_oscin = {
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.data = &(struct clk_regmap_gate_data){
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@ -164,30 +164,13 @@ static struct clk_regmap c3_rtc_clk = {
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},
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};
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#define C3_PCLK(_name, _reg, _bit, _fw_name, _ops, _flags) \
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struct clk_regmap c3_##_name = { \
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.data = &(struct clk_regmap_gate_data){ \
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.offset = (_reg), \
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.bit_idx = (_bit), \
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}, \
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.hw.init = &(struct clk_init_data) { \
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.name = "c3_" #_name, \
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.ops = _ops, \
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.parent_data = &(const struct clk_parent_data) { \
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.fw_name = (_fw_name), \
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}, \
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.num_parents = 1, \
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.flags = (_flags), \
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}, \
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}
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static const struct clk_parent_data c3_sys_pclk_parents = { .fw_name = "sysclk" };
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#define C3_SYS_PCLK(_name, _reg, _bit, _flags) \
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C3_PCLK(_name, _reg, _bit, "sysclk", \
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&clk_regmap_gate_ops, _flags)
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#define C3_SYS_PCLK(_name, _reg, _bit, _flags) \
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MESON_PCLK(c3_##_name, _reg, _bit, &c3_sys_pclk_parents, _flags)
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#define C3_SYS_PCLK_RO(_name, _reg, _bit) \
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C3_PCLK(_name, _reg, _bit, "sysclk", \
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&clk_regmap_gate_ro_ops, 0)
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#define C3_SYS_PCLK_RO(_name, _reg, _bit) \
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MESON_PCLK_RO(c3_##_name, _reg, _bit, &c3_sys_pclk_parents, 0)
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static C3_SYS_PCLK(sys_reset_ctrl, SYS_CLK_EN0_REG0, 1, 0);
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static C3_SYS_PCLK(sys_pwr_ctrl, SYS_CLK_EN0_REG0, 3, 0);
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@ -290,9 +273,10 @@ static C3_SYS_PCLK(sys_vc9000e, SYS_CLK_EN0_REG2, 2, 0);
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static C3_SYS_PCLK(sys_pwm_mn, SYS_CLK_EN0_REG2, 3, 0);
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static C3_SYS_PCLK(sys_sd_emmc_b, SYS_CLK_EN0_REG2, 4, 0);
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#define C3_AXI_PCLK(_name, _reg, _bit, _flags) \
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C3_PCLK(_name, _reg, _bit, "axiclk", \
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&clk_regmap_gate_ops, _flags)
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static const struct clk_parent_data c3_axi_pclk_parents = { .fw_name = "axiclk" };
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#define C3_AXI_PCLK(_name, _reg, _bit, _flags) \
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MESON_PCLK(c3_##_name, _reg, _bit, &c3_axi_pclk_parents, _flags)
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/*
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* NOTE: axi_sys_nic provides the clock to the AXI bus of the system NIC. After
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@ -37,22 +37,10 @@
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#define AO_RTC_ALT_CLK_CNTL0 0x94
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#define AO_RTC_ALT_CLK_CNTL1 0x98
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#define G12A_AO_PCLK(_name, _reg, _bit, _flags) \
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static struct clk_regmap g12a_ao_##_name = { \
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.data = &(struct clk_regmap_gate_data) { \
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.offset = (_reg), \
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.bit_idx = (_bit), \
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}, \
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.hw.init = &(struct clk_init_data) { \
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.name = "g12a_ao_" #_name, \
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.ops = &clk_regmap_gate_ops, \
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.parent_data = &(const struct clk_parent_data) { \
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.fw_name = "mpeg-clk", \
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}, \
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.num_parents = 1, \
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.flags = (_flags), \
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}, \
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}
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static const struct clk_parent_data g12a_ao_pclk_parents = { .fw_name = "mpeg-clk" };
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#define G12A_AO_PCLK(_name, _reg, _bit, _flags) \
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MESON_PCLK(g12a_ao_##_name, _reg, _bit, &g12a_ao_pclk_parents, _flags)
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/*
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* NOTE: The gates below are marked with CLK_IGNORE_UNUSED for historic reasons
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@ -63,22 +51,22 @@ static struct clk_regmap g12a_ao_##_name = { \
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* - add a comment explaining why the use of CLK_IGNORE_UNUSED is desirable
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* for a particular clock.
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*/
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G12A_AO_PCLK(ahb, AO_CLK_GATE0, 0, CLK_IGNORE_UNUSED);
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G12A_AO_PCLK(ir_in, AO_CLK_GATE0, 1, CLK_IGNORE_UNUSED);
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G12A_AO_PCLK(i2c_m0, AO_CLK_GATE0, 2, CLK_IGNORE_UNUSED);
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G12A_AO_PCLK(i2c_s0, AO_CLK_GATE0, 3, CLK_IGNORE_UNUSED);
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G12A_AO_PCLK(uart, AO_CLK_GATE0, 4, CLK_IGNORE_UNUSED);
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G12A_AO_PCLK(prod_i2c, AO_CLK_GATE0, 5, CLK_IGNORE_UNUSED);
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G12A_AO_PCLK(uart2, AO_CLK_GATE0, 6, CLK_IGNORE_UNUSED);
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G12A_AO_PCLK(ir_out, AO_CLK_GATE0, 7, CLK_IGNORE_UNUSED);
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G12A_AO_PCLK(saradc, AO_CLK_GATE0, 8, CLK_IGNORE_UNUSED);
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static G12A_AO_PCLK(ahb, AO_CLK_GATE0, 0, CLK_IGNORE_UNUSED);
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static G12A_AO_PCLK(ir_in, AO_CLK_GATE0, 1, CLK_IGNORE_UNUSED);
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static G12A_AO_PCLK(i2c_m0, AO_CLK_GATE0, 2, CLK_IGNORE_UNUSED);
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static G12A_AO_PCLK(i2c_s0, AO_CLK_GATE0, 3, CLK_IGNORE_UNUSED);
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static G12A_AO_PCLK(uart, AO_CLK_GATE0, 4, CLK_IGNORE_UNUSED);
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static G12A_AO_PCLK(prod_i2c, AO_CLK_GATE0, 5, CLK_IGNORE_UNUSED);
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static G12A_AO_PCLK(uart2, AO_CLK_GATE0, 6, CLK_IGNORE_UNUSED);
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static G12A_AO_PCLK(ir_out, AO_CLK_GATE0, 7, CLK_IGNORE_UNUSED);
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static G12A_AO_PCLK(saradc, AO_CLK_GATE0, 8, CLK_IGNORE_UNUSED);
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G12A_AO_PCLK(mailbox, AO_CLK_GATE0_SP, 0, CLK_IGNORE_UNUSED);
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G12A_AO_PCLK(m3, AO_CLK_GATE0_SP, 1, CLK_IGNORE_UNUSED);
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G12A_AO_PCLK(ahb_sram, AO_CLK_GATE0_SP, 2, CLK_IGNORE_UNUSED);
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G12A_AO_PCLK(rti, AO_CLK_GATE0_SP, 3, CLK_IGNORE_UNUSED);
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G12A_AO_PCLK(m4_fclk, AO_CLK_GATE0_SP, 4, CLK_IGNORE_UNUSED);
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G12A_AO_PCLK(m4_hclk, AO_CLK_GATE0_SP, 5, CLK_IGNORE_UNUSED);
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static G12A_AO_PCLK(mailbox, AO_CLK_GATE0_SP, 0, CLK_IGNORE_UNUSED);
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static G12A_AO_PCLK(m3, AO_CLK_GATE0_SP, 1, CLK_IGNORE_UNUSED);
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static G12A_AO_PCLK(ahb_sram, AO_CLK_GATE0_SP, 2, CLK_IGNORE_UNUSED);
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static G12A_AO_PCLK(rti, AO_CLK_GATE0_SP, 3, CLK_IGNORE_UNUSED);
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static G12A_AO_PCLK(m4_fclk, AO_CLK_GATE0_SP, 4, CLK_IGNORE_UNUSED);
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static G12A_AO_PCLK(m4_hclk, AO_CLK_GATE0_SP, 5, CLK_IGNORE_UNUSED);
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static struct clk_regmap g12a_ao_cts_oscin = {
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.data = &(struct clk_regmap_gate_data){
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@ -23,29 +23,18 @@
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#define AO_RTC_ALT_CLK_CNTL0 0x94
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#define AO_RTC_ALT_CLK_CNTL1 0x98
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#define GXBB_AO_PCLK(_name, _bit, _flags) \
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static struct clk_regmap gxbb_ao_##_name = { \
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.data = &(struct clk_regmap_gate_data) { \
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.offset = AO_RTI_GEN_CNTL_REG0, \
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.bit_idx = (_bit), \
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}, \
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.hw.init = &(struct clk_init_data) { \
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.name = "gxbb_ao_" #_name, \
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.ops = &clk_regmap_gate_ops, \
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.parent_data = &(const struct clk_parent_data) { \
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.fw_name = "mpeg-clk", \
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}, \
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.num_parents = 1, \
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.flags = (_flags), \
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}, \
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}
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static const struct clk_parent_data gxbb_ao_pclk_parents = { .fw_name = "mpeg-clk" };
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GXBB_AO_PCLK(remote, 0, CLK_IGNORE_UNUSED);
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GXBB_AO_PCLK(i2c_master, 1, CLK_IGNORE_UNUSED);
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GXBB_AO_PCLK(i2c_slave, 2, CLK_IGNORE_UNUSED);
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GXBB_AO_PCLK(uart1, 3, CLK_IGNORE_UNUSED);
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GXBB_AO_PCLK(uart2, 5, CLK_IGNORE_UNUSED);
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GXBB_AO_PCLK(ir_blaster, 6, CLK_IGNORE_UNUSED);
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#define GXBB_AO_PCLK(_name, _bit, _flags) \
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MESON_PCLK(gxbb_ao_##_name, AO_RTI_GEN_CNTL_REG0, _bit, \
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&gxbb_ao_pclk_parents, _flags)
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static GXBB_AO_PCLK(remote, 0, CLK_IGNORE_UNUSED);
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static GXBB_AO_PCLK(i2c_master, 1, CLK_IGNORE_UNUSED);
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static GXBB_AO_PCLK(i2c_slave, 2, CLK_IGNORE_UNUSED);
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static GXBB_AO_PCLK(uart1, 3, CLK_IGNORE_UNUSED);
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static GXBB_AO_PCLK(uart2, 5, CLK_IGNORE_UNUSED);
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static GXBB_AO_PCLK(ir_blaster, 6, CLK_IGNORE_UNUSED);
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static struct clk_regmap gxbb_ao_cts_oscin = {
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.data = &(struct clk_regmap_gate_data){
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