Updates for the interrupt subsystem:

- Ensure ordering of memory and device I/O for IPIs on RISCV
 
    The RISCV interrupt controllers use writel_relaxed() for generating an
    IPI. That's a device I/O write which is not guaranteed to be ordered
    against preceding memory writes. As a consequence a IPI receiving CPU
    might not be able to observe the actual IPI data which is required to
    handle it. Switch to writel() which contains the necessary memory
    barriers to enforce ordering.
 
  - Fix up the fallout of the MSI conversion in the MVEVBU ICU driver.
 
    The conversion failed to handle the change of the data storage and kept
    the original code which uses the domain::host_data pointer
    unchanged. After the conversion domain::host_data points to the new
    msi_domain_info structure and not longer to the MVEBU specific MSI data,
    which is now stored in a member of msi_domain_info. This leads to
    malfunction of the transalate() callback.
 
  - Only handle the PMC in FIQ mode when it is configured that way.
 
    The original check was incorrect as it did not explicitely check for the
    proper conditions, which led to malfunctions of the PMU interrupt.
 
  - Improve Kconfig dependencies for the LAN966x Outband Interrupt
    controller to avoid pointless pronmpts.
 -----BEGIN PGP SIGNATURE-----
 
 iQJHBAABCgAxFiEEQp8+kY+LLUocC4bMphj1TA10mKEFAmegvYoTHHRnbHhAbGlu
 dXRyb25peC5kZQAKCRCmGPVMDXSYoRsWEAC+CdtNpmlI56xnvAMCnmaUMiTHb5Be
 AFHb6yxmzUdQ53HOx5YhYuLfJojbn/0/upmE/2O3r9c0ku1GCPoNe8oEKCtf0Rai
 H65JVZMB9aEpnoQxO6wPCx5CUJILSNpEoyh9YwYa+xcdHXYsXot1PhS2UUj2OHkB
 yPv+Nt1rbJ6EHqV1bdti1yQ/Kig5WoQijEaYWHM4p1ZLlgQq628MXsvc6xYRbdeI
 d0Zf5HS3nTNxSXCe7KVs8VQWfgQyT2hrTFwIYb2b758pagM5pjTu6oxo6Wm2gHsL
 HHNkk3yZ5CvSzxbboQhPWlwYgtOd5wqAMuxeQGB4/ouZcUkJBvoTqDFC+T+ZCEpX
 faUW/vOve7UjSy7XNyqDyRKyLvwHw9xdX+fCdiY46dNqecnsz36IBD6xYkuKF8wK
 0Wy075/Zxq5uJ/7Q5cgobCPm7VzdRI5lbU0qBUnNNKlkce7pgKaUlRW0qfXPrnmi
 ZbzNZsUJFexFOx4bCvfioaJHDi1jmy+rq+kCoh2i3G8eK9RD2LsUdO4HR4QAWb6w
 nkBmNG10jdjO4UUQsA3kN8eyEvMVxpgZ/sP9jSY5W1p0jlWF28OZcTm4LZUqgUaD
 dG/jjC98qapEwSof67PLWjB5qXkL5ABDXiiMxYWkG287X4ayWT0lvwzoQ22q+3Ep
 Dr4uOTXuZ8j1VA==
 =9x00
 -----END PGP SIGNATURE-----

Merge tag 'irq-urgent-2025-02-03' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip

Pull irq fixes from Thomas Gleixner:

 - Ensure ordering of memory and device I/O for IPIs on RISCV

   The RISCV interrupt controllers use writel_relaxed() for generating
   an IPI. That's a device I/O write which is not guaranteed to be
   ordered against preceding memory writes. As a consequence a IPI
   receiving CPU might not be able to observe the actual IPI data which
   is required to handle it. Switch to writel() which contains the
   necessary memory barriers to enforce ordering.

 - Fix up the fallout of the MSI conversion in the MVEVBU ICU driver.

   The conversion failed to handle the change of the data storage and
   kept the original code which uses the domain::host_data pointer
   unchanged. After the conversion domain::host_data points to the new
   msi_domain_info structure and not longer to the MVEBU specific MSI
   data, which is now stored in a member of msi_domain_info. This leads
   to malfunction of the transalate() callback.

 - Only handle the PMC in FIQ mode when it is configured that way.

   The original check was incorrect as it did not explicitely check for
   the proper conditions, which led to malfunctions of the PMU
   interrupt.

 - Improve Kconfig dependencies for the LAN966x Outband Interrupt
   controller to avoid pointless pronmpts.

* tag 'irq-urgent-2025-02-03' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
  irqchip/apple-aic: Only handle PMC interrupt as FIQ when configured so
  irqchip/irq-mvebu-icu: Fix access to msi_data from irq_domain::host_data
  irqchip/riscv: Ensure ordering of memory writes and IPI writes
  irqchip/lan966x-oic: Make CONFIG_LAN966X_OIC depend on CONFIG_MCHP_LAN966X_PCI
  dt-bindings: interrupt-controller: microchip,lan966x-oic: Clarify endpoint use

Documentation/devicetree/bindings/interrupt-controller/microchip,lan966x-oic.yaml

@@ -14,9 +14,8 @@ allOf:
 
 description: |
   The Microchip LAN966x outband interrupt controller (OIC) maps the internal
-  interrupt sources of the LAN966x device to an external interrupt.
-  When the LAN966x device is used as a PCI device, the external interrupt is
-  routed to the PCI interrupt.
+  interrupt sources of the LAN966x device to a PCI interrupt when the LAN966x
+  device is used as a PCI device.
 
 properties:
   compatible:

drivers/irqchip/Kconfig

@@ -169,6 +169,7 @@ config IXP4XX_IRQ
 
 config LAN966X_OIC
 	tristate "Microchip LAN966x OIC Support"
+	depends on MCHP_LAN966X_PCI || COMPILE_TEST
 	select GENERIC_IRQ_CHIP
 	select IRQ_DOMAIN
 	help

drivers/irqchip/irq-apple-aic.c

@@ -577,7 +577,8 @@ static void __exception_irq_entry aic_handle_fiq(struct pt_regs *regs)
 						  AIC_FIQ_HWIRQ(AIC_TMR_EL02_VIRT));
 	}
 
-	if (read_sysreg_s(SYS_IMP_APL_PMCR0_EL1) & PMCR0_IACT) {
+	if ((read_sysreg_s(SYS_IMP_APL_PMCR0_EL1) & (PMCR0_IMODE | PMCR0_IACT)) ==
+			(FIELD_PREP(PMCR0_IMODE, PMCR0_IMODE_FIQ) | PMCR0_IACT)) {
 		int irq;
 		if (cpumask_test_cpu(smp_processor_id(),
 				     &aic_irqc->fiq_aff[AIC_CPU_PMU_P]->aff))

drivers/irqchip/irq-mvebu-icu.c

@@ -68,7 +68,8 @@ static int mvebu_icu_translate(struct irq_domain *d, struct irq_fwspec *fwspec,
 			       unsigned long *hwirq, unsigned int *type)
 {
 	unsigned int param_count = static_branch_unlikely(&legacy_bindings) ? 3 : 2;
-	struct mvebu_icu_msi_data *msi_data = d->host_data;
+	struct msi_domain_info *info = d->host_data;
+	struct mvebu_icu_msi_data *msi_data = info->chip_data;
 	struct mvebu_icu *icu = msi_data->icu;
 
 	/* Check the count of the parameters in dt */

drivers/irqchip/irq-riscv-imsic-early.c

@@ -27,7 +27,7 @@ static void imsic_ipi_send(unsigned int cpu)
 {
 	struct imsic_local_config *local = per_cpu_ptr(imsic->global.local, cpu);
 
-	writel_relaxed(IMSIC_IPI_ID, local->msi_va);
+	writel(IMSIC_IPI_ID, local->msi_va);
 }
 
 static void imsic_ipi_starting_cpu(void)

drivers/irqchip/irq-thead-c900-aclint-sswi.c

@@ -31,7 +31,7 @@ static DEFINE_PER_CPU(void __iomem *, sswi_cpu_regs);
 
 static void thead_aclint_sswi_ipi_send(unsigned int cpu)
 {
-	writel_relaxed(0x1, per_cpu(sswi_cpu_regs, cpu));
+	writel(0x1, per_cpu(sswi_cpu_regs, cpu));
 }
 
 static void thead_aclint_sswi_ipi_clear(void)