Adhemerval Zanella 7fec8a5de6 Revert __HAVE_64B_ATOMICS configure check ... The 53807741fb added a configure check for 64-bit atomic operations that were not previously enabled on some 32-bit ABIs. However, the NPTL semaphore code casts a sem_t to a new_sem and issues a 64-bit atomic operation for __HAVE_64B_ATOMICS. Since sem_t has 32-bit alignment on 32-bit architectures, this prevents the use of 64-bit atomics even if the ABI supports them. Assume 64-bit atomic support from __WORDSIZE, which maps to how glibc defines it before the broken change. Also rename __HAVE_64B_ATOMICS to USE_64B_ATOMICS to define better the flag meaning. Checked on x86_64-linux-gnu and i686-linux-gnu. Reviewed-by: Wilco Dijkstra <Wilco.Dijkstra@arm.com>		2025-11-14 14:05:20 -03:00
..
bits	…
multiarch	riscv: memcpy_noalignment: Reorder to store via a3, then bump a3	2025-10-30 17:49:21 -05:00
nofpu	…
nptl	…
rv32	…
rv64	…
rvd	…
rvf	…
sys	…
Implies	…
Makefile	…
__longjmp.S	…
atomic-machine.h	Revert __HAVE_64B_ATOMICS configure check	2025-11-14 14:05:20 -03:00
bsd-_setjmp.c	…
bsd-setjmp.c	…
configure	…
configure.ac	…
dl-irel.h	…
dl-link.sym	…
dl-machine.h	…
dl-relocate-ld.h	…
dl-tls.h	…
dl-trampoline.S	…
e_sqrtl.c	…
fpu_control.h	Fix RISC-V soft-float _FPU_SETCW for GCC 16 set-but-not-used warnings	2025-09-13 07:11:44 -07:00
gccframe.h	…
jmpbuf-offsets.h	…
jmpbuf-unwind.h	…
ldsodefs.h	…
libc-tls.c	…
linkmap.h	…
machine-gmon.h	…
math-tests-snan-payload.h	…
math-tests-trap.h	…
math-use-builtins-ffs.h	…
preconfigure	riscv: Add vector registers to __SYSCALL_CLOBBERS	2025-11-04 09:18:56 -06:00
preconfigure.ac	riscv: Add vector registers to __SYSCALL_CLOBBERS	2025-11-04 09:18:56 -06:00
riscv-ifunc.h	…
setjmp.S	…
sfp-machine.h	…
sotruss-lib.c	…
start.S	…
string-fza.h	…
string-fzi.h	…
string-misc.h	riscv: Add Zbkb optimized repeat_bytes helper	2025-10-31 16:23:57 -05:00
thread_pointer.h	…
tininess.h	…
tst-audit.h	…
utmp-size.h	…