15 Commits
Author SHA1 Message Date
Pierre Blanchard 2cce7ec3c8 AArch64: additional mathvec build system cleanups.
Rely on a single list of ISAs and precisions for
source, tests and benchmarks.

Reviewed-by: Adhemerval Zanella  <adhemerval.zanella@linaro.org>
2026-06-23 14:50:30 -03:00
Pierre Blanchard c5a4d7ccb2 AArch64: Update SHARED-FILES with files from Arm Optimized-Routines
Adds lists for math.h and string.h and track file revisions.

Reviewed-by: Adhemerval Zanella  <adhemerval.zanella@linaro.org>
2026-06-23 14:50:30 -03:00
Pierre Blanchard 5a60281b88 AArch64: Update mathvec directory structure.
The new structure matches that of Arm Optimized-routines,
to facilitate files traceability.

Reviewed-by: Adhemerval Zanella  <adhemerval.zanella@linaro.org>
2026-06-23 14:50:30 -03:00
Pierre Blanchard 2ff2565df7 AArch64: Implement AdvSIMD and SVE powr(f) routines
Vector variants of the new C23 powr routines.

These provide same maximum error error as pow by virtue of
relying on shared approximation techniques and sources.

Note: Benchmark inputs for powr(f) are identical to pow(f).

Performance gain over pow on V1 with GCC@15:
- SVE powr: 10-12% on subnormal x, 12-13% on x < 0.
- SVE powrf: 15% on all x < 0.
- AdvSIMD powr: for x < 0, 40% if x subnormal, 60% otherwise.
- AdvSIMD powrf: 4% on x subnormals or x < 0.
2026-04-20 13:01:25 -03:00
Pierre Blanchard 4794e84a2f benchtests: add libmvec powr inputs
They are identical to the libmvec pow ones.
2026-04-20 13:01:25 -03:00
Pierre Blanchard 51c4069206 benchtests: add libmvec powrf inputs
They are identical to the libmvec powf ones.
2026-04-20 13:01:25 -03:00
Pierre Blanchard 3f97be129d AArch64: Improve AdvSIMD and SVE pow(f).
Optimize handling of subnormal x and/or negative x.

Some cleanup in attributes, macros and improving overall consistency.

Move core computation to header
Introduce config parameter to turn sign_bias on/off.

Performance improvement on V1 with GCC@15:
- AdvSIMD pow: 10-15% on subnormals.
- AdvSIMD powf: 30 to 70% on subnormals or x < 0, <=3% on x > 0.
- SVE pow: 10-15% on subnormals, <=3% otherwise.
- SVE powf: no significant variations in codegen/perf.
2026-04-20 13:01:25 -03:00
Pierre Blanchard bb6519de1e AArch64: Fix and improve SVE pow(f) special cases
powf:

Update scalar special case function to best use new interface.

pow:

Make specialcase NOINLINE to prevent str/ldr leaking in fast path.
Remove depency in sv_call2, as new callback impl is not a
performance gain.
Replace with vectorised specialcase since structure of scalar
routine is fairly simple.

Throughput gain of about 5-10% on V1 for large values and 25% for subnormal `x`.

Reviewed-by: Wilco Dijkstra  <Wilco.Dijkstra@arm.com>
2025-11-18 15:51:15 +00:00
Pierre Blanchard e889160273 AArch64: fix SVE tanpi(f) [BZ #33642]
Fixed svld1rq using incorrect predicates (BZ #33642).
Next to no performance variations (tested on V1).

Reviewed-by: Wilco Dijkstra  <Wilco.Dijkstra@arm.com>
2025-11-18 15:51:15 +00:00
Pierre Blanchard aac077645a AArch64: Fix SVE powf routine [BZ #33299]
Fix a bug in predicate logic introduced in last change.
A slight performance improvement from relying on all true
predicates during conversion from single to double.
This fixes BZ #33299.

Reviewed-by: Wilco Dijkstra  <Wilco.Dijkstra@arm.com>
2025-08-20 17:45:21 +00:00
Pierre Blanchard cf56eb28fa AArch64: Optimize algorithm in users of SVE expf helper
Polynomial order was unnecessarily high, unlocking multiple
optimizations.
Max error for new SVE expf is 0.88 +0.5ULP.
Max error for new SVE coshf is 2.56 +0.5ULP.
Performance improvement on Neoverse V1: expf (30%), coshf (26%).

Reviewed-by: Wilco Dijkstra  <Wilco.Dijkstra@arm.com>
2025-03-18 17:15:18 +00:00
Pierre Blanchard 13a7ef5999 AArch64: Improve codegen in users of ADVSIMD expm1 helper
Add inline helper for expm1 and rearrange operations so MOV
is not necessary in reduction or around the special-case handler.
Reduce memory access by using more indexed MLAs in polynomial.
Speedup on Neoverse V1 for expm1 (19%), sinh (8.5%), and tanh (7.5%).
2024-12-09 16:20:34 +00:00
Pierre Blanchard ca0c0d0f26 AArch64: Improve codegen in users of ADVSIMD log1p helper
Add inline helper for log1p and rearrange operations so MOV
is not necessary in reduction or around the special-case handler.
Reduce memory access by using more indexed MLAs in polynomial.
Speedup on Neoverse V1 for log1p (3.5%), acosh (7.5%) and atanh (10%).
2024-12-09 16:20:34 +00:00
Pierre Blanchard 8eb5ad2ebc AArch64: Improve codegen in AdvSIMD logs
Remove spurious ADRP and a few MOVs.
Reduce memory access by using more indexed MLAs in polynomial.
Align notation so that algorithms are easier to compare.
Speedup on Neoverse V1 for log10 (8%), log (8.5%), and log2 (10%).
Update error threshold in AdvSIMD log (now matches SVE log).
2024-12-09 16:20:34 +00:00
Pierre Blanchard 569cfaaf49 AArch64: Improve codegen in AdvSIMD pow
Remove spurious ADRP. Improve memory access by shuffling constants and
using more indexed MLAs.

A few more optimisation with no impact on accuracy
- force fmas contraction
- switch from shift-aided rint to rint instruction

Between 1 and 5% throughput improvement on Neoverse
V1 depending on benchmark.
2024-12-09 16:20:34 +00:00