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* sysdeps/unix/sysv/linux/powerpc/powerpc32/getcontext.S: Fix pasto 

that clobbers r19.  Fix pasto that overflowed sigcontext.v_reserve.
	* sysdeps/unix/sysv/linux/powerpc/powerpc32/setcontext.S: Fix pasto
	that clobbers r19.
	* sysdeps/unix/sysv/linux/powerpc/powerpc32/swapcontext.S: Fix pasto
	that clobbers r19.  Fix pasto that overflowed sigcontext.v_reserve.
	* sysdeps/unix/sysv/linux/powerpc/powerpc64/getcontext.S:
	Fix setting of sigcontext.v_regs.  Fix pasto that clobbers r19.
	Fix pasto that overflowed sigcontext.v_reserve.
	* sysdeps/unix/sysv/linux/powerpc/powerpc64/setcontext.S:
	Fix pasto that clobbers r19.
	* sysdeps/unix/sysv/linux/powerpc/powerpc64/swapcontext.S: Fix setting
	of sigcontext.v_regs.  Fix pasto that clobbers r19.  Fix pasto that
	overflowed sigcontext.v_reserve.
This commit is contained in:
Roland McGrath 2004-06-15 20:02:33 +00:00
parent 77526fd238
commit e1ad4c533a
7 changed files with 48 additions and 48 deletions
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17
ChangeLog
View File

@ -1,3 +1,20 @@
2004-06-15 Steven Munroe <sjmunroe@us.ibm.com>
* sysdeps/unix/sysv/linux/powerpc/powerpc32/getcontext.S: Fix pasto
that clobbers r19. Fix pasto that overflowed sigcontext.v_reserve.
* sysdeps/unix/sysv/linux/powerpc/powerpc32/setcontext.S: Fix pasto
that clobbers r19.
* sysdeps/unix/sysv/linux/powerpc/powerpc32/swapcontext.S: Fix pasto
that clobbers r19. Fix pasto that overflowed sigcontext.v_reserve.
* sysdeps/unix/sysv/linux/powerpc/powerpc64/getcontext.S:
Fix setting of sigcontext.v_regs. Fix pasto that clobbers r19.
Fix pasto that overflowed sigcontext.v_reserve.
* sysdeps/unix/sysv/linux/powerpc/powerpc64/setcontext.S:
Fix pasto that clobbers r19.
* sysdeps/unix/sysv/linux/powerpc/powerpc64/swapcontext.S: Fix setting
of sigcontext.v_regs. Fix pasto that clobbers r19. Fix pasto that
overflowed sigcontext.v_reserve.
2004-05-04 H.J. Lu <hongjiu.lu@intel.com> 2004-05-04 H.J. Lu <hongjiu.lu@intel.com>
[BZ #150] [BZ #150]

9
sysdeps/unix/sysv/linux/powerpc/powerpc32/getcontext.S
View File

@ -187,8 +187,8 @@ ENTRY(__getcontext)
addi r9,r9,32 addi r9,r9,32
stvx v18,0,r10 stvx v18,0,r10
stvx v11,0,r9 stvx v19,0,r9
addi r19,r10,32 addi r10,r10,32
addi r9,r9,32 addi r9,r9,32
stvx v20,0,r10 stvx v20,0,r10
@ -221,11 +221,6 @@ ENTRY(__getcontext)
addi r10,r10,32 addi r10,r10,32
addi r9,r9,32 addi r9,r9,32
stvx v10,0,r10
stvx v11,0,r9
addi r10,r10,32
addi r9,r9,32
mfvscr v0 mfvscr v0
mfspr r0,VRSAVE mfspr r0,VRSAVE
stvx v0,0,r10 stvx v0,0,r10

4
sysdeps/unix/sysv/linux/powerpc/powerpc32/setcontext.S
View File

@ -133,8 +133,8 @@ ENTRY(__setcontext)
addi r9,r9,32 addi r9,r9,32
lvx v18,0,r10 lvx v18,0,r10
lvx v11,0,r9 lvx v19,0,r9
addi r19,r10,32 addi r10,r10,32
addi r9,r9,32 addi r9,r9,32
lvx v20,0,r10 lvx v20,0,r10

13
sysdeps/unix/sysv/linux/powerpc/powerpc32/swapcontext.S
View File

@ -189,8 +189,8 @@ ENTRY(__swapcontext)
addi r9,r9,32 addi r9,r9,32
stvx v18,0,r10 stvx v18,0,r10
stvx v11,0,r9 stvx v19,0,r9
addi r19,r10,32 addi r10,r10,32
addi r9,r9,32 addi r9,r9,32
stvx v20,0,r10 stvx v20,0,r10
@ -223,11 +223,6 @@ ENTRY(__swapcontext)
addi r10,r10,32 addi r10,r10,32
addi r9,r9,32 addi r9,r9,32
stvx v10,0,r10
stvx v11,0,r9
addi r10,r10,32
addi r9,r9,32
mfvscr v0 mfvscr v0
mfspr r0,VRSAVE mfspr r0,VRSAVE
stvx v0,0,r10 stvx v0,0,r10
@ -339,8 +334,8 @@ L(no_vec):
addi r9,r9,32 addi r9,r9,32
lvx v18,0,r10 lvx v18,0,r10
lvx v11,0,r9 lvx v19,0,r9
addi r19,r10,32 addi r10,r10,32
addi r9,r9,32 addi r9,r9,32
lvx v20,0,r10 lvx v20,0,r10

24
sysdeps/unix/sysv/linux/powerpc/powerpc64/getcontext.S
View File

@ -268,21 +268,22 @@ ENTRY(__getcontext)
stfd fp0,(SIGCONTEXT_FP_REGS+(32*8))(r3) stfd fp0,(SIGCONTEXT_FP_REGS+(32*8))(r3)
ld r5,.LC__dl_hwcap@toc(r2) ld r5,.LC__dl_hwcap@toc(r2)
li r10,0
# ifdef SHARED # ifdef SHARED
/* Load _rtld-global._dl_hwcap. */ /* Load _rtld-global._dl_hwcap. */
ld r5,RTLD_GLOBAL_RO_DL_HWCAP_OFFSET(r5) ld r5,RTLD_GLOBAL_RO_DL_HWCAP_OFFSET(r5)
# else # else
ld r5,0(r5) /* Load extern _dl_hwcap. */ ld r5,0(r5) /* Load extern _dl_hwcap. */
# endif # endif
andis. r5,r5,(PPC_FEATURE_HAS_ALTIVEC >> 16)
beq L(has_no_vec)
la r10,(SIGCONTEXT_V_RESERVE+8)(r3) la r10,(SIGCONTEXT_V_RESERVE+8)(r3)
la r9,(SIGCONTEXT_V_RESERVE+24)(r3) la r9,(SIGCONTEXT_V_RESERVE+24)(r3)
andis. r5,r5,(PPC_FEATURE_HAS_ALTIVEC >> 16)
clrrdi r10,r10,4 clrrdi r10,r10,4
beq L(has_no_vec)
clrrdi r9,r9,4 clrrdi r9,r9,4
mr r5,r10 /* Capture *v_regs value in r5. */
stvx v0,0,r10 stvx v0,0,r10
stvx v1,0,r9 stvx v1,0,r9
addi r10,r10,32 addi r10,r10,32
@ -329,8 +330,8 @@ ENTRY(__getcontext)
addi r9,r9,32 addi r9,r9,32
stvx v18,0,r10 stvx v18,0,r10
stvx v11,0,r9 stvx v19,0,r9
addi r19,r10,32 addi r10,r10,32
addi r9,r9,32 addi r9,r9,32
stvx v20,0,r10 stvx v20,0,r10
@ -363,11 +364,6 @@ ENTRY(__getcontext)
addi r10,r10,32 addi r10,r10,32
addi r9,r9,32 addi r9,r9,32
stvx v10,0,r10
stvx v11,0,r9
addi r10,r10,32
addi r9,r9,32
mfvscr v0 mfvscr v0
mfspr r0,VRSAVE mfspr r0,VRSAVE
stvx v0,0,r10 stvx v0,0,r10
@ -378,7 +374,7 @@ L(has_no_vec):
Store either a NULL or a quadword aligned pointer to the Vector register Store either a NULL or a quadword aligned pointer to the Vector register
array into *v_regs. array into *v_regs.
*/ */
std r10,(SIGCONTEXT_V_REGS_PTR)(r3) std r5,(SIGCONTEXT_V_REGS_PTR)(r3)
addi r5,r3,UCONTEXT_SIGMASK addi r5,r3,UCONTEXT_SIGMASK
li r4,0 li r4,0

4
sysdeps/unix/sysv/linux/powerpc/powerpc64/setcontext.S
View File

@ -293,8 +293,8 @@ ENTRY(__setcontext)
addi r9,r9,32 addi r9,r9,32
lvx v18,0,r10 lvx v18,0,r10
lvx v11,0,r9 lvx v19,0,r9
addi r19,r10,32 addi r10,r10,32
addi r9,r9,32 addi r9,r9,32
lvx v20,0,r10 lvx v20,0,r10

25
sysdeps/unix/sysv/linux/powerpc/powerpc64/swapcontext.S
View File

@ -391,20 +391,22 @@ ENTRY(__swapcontext)
stfd fp0,(SIGCONTEXT_FP_REGS+(32*8))(r3) stfd fp0,(SIGCONTEXT_FP_REGS+(32*8))(r3)
ld r8,.LC__dl_hwcap@toc(r2) ld r8,.LC__dl_hwcap@toc(r2)
li r10,0
#ifdef SHARED #ifdef SHARED
/* Load _rtld-global._dl_hwcap. */ /* Load _rtld-global._dl_hwcap. */
ld r8,RTLD_GLOBAL_RO_DL_HWCAP_OFFSET(r8) ld r8,RTLD_GLOBAL_RO_DL_HWCAP_OFFSET(r8)
#else #else
ld r8,0(r8) /* Load extern _dl_hwcap. */ ld r8,0(r8) /* Load extern _dl_hwcap. */
#endif #endif
andis. r8,r8,(PPC_FEATURE_HAS_ALTIVEC >> 16)
beq L(has_no_vec)
la r10,(SIGCONTEXT_V_RESERVE+8)(r3) la r10,(SIGCONTEXT_V_RESERVE+8)(r3)
la r9,(SIGCONTEXT_V_RESERVE+24)(r3) la r9,(SIGCONTEXT_V_RESERVE+24)(r3)
andis. r8,r8,(PPC_FEATURE_HAS_ALTIVEC >> 16)
clrrdi r10,r10,4 clrrdi r10,r10,4
beq L(has_no_vec)
clrrdi r9,r9,4 clrrdi r9,r9,4
mr r8,r10 /* Capture *v_regs value in r5. */
stvx v0,0,r10 stvx v0,0,r10
stvx v1,0,r9 stvx v1,0,r9
@ -452,8 +454,8 @@ ENTRY(__swapcontext)
addi r9,r9,32 addi r9,r9,32
stvx v18,0,r10 stvx v18,0,r10
stvx v11,0,r9 stvx v19,0,r9
addi r19,r10,32 addi r10,r10,32
addi r9,r9,32 addi r9,r9,32
stvx v20,0,r10 stvx v20,0,r10
@ -486,11 +488,6 @@ ENTRY(__swapcontext)
addi r10,r10,32 addi r10,r10,32
addi r9,r9,32 addi r9,r9,32
stvx v10,0,r10
stvx v11,0,r9
addi r10,r10,32
addi r9,r9,32
mfvscr v0 mfvscr v0
mfspr r0,VRSAVE mfspr r0,VRSAVE
stvx v0,0,r10 stvx v0,0,r10
@ -501,7 +498,7 @@ L(has_no_vec):
Store either a NULL or a quadword aligned pointer to the Vector register Store either a NULL or a quadword aligned pointer to the Vector register
array into *v_regs. array into *v_regs.
*/ */
std r10,(SIGCONTEXT_V_REGS_PTR)(r3) std r8,(SIGCONTEXT_V_REGS_PTR)(r3)
mr r31,r4 mr r31,r4
addi r5,r3,UCONTEXT_SIGMASK addi r5,r3,UCONTEXT_SIGMASK
@ -596,8 +593,8 @@ L(has_no_vec):
addi r9,r9,32 addi r9,r9,32
lvx v18,0,r10 lvx v18,0,r10
lvx v11,0,r9 lvx v19,0,r9
addi r19,r10,32 addi r10,r10,32
addi r9,r9,32 addi r9,r9,32
lvx v20,0,r10 lvx v20,0,r10