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Document cache information sysconf variables 

Write short descriptions for each of the cache information sysconf
variables.

	* manual/conf.texi (_SC_LEVEL1_ICACHE_SIZE,
	_SC_LEVEL1_ICACHE_ASSOC, _SC_LEVEL1_ICACHE_LINESIZE,
	_SC_LEVEL1_DCACHE_SIZE, _SC_LEVEL1_DCACHE_ASSOC,
	_SC_LEVEL1_DCACHE_LINESIZE, _SC_LEVEL2_CACHE_SIZE,
	_SC_LEVEL2_CACHE_ASSOC, _SC_LEVEL2_CACHE_LINESIZE,
	_SC_LEVEL3_CACHE_SIZE, _SC_LEVEL3_CACHE_ASSOC,
	_SC_LEVEL3_CACHE_LINESIZE, _SC_LEVEL4_CACHE_SIZE,
	_SC_LEVEL4_CACHE_ASSOC, _SC_LEVEL4_CACHE_LINESIZE): New
	variables.

Reviewed-by: Rical Jasan <ricaljasan@pacific.net>
This commit is contained in:
Siddhesh Poyarekar 2017-10-23 20:19:34 +05:30
parent be080b6c14
commit db9bab09a5
2 changed files with 73 additions and 0 deletions
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12
ChangeLog
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@ -1,3 +1,15 @@
2017-10-23 Siddhesh Poyarekar <siddhesh@sourceware.org>
* manual/conf.texi (_SC_LEVEL1_ICACHE_SIZE,
_SC_LEVEL1_ICACHE_ASSOC, _SC_LEVEL1_ICACHE_LINESIZE,
_SC_LEVEL1_DCACHE_SIZE, _SC_LEVEL1_DCACHE_ASSOC,
_SC_LEVEL1_DCACHE_LINESIZE, _SC_LEVEL2_CACHE_SIZE,
_SC_LEVEL2_CACHE_ASSOC, _SC_LEVEL2_CACHE_LINESIZE,
_SC_LEVEL3_CACHE_SIZE, _SC_LEVEL3_CACHE_ASSOC,
_SC_LEVEL3_CACHE_LINESIZE, _SC_LEVEL4_CACHE_SIZE,
_SC_LEVEL4_CACHE_ASSOC, _SC_LEVEL4_CACHE_LINESIZE): New
variables.
2017-10-23 Michael Collison <michael.collison@arm.com> 2017-10-23 Michael Collison <michael.collison@arm.com>
* sysdeps/aarch64/fpu/e_sqrt.c (ieee754_sqrt): Replace asm statements * sysdeps/aarch64/fpu/e_sqrt.c (ieee754_sqrt): Replace asm statements

61
manual/conf.texi
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@ -678,6 +678,67 @@ Inquire about the number of available physical pages in the system.
Inquire about the number of functions which can be registered as termination Inquire about the number of functions which can be registered as termination
functions for @code{atexit}; @pxref{Cleanups on Exit}. functions for @code{atexit}; @pxref{Cleanups on Exit}.
@item _SC_LEVEL1_ICACHE_SIZE
@standards{GNU, unistd.h}
Inquire about the size of the Level 1 instruction cache.
@item _SC_LEVEL1_ICACHE_ASSOC
@standards{GNU, unistd.h}
Inquire about the associativity of the Level 1 instruction cache.
@item _SC_LEVEL1_ICACHE_LINESIZE
@standards{GNU, unistd.h}
Inquire about the line length of the Level 1 instruction cache.
@item _SC_LEVEL1_DCACHE_SIZE
@standards{GNU, unistd.h}
Inquire about the size of the Level 1 data cache.
@item _SC_LEVEL1_DCACHE_ASSOC
@standards{GNU, unistd.h}
Inquire about the associativity of the Level 1 data cache.
@item _SC_LEVEL1_DCACHE_LINESIZE
@standards{GNU, unistd.h}
Inquire about the line length of the Level 1 data cache.
@item _SC_LEVEL2_CACHE_SIZE
@standards{GNU, unistd.h}
Inquire about the size of the Level 2 cache.
@item _SC_LEVEL2_CACHE_ASSOC
@standards{GNU, unistd.h}
Inquire about the associativity of the Level 2 cache.
@item _SC_LEVEL2_CACHE_LINESIZE
@standards{GNU, unistd.h}
Inquire about the line length of the Level 2 cache.
@item _SC_LEVEL3_CACHE_SIZE
@standards{GNU, unistd.h}
Inquire about the size of the Level 3 cache.
@item _SC_LEVEL3_CACHE_ASSOC
@standards{GNU, unistd.h}
Inquire about the associativity of the Level 3 cache.
@item _SC_LEVEL3_CACHE_LINESIZE
@standards{GNU, unistd.h}
Inquire about the line length of the Level 3 cache.
@item _SC_LEVEL4_CACHE_SIZE
@standards{GNU, unistd.h}
Inquire about the size of the Level 4 cache.
@item _SC_LEVEL4_CACHE_ASSOC
@standards{GNU, unistd.h}
Inquire about the associativity of the Level 4 cache.
@item _SC_LEVEL4_CACHE_LINESIZE
@standards{GNU, unistd.h}
Inquire about the line length of the Level 4 cache.
@item _SC_XOPEN_VERSION @item _SC_XOPEN_VERSION
@standards{X/Open, unistd.h} @standards{X/Open, unistd.h}
Inquire about the parameter corresponding to @code{_XOPEN_VERSION}. Inquire about the parameter corresponding to @code{_XOPEN_VERSION}.