mirror of git://sourceware.org/git/glibc.git
powerpc: Consolidate atomic-machine.h
The __HAVE_64B_ATOMICS can be define based on __WORDSIZE, and the __ARCH_ACQ_INSTR, MUTEX_HINT_*, and barriers definition are defined by the target cpu. Reviewed-by: Wilco Dijkstra <Wilco.Dijkstra@arm.com>
This commit is contained in:
Adhemerval Zanella
parent
9201eabed8
commit
d76e20791b
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@ -16,25 +16,47 @@
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License along with the GNU C Library; if not, see
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<https://www.gnu.org/licenses/>. */
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/*
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* Never include sysdeps/powerpc/atomic-machine.h directly.
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* Always use include/atomic.h which will include either
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* sysdeps/powerpc/powerpc32/atomic-machine.h
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* or
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* sysdeps/powerpc/powerpc64/atomic-machine.h
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* as appropriate and which in turn include this file.
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*/
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#ifndef _POWERPC_ATOMIC_MACHINE_H
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#define _POWERPC_ATOMIC_MACHINE_H 1
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#define __ARCH_ACQ_INSTR "isync"
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#ifndef __ARCH_REL_INSTR
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# define __ARCH_REL_INSTR "sync"
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#if __WORDSIZE == 64
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# define __HAVE_64B_ATOMICS 1
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#else
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# define __HAVE_64B_ATOMICS 0
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#endif
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#define ATOMIC_EXCHANGE_USES_CAS 1
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#ifndef MUTEX_HINT_ACQ
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/* Used on pthread_spin_{try}lock. */
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#define __ARCH_ACQ_INSTR "isync"
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#if defined _ARCH_PWR6 || defined _ARCH_PWR6X
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# define MUTEX_HINT_ACQ ",1"
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# define MUTEX_HINT_REL ",0"
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#else
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# define MUTEX_HINT_ACQ
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#endif
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#ifndef MUTEX_HINT_REL
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# define MUTEX_HINT_REL
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#endif
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#ifdef _ARCH_PWR4
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/*
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* Newer powerpc64 processors support the new "light weight" sync (lwsync)
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* So if the build is using -mcpu=[power4,power5,power5+,970] we can
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* safely use lwsync.
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*/
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# define atomic_read_barrier() __asm ("lwsync" ::: "memory")
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/*
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* "light weight" sync can also be used for the release barrier.
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*/
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# define atomic_write_barrier() __asm ("lwsync" ::: "memory")
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#else
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/*
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* Older powerpc32 processors don't support the new "light weight"
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* sync (lwsync). So the only safe option is to use normal sync
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* for all powerpc32 applications.
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*/
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# define atomic_read_barrier() __asm ("sync" ::: "memory")
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# define atomic_write_barrier() __asm ("sync" ::: "memory")
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#endif
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#define atomic_full_barrier() __asm ("sync" ::: "memory")
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#endif
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@ -1,65 +0,0 @@
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/* Atomic operations. PowerPC32 version.
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Copyright (C) 2003-2025 Free Software Foundation, Inc.
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This file is part of the GNU C Library.
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The GNU C Library is free software; you can redistribute it and/or
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modify it under the terms of the GNU Lesser General Public
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License as published by the Free Software Foundation; either
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version 2.1 of the License, or (at your option) any later version.
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The GNU C Library is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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Lesser General Public License for more details.
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You should have received a copy of the GNU Lesser General Public
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License along with the GNU C Library; if not, see
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<https://www.gnu.org/licenses/>. */
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/* POWER6 adds a "Mutex Hint" to the Load and Reserve instruction.
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This is a hint to the hardware to expect additional updates adjacent
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to the lock word or not. If we are acquiring a Mutex, the hint
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should be true. Otherwise we releasing a Mutex or doing a simple
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atomic operation. In that case we don't expect additional updates
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adjacent to the lock word after the Store Conditional and the hint
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should be false. */
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#if defined _ARCH_PWR6 || defined _ARCH_PWR6X
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# define MUTEX_HINT_ACQ ",1"
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# define MUTEX_HINT_REL ",0"
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#else
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# define MUTEX_HINT_ACQ
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# define MUTEX_HINT_REL
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#endif
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#define __HAVE_64B_ATOMICS 0
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#define USE_ATOMIC_COMPILER_BUILTINS 1
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#define ATOMIC_EXCHANGE_USES_CAS 1
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#ifdef _ARCH_PWR4
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/*
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* Newer powerpc64 processors support the new "light weight" sync (lwsync)
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* So if the build is using -mcpu=[power4,power5,power5+,970] we can
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* safely use lwsync.
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*/
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# define atomic_read_barrier() __asm ("lwsync" ::: "memory")
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/*
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* "light weight" sync can also be used for the release barrier.
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*/
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# define __ARCH_REL_INSTR "lwsync"
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# define atomic_write_barrier() __asm ("lwsync" ::: "memory")
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#else
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/*
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* Older powerpc32 processors don't support the new "light weight"
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* sync (lwsync). So the only safe option is to use normal sync
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* for all powerpc32 applications.
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*/
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# define atomic_read_barrier() __asm ("sync" ::: "memory")
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# define atomic_write_barrier() __asm ("sync" ::: "memory")
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#endif
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/*
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* Include the rest of the atomic ops macros which are common to both
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* powerpc32 and powerpc64.
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*/
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#include_next <atomic-machine.h>
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@ -1,53 +0,0 @@
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/* Atomic operations. PowerPC64 version.
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Copyright (C) 2003-2025 Free Software Foundation, Inc.
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This file is part of the GNU C Library.
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The GNU C Library is free software; you can redistribute it and/or
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modify it under the terms of the GNU Lesser General Public
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License as published by the Free Software Foundation; either
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version 2.1 of the License, or (at your option) any later version.
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The GNU C Library is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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Lesser General Public License for more details.
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You should have received a copy of the GNU Lesser General Public
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License along with the GNU C Library; if not, see
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<https://www.gnu.org/licenses/>. */
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/* POWER6 adds a "Mutex Hint" to the Load and Reserve instruction.
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This is a hint to the hardware to expect additional updates adjacent
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to the lock word or not. If we are acquiring a Mutex, the hint
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should be true. Otherwise we releasing a Mutex or doing a simple
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atomic operation. In that case we don't expect additional updates
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adjacent to the lock word after the Store Conditional and the hint
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should be false. */
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#if defined _ARCH_PWR6 || defined _ARCH_PWR6X
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# define MUTEX_HINT_ACQ ",1"
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# define MUTEX_HINT_REL ",0"
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#else
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# define MUTEX_HINT_ACQ
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# define MUTEX_HINT_REL
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#endif
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#define __HAVE_64B_ATOMICS 1
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#define USE_ATOMIC_COMPILER_BUILTINS 1
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#define ATOMIC_EXCHANGE_USES_CAS 1
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/*
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* All powerpc64 processors support the new "light weight" sync (lwsync).
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*/
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#define atomic_read_barrier() __asm ("lwsync" ::: "memory")
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/*
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* "light weight" sync can also be used for the release barrier.
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*/
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#define __ARCH_REL_INSTR "lwsync"
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#define atomic_write_barrier() __asm ("lwsync" ::: "memory")
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/*
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* Include the rest of the atomic ops macros which are common to both
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* powerpc32 and powerpc64.
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*/
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#include_next <atomic-machine.h>
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