mirror of git://sourceware.org/git/glibc.git
Update.
* sysdeps/i386/fpu/fedisblxcpt.c: Use dl_hwcap, not dl_hwcap_mask. * sysdeps/i386/fpu/feenablxcpt.c: Likewise. * sysdeps/i386/fpu/feholdexcpt.c: Likewise. * sysdeps/i386/fpu/fesetround.c: Likewise. * sysdeps/i386/fpu/ftestexcept.c: Likewise.
This commit is contained in:
parent
1a379ea0c7
commit
b72e048f19
|
@ -6,6 +6,12 @@
|
||||||
which has undefined symbols.
|
which has undefined symbols.
|
||||||
* elf/Makefile: Likewise.
|
* elf/Makefile: Likewise.
|
||||||
|
|
||||||
|
* sysdeps/i386/fpu/fedisblxcpt.c: Use dl_hwcap, not dl_hwcap_mask.
|
||||||
|
* sysdeps/i386/fpu/feenablxcpt.c: Likewise.
|
||||||
|
* sysdeps/i386/fpu/feholdexcpt.c: Likewise.
|
||||||
|
* sysdeps/i386/fpu/fesetround.c: Likewise.
|
||||||
|
* sysdeps/i386/fpu/ftestexcept.c: Likewise.
|
||||||
|
|
||||||
2003-07-21 HJ Lu <hongjiu.lu@intel.com>
|
2003-07-21 HJ Lu <hongjiu.lu@intel.com>
|
||||||
|
|
||||||
* elf/ldconfig.c (search_dir): Treat symlink as regular file
|
* elf/ldconfig.c (search_dir): Treat symlink as regular file
|
||||||
|
|
|
@ -39,7 +39,7 @@ fedisableexcept (int excepts)
|
||||||
__asm__ ("fldcw %0" : : "m" (*&new_exc));
|
__asm__ ("fldcw %0" : : "m" (*&new_exc));
|
||||||
|
|
||||||
/* If the CPU supports SSE we set the MXCSR as well. */
|
/* If the CPU supports SSE we set the MXCSR as well. */
|
||||||
if ((GL(dl_hwcap_mask) & HWCAP_I386_XMM) != 0)
|
if ((GL(dl_hwcap) & HWCAP_I386_XMM) != 0)
|
||||||
{
|
{
|
||||||
unsigned int xnew_exc;
|
unsigned int xnew_exc;
|
||||||
|
|
||||||
|
|
|
@ -39,7 +39,7 @@ feenableexcept (int excepts)
|
||||||
__asm__ ("fldcw %0" : : "m" (*&new_exc));
|
__asm__ ("fldcw %0" : : "m" (*&new_exc));
|
||||||
|
|
||||||
/* If the CPU supports SSE we set the MXCSR as well. */
|
/* If the CPU supports SSE we set the MXCSR as well. */
|
||||||
if ((GL(dl_hwcap_mask) & HWCAP_I386_XMM) != 0)
|
if ((GL(dl_hwcap) & HWCAP_I386_XMM) != 0)
|
||||||
{
|
{
|
||||||
unsigned int xnew_exc;
|
unsigned int xnew_exc;
|
||||||
|
|
||||||
|
|
|
@ -36,7 +36,7 @@ feholdexcept (fenv_t *envp)
|
||||||
__asm__ ("fldcw %0" : : "m" (*&work));
|
__asm__ ("fldcw %0" : : "m" (*&work));
|
||||||
|
|
||||||
/* If the CPU supports SSE we set the MXCSR as well. */
|
/* If the CPU supports SSE we set the MXCSR as well. */
|
||||||
if ((GL(dl_hwcap_mask) & HWCAP_I386_XMM) != 0)
|
if ((GL(dl_hwcap) & HWCAP_I386_XMM) != 0)
|
||||||
{
|
{
|
||||||
unsigned int xwork;
|
unsigned int xwork;
|
||||||
|
|
||||||
|
|
|
@ -38,7 +38,7 @@ fesetround (int round)
|
||||||
__asm__ ("fldcw %0" : : "m" (*&cw));
|
__asm__ ("fldcw %0" : : "m" (*&cw));
|
||||||
|
|
||||||
/* If the CPU supports SSE we set the MXCSR as well. */
|
/* If the CPU supports SSE we set the MXCSR as well. */
|
||||||
if ((GL(dl_hwcap_mask) & HWCAP_I386_XMM) != 0)
|
if ((GL(dl_hwcap) & HWCAP_I386_XMM) != 0)
|
||||||
{
|
{
|
||||||
unsigned int xcw;
|
unsigned int xcw;
|
||||||
|
|
||||||
|
|
|
@ -33,7 +33,7 @@ fetestexcept (int excepts)
|
||||||
__asm__ ("fnstsw %0" : "=a" (temp));
|
__asm__ ("fnstsw %0" : "=a" (temp));
|
||||||
|
|
||||||
/* If the CPU supports SSE we test the MXCSR as well. */
|
/* If the CPU supports SSE we test the MXCSR as well. */
|
||||||
if ((GL(dl_hwcap_mask) & HWCAP_I386_XMM) != 0)
|
if ((GL(dl_hwcap) & HWCAP_I386_XMM) != 0)
|
||||||
__asm__ ("stmxcsr %0" : "=m" (*&xtemp));
|
__asm__ ("stmxcsr %0" : "=m" (*&xtemp));
|
||||||
|
|
||||||
return (temp | xtemp) & excepts & FE_ALL_EXCEPT;
|
return (temp | xtemp) & excepts & FE_ALL_EXCEPT;
|
||||||
|
|
Loading…
Reference in New Issue