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[powerpc] Rename fegetenv_status to fegetenv_control 

fegetenv_status is used variously to retrieve the FPSCR exception enable
bits, rounding mode bits, or both.  These are referred to as the control
bits in the POWER ISA.  FPSCR status bits are also returned by the
'mffs' and 'mffsl' instructions, but they are uniformly ignored by all
uses of fegetenv_status.  Change the name to be reflective of its
current and expected use.

Reviewed-By: Paul E Murphy <murphyp@linux.ibm.com>
This commit is contained in:
Paul A. Clarke 2019-09-19 11:58:46 -05:00
parent e68b1151f7
commit 81ecb0ee49
8 changed files with 21 additions and 9 deletions
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12
ChangeLog
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@ -1,3 +1,15 @@
2019-09-27 Paul A. Clarke <pc@us.ibm.com>
* sysdeps/powerpc/fpu/fenv_libc.h (fegetenv_status): Rename to
fegetenv_control.
* sysdeps/powerpc/fpu/fedisblxcpt.c (fedisableexcept): Accommodate
rename of fegetenv_status to fegetenv_control.
* sysdeps/powerpc/fpu/feenablxcpt.c (feenableexcept): Likewise.
* sysdeps/powerpc/fpu/fegetexcept.c (__fegetexcept): Likewise.
* sysdeps/powerpc/fpu/fegetmode.c (fegetmode): Likewise.
* sysdeps/powerpc/fpu/fesetenv.c (__fesetenv): Likewise.
* sysdeps/powerpc/fpu/fesetmode.c (fesetmode): Likewise.
2019-09-27 Paul A. Clarke <pc@us.ibm.com>
* sysdeps/powerpc/fpu/fenv_libc.h (__fesetround_inline): Use

2
sysdeps/powerpc/fpu/fedisblxcpt.c
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@ -26,7 +26,7 @@ fedisableexcept (int excepts)
int result, new;
/* Get current exception mask to return. */
fe.fenv = curr.fenv = fegetenv_status ();
fe.fenv = curr.fenv = fegetenv_control ();
result = fenv_reg_to_exceptions (fe.l);
if ((excepts & FE_ALL_INVALID) == FE_ALL_INVALID)

2
sysdeps/powerpc/fpu/feenablxcpt.c
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@ -26,7 +26,7 @@ feenableexcept (int excepts)
int result, new;
/* Get current exception mask to return. */
fe.fenv = curr.fenv = fegetenv_status ();
fe.fenv = curr.fenv = fegetenv_control ();
result = fenv_reg_to_exceptions (fe.l);
if ((excepts & FE_ALL_INVALID) == FE_ALL_INVALID)

2
sysdeps/powerpc/fpu/fegetexcept.c
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@ -24,7 +24,7 @@ __fegetexcept (void)
{
fenv_union_t fe;
fe.fenv = fegetenv_status ();
fe.fenv = fegetenv_control ();
return fenv_reg_to_exceptions (fe.l);
}

2
sysdeps/powerpc/fpu/fegetmode.c
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@ -21,6 +21,6 @@
int
fegetmode (femode_t *modep)
{
*modep = fegetenv_status ();
*modep = fegetenv_control ();
return 0;
}

6
sysdeps/powerpc/fpu/fenv_libc.h
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@ -60,7 +60,7 @@ extern const fenv_t *__fe_mask_env (void) attribute_hidden;
'mffs' on architectures older than "power9" because the additional
bits set for 'mffsl' are "don't care" for 'mffs'. 'mffs' is a superset
of 'mffsl'. */
#define fegetenv_status() \
#define fegetenv_control() \
({register double __fr; \
__asm__ __volatile__ ( \
".machine push; .machine \"power9\"; mffsl %0; .machine pop" \
@ -84,7 +84,7 @@ extern const fenv_t *__fe_mask_env (void) attribute_hidden;
__fr.fenv; \
})
/* Like fegetenv_status, but also sets the rounding mode. */
/* Like fegetenv_control, but also sets the rounding mode. */
#ifdef _ARCH_PWR9
#define fegetenv_and_set_rn(rn) __fe_mffscrn (rn)
#else
@ -115,7 +115,7 @@ extern const fenv_t *__fe_mask_env (void) attribute_hidden;
/* Set the last 2 nibbles of the FPSCR, which contain the
exception enables and the rounding mode.
'fegetenv_status' retrieves these bits by reading the FPSCR. */
'fegetenv_control' retrieves these bits by reading the FPSCR. */
#define fesetenv_mode(env) __builtin_mtfsf (0b00000011, (env));
/* This very handy macro:

2
sysdeps/powerpc/fpu/fesetenv.c
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@ -26,7 +26,7 @@ __fesetenv (const fenv_t *envp)
/* get the currently set exceptions. */
new.fenv = *envp;
old.fenv = fegetenv_status ();
old.fenv = fegetenv_control ();
__TEST_AND_EXIT_NON_STOP (old.l, new.l);
__TEST_AND_ENTER_NON_STOP (old.l, new.l);

2
sysdeps/powerpc/fpu/fesetmode.c
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@ -27,7 +27,7 @@ fesetmode (const femode_t *modep)
/* Logic regarding enabled exceptions as in fesetenv. */
new.fenv = *modep;
old.fenv = fegetenv_status ();
old.fenv = fegetenv_control ();
new.l = (new.l & ~FPSCR_STATUS_MASK) | (old.l & FPSCR_STATUS_MASK);
if (old.l == new.l)