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Improve feenableexcept performance - avoid an unnecessary FPCR read in case 

the FPCR does not change. Also improve the logic of the return value.
This commit is contained in:
Wilco Dijkstra 2015-08-05 15:03:08 +01:00
parent 3136eb7abd
commit 7b1c56e483
2 changed files with 12 additions and 9 deletions
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5
ChangeLog
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@ -1,3 +1,8 @@
2015-08-05 Wilco Dijkstra <wdijkstr@arm.com>
* sysdeps/aarch64/fpu/feenablxcpt.c (feenableexcept):
Optimize to avoid an unnecessary FPCR read.
2015-08-05 Wilco Dijkstra <wdijkstr@arm.com> 2015-08-05 Wilco Dijkstra <wdijkstr@arm.com>
* sysdeps/aarch64/fpu/fesetenv.c (fesetenv): * sysdeps/aarch64/fpu/fesetenv.c (fesetenv):

16
sysdeps/aarch64/fpu/feenablxcpt.c
View File

@ -24,24 +24,22 @@ feenableexcept (int excepts)
{ {
fpu_control_t fpcr; fpu_control_t fpcr;
fpu_control_t fpcr_new; fpu_control_t fpcr_new;
fpu_control_t updated_fpcr;
_FPU_GETCW (fpcr); _FPU_GETCW (fpcr);
excepts &= FE_ALL_EXCEPT; excepts &= FE_ALL_EXCEPT;
fpcr_new = fpcr | (excepts << FE_EXCEPT_SHIFT); fpcr_new = fpcr | (excepts << FE_EXCEPT_SHIFT);
if (fpcr != fpcr_new) if (fpcr != fpcr_new)
{
_FPU_SETCW (fpcr_new); _FPU_SETCW (fpcr_new);
/* Trapping exceptions are optional in AArch64 the relevant enable /* Trapping exceptions are optional in AArch64; the relevant enable
bits in FPCR are RES0 hence the absence of support can be bits in FPCR are RES0 hence the absence of support can be detected
detected by reading back the FPCR and comparing with the required by reading back the FPCR and comparing with the required value. */
value. */
if (excepts)
{
fpu_control_t updated_fpcr;
_FPU_GETCW (updated_fpcr); _FPU_GETCW (updated_fpcr);
if (((updated_fpcr >> FE_EXCEPT_SHIFT) & excepts) != excepts)
if (fpcr_new & ~updated_fpcr)
return -1; return -1;
} }