aarch64: Use 64-bit variable to access the special registers

clang issues:

  error: value size does not match register size specified by the
  constraint and modifier [-Werror,-Wasm-operand-widths]

while tryng to use 32 bit variables with 'mrs' to get/set the
fpsr, dczid_el0, and ctr.

sysdeps/aarch64/fpu/fpu_control.h

@@ -29,17 +29,31 @@
 # define _FPU_GETFPSR(fpsr) (fpsr = __builtin_aarch64_get_fpsr ())
 # define _FPU_SETFPSR(fpsr) __builtin_aarch64_set_fpsr (fpsr)
 #else
-# define _FPU_GETCW(fpcr) \
-  __asm__ __volatile__ ("mrs	%0, fpcr" : "=r" (fpcr))
+# define _FPU_GETCW(fpcr)					\
+  ({ 								\
+   __uint64_t __fpcr;						\
+   __asm__ __volatile__ ("mrs	%0, fpcr" : "=r" (__fpcr));	\
+   fpcr = __fpcr;						\
+  })
 
-# define _FPU_SETCW(fpcr) \
-  __asm__ __volatile__ ("msr	fpcr, %0" : : "r" (fpcr))
+# define _FPU_SETCW(fpcr)					\
+  ({								\
+   __uint64_t __fpcr = fpcr;					\
+   __asm__ __volatile__ ("msr	fpcr, %0" : : "r" (__fpcr));    \
+  })
 
-# define _FPU_GETFPSR(fpsr) \
-  __asm__ __volatile__ ("mrs	%0, fpsr" : "=r" (fpsr))
+# define _FPU_GETFPSR(fpsr)					\
+  ({								\
+   __uint64_t __fpsr;						\
+   __asm__ __volatile__ ("mrs	%0, fpsr" : "=r" (__fpsr));	\
+   fpsr = __fpsr;						\
+  })
 
-# define _FPU_SETFPSR(fpsr) \
-  __asm__ __volatile__ ("msr	fpsr, %0" : : "r" (fpsr))
+# define _FPU_SETFPSR(fpsr)					\
+  ({								\
+   __uint64_t __fpsr = fpsr;					\
+   __asm__ __volatile__ ("msr	fpsr, %0" : : "r" (__fpsr));    \
+  })
 #endif
 
 /* Reserved bits should be preserved when modifying register

sysdeps/aarch64/fpu/fraiseexcpt.c

@@ -19,11 +19,12 @@
 #include <fenv.h>
 #include <fpu_control.h>
 #include <float.h>
+#include <stdint.h>
 
 int
 __feraiseexcept (int excepts)
 {
-  int fpsr;
+  uint64_t fpsr;
   const float fp_zero = 0.0;
   const float fp_one = 1.0;
   const float fp_max = FLT_MAX;

sysdeps/aarch64/sfp-machine.h

@@ -74,7 +74,7 @@ do {						\
     const float fp_1e32 = 1.0e32f;					\
     const float fp_zero = 0.0;						\
     const float fp_one = 1.0;						\
-    unsigned fpsr;							\
+    uint64_t fpsr;							\
     if (_fex & FP_EX_INVALID)						\
       {									\
         __asm__ __volatile__ ("fdiv\ts0, %s0, %s0"			\

sysdeps/unix/sysv/linux/aarch64/cpu-features.c

@@ -128,7 +128,7 @@ init_cpu_features (struct cpu_features *cpu_features)
   cpu_features->midr_el1 = midr;
 
   /* Check if ZVA is enabled.  */
-  unsigned dczid;
+  uint64_t dczid;
   asm volatile ("mrs %0, dczid_el0" : "=r"(dczid));
 
   if ((dczid & DCZID_DZP_MASK) == 0)

sysdeps/unix/sysv/linux/aarch64/sysconf.c

@@ -27,7 +27,7 @@ static long int linux_sysconf (int name);
 long int
 __sysconf (int name)
 {
-  unsigned ctr;
+  uint64_t ctr;
 
   /* Unfortunately, the registers that contain the actual cache info
      (CCSIDR_EL1, CLIDR_EL1, and CSSELR_EL1) are protected by the Linux