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i686: Skip SSE4_2 version for strcmp, strncmp, strncase, strcasecmp 

if bit_Slow_SSE4_2 is set.
This commit is contained in:
Liubov Dmitrieva 2013-08-21 18:24:44 +04:00
parent d400dcac5e
commit 46ed103824
4 changed files with 19 additions and 0 deletions
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7
ChangeLog
View File

@ -1,3 +1,10 @@
2013-08-21 Liubov Dmitrieva <liubov.dmitrieva@intel.com>
* sysdeps/i386/i686/multiarch/strcmp.S: Skip SSE4_2
version if bit_Slow_SSE4_2 is set.
* sysdeps/i386/i686/multiarch/strncase.S: Likewise.
* sysdeps/i386/i686/multiarch/strcasecmp.S: Likewise.
2013-07-23 Adhemerval Zanella <azanella@linux.vnet.ibm.com>
[BZ #15867]

4
sysdeps/i386/i686/multiarch/strcasecmp.S
View File

@ -37,6 +37,8 @@ ENTRY(__strcasecmp)
leal __strcasecmp_ssse3@GOTOFF(%ebx), %eax
testl $bit_SSE4_2, CPUID_OFFSET+index_SSE4_2+__cpu_features@GOTOFF(%ebx)
jz 2f
testl $bit_Slow_SSE4_2, CPUID_OFFSET+index_Slow_SSE4_2+__cpu_features@GOTOFF(%ebx)
jnz 2f
leal __strcasecmp_sse4_2@GOTOFF(%ebx), %eax
2: popl %ebx
cfi_adjust_cfa_offset (-4)
@ -56,6 +58,8 @@ ENTRY(__strcasecmp)
leal __strcasecmp_ssse3, %eax
testl $bit_SSE4_2, CPUID_OFFSET+index_SSE4_2+__cpu_features
jz 2f
testl $bit_Slow_SSE4_2, CPUID_OFFSET+index_Slow_SSE4_2+__cpu_features
jnz 2f
leal __strcasecmp_sse4_2, %eax
2: ret
END(__strcasecmp)

4
sysdeps/i386/i686/multiarch/strcmp.S
View File

@ -68,6 +68,8 @@ ENTRY(STRCMP)
leal __STRCMP_SSSE3@GOTOFF(%ebx), %eax
testl $bit_SSE4_2, CPUID_OFFSET+index_SSE4_2+__cpu_features@GOTOFF(%ebx)
jz 2f
testl $bit_Slow_SSE4_2, CPUID_OFFSET+index_Slow_SSE4_2+__cpu_features@GOTOFF(%ebx)
jnz 2f
leal __STRCMP_SSE4_2@GOTOFF(%ebx), %eax
2: popl %ebx
cfi_adjust_cfa_offset (-4)
@ -87,6 +89,8 @@ ENTRY(STRCMP)
leal __STRCMP_SSSE3, %eax
testl $bit_SSE4_2, CPUID_OFFSET+index_SSE4_2+__cpu_features
jz 2f
testl $bit_Slow_SSE4_2, CPUID_OFFSET+index_Slow_SSE4_2+__cpu_features
jnz 2f
leal __STRCMP_SSE4_2, %eax
2: ret
END(STRCMP)

4
sysdeps/i386/i686/multiarch/strncase.S
View File

@ -37,6 +37,8 @@ ENTRY(__strncasecmp)
leal __strncasecmp_ssse3@GOTOFF(%ebx), %eax
testl $bit_SSE4_2, CPUID_OFFSET+index_SSE4_2+__cpu_features@GOTOFF(%ebx)
jz 2f
testl $bit_Slow_SSE4_2, CPUID_OFFSET+index_Slow_SSE4_2+__cpu_features@GOTOFF(%ebx)
jnz 2f
leal __strncasecmp_sse4_2@GOTOFF(%ebx), %eax
2: popl %ebx
cfi_adjust_cfa_offset (-4)
@ -56,6 +58,8 @@ ENTRY(__strncasecmp)
leal __strncasecmp_ssse3, %eax
testl $bit_SSE4_2, CPUID_OFFSET+index_SSE4_2+__cpu_features
jz 2f
testl $bit_Slow_SSE4_2, CPUID_OFFSET+index_Slow_SSE4_2+__cpu_features
jnz 2f
leal __strncasecmp_sse4_2, %eax
2: ret
END(__strncasecmp)