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glibc/sysdeps/aarch64/fpu/advsimd_f32_protos.h

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aarch64: Add half-width versions of AdvSIMD f32 libmvec routines Compilers may emit calls to 'half-width' routines (two-lane single-precision variants). These have been added in the form of wrappers around the full-width versions, where the low half of the vector is simply duplicated. This will perform poorly when one lane triggers the special-case handler, as there will be a redundant call to the scalar version, however this is expected to be rare at Ofast. Reviewed-by: Szabolcs Nagy <szabolcs.nagy@arm.com>
2023-12-19 16:44:01 +00:00
/* Hidden prototypes for single-precision AdvSIMD routines
Update copyright dates with scripts/update-copyrights
2025-01-01 18:14:45 +00:00
Copyright (C) 2023-2025 Free Software Foundation, Inc.
aarch64: Add half-width versions of AdvSIMD f32 libmvec routines Compilers may emit calls to 'half-width' routines (two-lane single-precision variants). These have been added in the form of wrappers around the full-width versions, where the low half of the vector is simply duplicated. This will perform poorly when one lane triggers the special-case handler, as there will be a redundant call to the scalar version, however this is expected to be rare at Ofast. Reviewed-by: Szabolcs Nagy <szabolcs.nagy@arm.com>
2023-12-19 16:44:01 +00:00
This file is part of the GNU C Library.
The GNU C Library is free software; you can redistribute it and/or
modify it under the terms of the GNU Lesser General Public
License as published by the Free Software Foundation; either
version 2.1 of the License, or (at your option) any later version.
The GNU C Library is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
Lesser General Public License for more details.
You should have received a copy of the GNU Lesser General Public
License along with the GNU C Library; if not, see
<https://www.gnu.org/licenses/>. */
libmvec_hidden_proto (V_NAME_F1(acos));
aarch64/fpu: Add vector variants of acosh Reviewed-by: Szabolcs Nagy <szabolcs.nagy@arm.com>
2024-02-20 16:59:40 +00:00
libmvec_hidden_proto (V_NAME_F1(acosh));
AArch64: Implement AdvSIMD and SVE acospi/f Implement double and single precision variants of the C23 routine acospi for both AdvSIMD and SVE. Reviewed-by: Wilco Dijkstra <Wilco.Dijkstra@arm.com>
2025-05-19 12:26:50 +00:00
libmvec_hidden_proto (V_NAME_F1(acospi));
aarch64: Add half-width versions of AdvSIMD f32 libmvec routines Compilers may emit calls to 'half-width' routines (two-lane single-precision variants). These have been added in the form of wrappers around the full-width versions, where the low half of the vector is simply duplicated. This will perform poorly when one lane triggers the special-case handler, as there will be a redundant call to the scalar version, however this is expected to be rare at Ofast. Reviewed-by: Szabolcs Nagy <szabolcs.nagy@arm.com>
2023-12-19 16:44:01 +00:00
libmvec_hidden_proto (V_NAME_F1(asin));
aarch64/fpu: Add vector variants of asinh Reviewed-by: Szabolcs Nagy <szabolcs.nagy@arm.com>
2024-02-20 16:59:41 +00:00
libmvec_hidden_proto (V_NAME_F1(asinh));
AArch64: Implement AdvSIMD and SVE asinpi/f Implement double and single precision variants of the C23 routine asinpi for both AdvSIMD and SVE. Reviewed-by: Wilco Dijkstra <Wilco.Dijkstra@arm.com>
2025-05-19 12:39:51 +00:00
libmvec_hidden_proto (V_NAME_F1(asinpi));
aarch64: Add half-width versions of AdvSIMD f32 libmvec routines Compilers may emit calls to 'half-width' routines (two-lane single-precision variants). These have been added in the form of wrappers around the full-width versions, where the low half of the vector is simply duplicated. This will perform poorly when one lane triggers the special-case handler, as there will be a redundant call to the scalar version, however this is expected to be rare at Ofast. Reviewed-by: Szabolcs Nagy <szabolcs.nagy@arm.com>
2023-12-19 16:44:01 +00:00
libmvec_hidden_proto (V_NAME_F1(atan));
aarch64/fpu: Add vector variants of atanh Reviewed-by: Szabolcs Nagy <szabolcs.nagy@arm.com>
2024-04-03 11:13:53 +00:00
libmvec_hidden_proto (V_NAME_F1(atanh));
AArch64: Implement AdvSIMD and SVE atanpi/f Implement double and single precision variants of the C23 routine atanpi for both AdvSIMD and SVE. Reviewed-by: Wilco Dijkstra <Wilco.Dijkstra@arm.com>
2025-05-19 12:44:20 +00:00
libmvec_hidden_proto (V_NAME_F1(atanpi));
aarch64/fpu: Add vector variants of cbrt Reviewed-by: Szabolcs Nagy <szabolcs.nagy@arm.com>
2024-04-30 12:49:59 +00:00
libmvec_hidden_proto (V_NAME_F1(cbrt));
aarch64: Add half-width versions of AdvSIMD f32 libmvec routines Compilers may emit calls to 'half-width' routines (two-lane single-precision variants). These have been added in the form of wrappers around the full-width versions, where the low half of the vector is simply duplicated. This will perform poorly when one lane triggers the special-case handler, as there will be a redundant call to the scalar version, however this is expected to be rare at Ofast. Reviewed-by: Szabolcs Nagy <szabolcs.nagy@arm.com>
2023-12-19 16:44:01 +00:00
libmvec_hidden_proto (V_NAME_F1(cos));
aarch64/fpu: Add vector variants of cosh Reviewed-by: Szabolcs Nagy <szabolcs.nagy@arm.com>
2024-02-20 16:59:39 +00:00
libmvec_hidden_proto (V_NAME_F1(cosh));
AArch64: Add vector cospi routines Vector variant of the new C23 cospi. New tests pass on AArch64.
2025-01-03 20:12:10 +00:00
libmvec_hidden_proto (V_NAME_F1(cospi));
aarch64/fpu: Add vector variants of erf Reviewed-by: Szabolcs Nagy <szabolcs.nagy@arm.com>
2024-02-20 16:59:38 +00:00
libmvec_hidden_proto (V_NAME_F1(erf));
aarch64/fpu: Add vector variants of erfc Reviewed-by: Szabolcs Nagy <szabolcs.nagy@arm.com>
2024-02-20 16:59:45 +00:00
libmvec_hidden_proto (V_NAME_F1(erfc));
aarch64: Add half-width versions of AdvSIMD f32 libmvec routines Compilers may emit calls to 'half-width' routines (two-lane single-precision variants). These have been added in the form of wrappers around the full-width versions, where the low half of the vector is simply duplicated. This will perform poorly when one lane triggers the special-case handler, as there will be a redundant call to the scalar version, however this is expected to be rare at Ofast. Reviewed-by: Szabolcs Nagy <szabolcs.nagy@arm.com>
2023-12-19 16:44:01 +00:00
libmvec_hidden_proto (V_NAME_F1(exp10));
libmvec_hidden_proto (V_NAME_F1(exp2));
libmvec_hidden_proto (V_NAME_F1(exp));
libmvec_hidden_proto (V_NAME_F1(expm1));
AArch64: Implement exp2m1 and exp10m1 routines Vector variants of the new C23 exp2m1 & exp10m1 routines. Note: Benchmark inputs for exp2m1 & exp10m1 are identical to exp2 & exp10 respectively, this also includes the floating point variations. Reviewed-by: Wilco Dijkstra <Wilco.Dijkstra@arm.com>
2025-08-20 11:27:23 +00:00
libmvec_hidden_proto (V_NAME_F1(exp2m1));
libmvec_hidden_proto (V_NAME_F1(exp10m1));
aarch64/fpu: Add vector variants of hypot Reviewed-by: Szabolcs Nagy <szabolcs.nagy@arm.com>
2024-04-30 12:49:58 +00:00
libmvec_hidden_proto (V_NAME_F2(hypot));
aarch64: Add half-width versions of AdvSIMD f32 libmvec routines Compilers may emit calls to 'half-width' routines (two-lane single-precision variants). These have been added in the form of wrappers around the full-width versions, where the low half of the vector is simply duplicated. This will perform poorly when one lane triggers the special-case handler, as there will be a redundant call to the scalar version, however this is expected to be rare at Ofast. Reviewed-by: Szabolcs Nagy <szabolcs.nagy@arm.com>
2023-12-19 16:44:01 +00:00
libmvec_hidden_proto (V_NAME_F1(log10));
libmvec_hidden_proto (V_NAME_F1(log1p));
libmvec_hidden_proto (V_NAME_F1(log2));
AArch64: Implement AdvSIMD and SVE log2p1(f) routines Vector variants of the new C23 log2p1 routines. Note: Benchmark inputs for log2p1(f) are identical to log1p(f). Reviewed-by: Wilco Dijkstra <Wilco.Dijkstra@arm.com>
2025-09-27 10:33:19 +00:00
libmvec_hidden_proto (V_NAME_F1(log2p1));
AArch64: Add vector logp1 alias for log1p This enables vectorisation of C23 logp1, which is an alias for log1p. There are no new tests or ulp entries because the new symbols are simply aliases. Reviewed-by: Wilco Dijkstra <Wilco.Dijkstra@arm.com>
2024-09-19 16:34:02 +00:00
libmvec_hidden_proto (V_NAME_F1(logp1));
aarch64: Add half-width versions of AdvSIMD f32 libmvec routines Compilers may emit calls to 'half-width' routines (two-lane single-precision variants). These have been added in the form of wrappers around the full-width versions, where the low half of the vector is simply duplicated. This will perform poorly when one lane triggers the special-case handler, as there will be a redundant call to the scalar version, however this is expected to be rare at Ofast. Reviewed-by: Szabolcs Nagy <szabolcs.nagy@arm.com>
2023-12-19 16:44:01 +00:00
libmvec_hidden_proto (V_NAME_F1(log));
aarch64/fpu: Add vector variants of pow Plus a small amount of moving includes around in order to be able to remove duplicate definition of asuint64. Reviewed-by: Szabolcs Nagy <szabolcs.nagy@arm.com>
2024-05-16 08:21:24 +00:00
libmvec_hidden_proto (V_NAME_F2(pow));
aarch64: Add half-width versions of AdvSIMD f32 libmvec routines Compilers may emit calls to 'half-width' routines (two-lane single-precision variants). These have been added in the form of wrappers around the full-width versions, where the low half of the vector is simply duplicated. This will perform poorly when one lane triggers the special-case handler, as there will be a redundant call to the scalar version, however this is expected to be rare at Ofast. Reviewed-by: Szabolcs Nagy <szabolcs.nagy@arm.com>
2023-12-19 16:44:01 +00:00
libmvec_hidden_proto (V_NAME_F1(sin));
aarch64/fpu: Add vector variants of sinh Reviewed-by: Szabolcs Nagy <szabolcs.nagy@arm.com>
2024-04-03 11:15:41 +00:00
libmvec_hidden_proto (V_NAME_F1(sinh));
AArch64: Add vector sinpi to libmvec Vector variant of the new C23 sinpi. New tests pass on AArch64.
2025-01-03 20:07:51 +00:00
libmvec_hidden_proto (V_NAME_F1(sinpi));
aarch64: Add half-width versions of AdvSIMD f32 libmvec routines Compilers may emit calls to 'half-width' routines (two-lane single-precision variants). These have been added in the form of wrappers around the full-width versions, where the low half of the vector is simply duplicated. This will perform poorly when one lane triggers the special-case handler, as there will be a redundant call to the scalar version, however this is expected to be rare at Ofast. Reviewed-by: Szabolcs Nagy <szabolcs.nagy@arm.com>
2023-12-19 16:44:01 +00:00
libmvec_hidden_proto (V_NAME_F1(tan));
aarch64/fpu: Add vector variants of tanh Reviewed-by: Szabolcs Nagy <szabolcs.nagy@arm.com>
2024-02-20 16:59:44 +00:00
libmvec_hidden_proto (V_NAME_F1(tanh));
AArch64: Add vector tanpi routines Vector variant of the new C23 tanpi. New tests pass on AArch64.
2025-01-03 20:13:51 +00:00
libmvec_hidden_proto (V_NAME_F1(tanpi));
aarch64: Add half-width versions of AdvSIMD f32 libmvec routines Compilers may emit calls to 'half-width' routines (two-lane single-precision variants). These have been added in the form of wrappers around the full-width versions, where the low half of the vector is simply duplicated. This will perform poorly when one lane triggers the special-case handler, as there will be a redundant call to the scalar version, however this is expected to be rare at Ofast. Reviewed-by: Szabolcs Nagy <szabolcs.nagy@arm.com>
2023-12-19 16:44:01 +00:00
libmvec_hidden_proto (V_NAME_F2(atan2));
AArch64: Implement AdvSIMD and SVE atan2pi/f Implement double and single precision variants of the C23 routine atan2pi for both AdvSIMD and SVE. Reviewed-by: Wilco Dijkstra <Wilco.Dijkstra@arm.com>
2025-05-19 13:58:30 +00:00
libmvec_hidden_proto (V_NAME_F2(atan2pi));