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glibc/sysdeps/unix/sysv/linux/aarch64/libmvec.abilist

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Enable libmvec support for AArch64 This patch enables libmvec on AArch64. The proposed change is mainly implementing build infrastructure to add the new routines to ABI, tests and benchmarks. I have demonstrated how this all fits together by adding implementations for vector cos, in both single and double precision, targeting both Advanced SIMD and SVE. The implementations of the routines themselves are just loops over the scalar routine from libm for now, as we are more concerned with getting the plumbing right at this point. We plan to contribute vector routines from the Arm Optimized Routines repo that are compliant with requirements described in the libmvec wiki. Building libmvec requires minimum GCC 10 for SVE ACLE. To avoid raising the minimum GCC by such a big jump, we allow users to disable libmvec if their compiler is too old. Note that at this point users have to manually call the vector math functions. This seems to be acceptable to some downstream users. Reviewed-by: Szabolcs Nagy <szabolcs.nagy@arm.com>
2023-04-12 13:37:49 +00:00
GLIBC_2.38 _ZGVnN2v_cos F
aarch64: Add vector implementations of exp routines Optimised implementations for single and double precision, Advanced SIMD and SVE, copied from Arm Optimized Routines. As previously, data tables are used via a barrier to prevent overly aggressive constant inlining. Special-case handlers are marked NOINLINE to avoid incurring the penalty of switching call standards unnecessarily. Reviewed-by: Szabolcs Nagy <szabolcs.nagy@arm.com>
2023-06-28 11:19:39 +00:00
GLIBC_2.38 _ZGVnN2v_exp F
aarch64: Add vector implementations of log routines Optimised implementations for single and double precision, Advanced SIMD and SVE, copied from Arm Optimized Routines. Log lookup table added as HIDDEN symbol to allow it to be shared between AdvSIMD and SVE variants. As previously, data tables are used via a barrier to prevent overly aggressive constant inlining. Special-case handlers are marked NOINLINE to avoid incurring the penalty of switching call standards unnecessarily. Reviewed-by: Szabolcs Nagy <szabolcs.nagy@arm.com>
2023-06-28 11:19:38 +00:00
GLIBC_2.38 _ZGVnN2v_log F
aarch64: Add vector implementations of sin routines Optimised implementations for single and double precision, Advanced SIMD and SVE, copied from Arm Optimized Routines. As previously, data tables are used via a barrier to prevent overly aggressive constant inlining. Special-case handlers are marked NOINLINE to avoid incurring the penalty of switching call standards unnecessarily. Reviewed-by: Szabolcs Nagy <szabolcs.nagy@arm.com>
2023-06-28 11:19:37 +00:00
GLIBC_2.38 _ZGVnN2v_sin F
Enable libmvec support for AArch64 This patch enables libmvec on AArch64. The proposed change is mainly implementing build infrastructure to add the new routines to ABI, tests and benchmarks. I have demonstrated how this all fits together by adding implementations for vector cos, in both single and double precision, targeting both Advanced SIMD and SVE. The implementations of the routines themselves are just loops over the scalar routine from libm for now, as we are more concerned with getting the plumbing right at this point. We plan to contribute vector routines from the Arm Optimized Routines repo that are compliant with requirements described in the libmvec wiki. Building libmvec requires minimum GCC 10 for SVE ACLE. To avoid raising the minimum GCC by such a big jump, we allow users to disable libmvec if their compiler is too old. Note that at this point users have to manually call the vector math functions. This seems to be acceptable to some downstream users. Reviewed-by: Szabolcs Nagy <szabolcs.nagy@arm.com>
2023-04-12 13:37:49 +00:00
GLIBC_2.38 _ZGVnN4v_cosf F
aarch64: Add vector implementations of exp routines Optimised implementations for single and double precision, Advanced SIMD and SVE, copied from Arm Optimized Routines. As previously, data tables are used via a barrier to prevent overly aggressive constant inlining. Special-case handlers are marked NOINLINE to avoid incurring the penalty of switching call standards unnecessarily. Reviewed-by: Szabolcs Nagy <szabolcs.nagy@arm.com>
2023-06-28 11:19:39 +00:00
GLIBC_2.38 _ZGVnN4v_expf F
aarch64: Add vector implementations of log routines Optimised implementations for single and double precision, Advanced SIMD and SVE, copied from Arm Optimized Routines. Log lookup table added as HIDDEN symbol to allow it to be shared between AdvSIMD and SVE variants. As previously, data tables are used via a barrier to prevent overly aggressive constant inlining. Special-case handlers are marked NOINLINE to avoid incurring the penalty of switching call standards unnecessarily. Reviewed-by: Szabolcs Nagy <szabolcs.nagy@arm.com>
2023-06-28 11:19:38 +00:00
GLIBC_2.38 _ZGVnN4v_logf F
aarch64: Add vector implementations of sin routines Optimised implementations for single and double precision, Advanced SIMD and SVE, copied from Arm Optimized Routines. As previously, data tables are used via a barrier to prevent overly aggressive constant inlining. Special-case handlers are marked NOINLINE to avoid incurring the penalty of switching call standards unnecessarily. Reviewed-by: Szabolcs Nagy <szabolcs.nagy@arm.com>
2023-06-28 11:19:37 +00:00
GLIBC_2.38 _ZGVnN4v_sinf F
Enable libmvec support for AArch64 This patch enables libmvec on AArch64. The proposed change is mainly implementing build infrastructure to add the new routines to ABI, tests and benchmarks. I have demonstrated how this all fits together by adding implementations for vector cos, in both single and double precision, targeting both Advanced SIMD and SVE. The implementations of the routines themselves are just loops over the scalar routine from libm for now, as we are more concerned with getting the plumbing right at this point. We plan to contribute vector routines from the Arm Optimized Routines repo that are compliant with requirements described in the libmvec wiki. Building libmvec requires minimum GCC 10 for SVE ACLE. To avoid raising the minimum GCC by such a big jump, we allow users to disable libmvec if their compiler is too old. Note that at this point users have to manually call the vector math functions. This seems to be acceptable to some downstream users. Reviewed-by: Szabolcs Nagy <szabolcs.nagy@arm.com>
2023-04-12 13:37:49 +00:00
GLIBC_2.38 _ZGVsMxv_cos F
GLIBC_2.38 _ZGVsMxv_cosf F
aarch64: Add vector implementations of exp routines Optimised implementations for single and double precision, Advanced SIMD and SVE, copied from Arm Optimized Routines. As previously, data tables are used via a barrier to prevent overly aggressive constant inlining. Special-case handlers are marked NOINLINE to avoid incurring the penalty of switching call standards unnecessarily. Reviewed-by: Szabolcs Nagy <szabolcs.nagy@arm.com>
2023-06-28 11:19:39 +00:00
GLIBC_2.38 _ZGVsMxv_exp F
GLIBC_2.38 _ZGVsMxv_expf F
aarch64: Add vector implementations of log routines Optimised implementations for single and double precision, Advanced SIMD and SVE, copied from Arm Optimized Routines. Log lookup table added as HIDDEN symbol to allow it to be shared between AdvSIMD and SVE variants. As previously, data tables are used via a barrier to prevent overly aggressive constant inlining. Special-case handlers are marked NOINLINE to avoid incurring the penalty of switching call standards unnecessarily. Reviewed-by: Szabolcs Nagy <szabolcs.nagy@arm.com>
2023-06-28 11:19:38 +00:00
GLIBC_2.38 _ZGVsMxv_log F
GLIBC_2.38 _ZGVsMxv_logf F
aarch64: Add vector implementations of sin routines Optimised implementations for single and double precision, Advanced SIMD and SVE, copied from Arm Optimized Routines. As previously, data tables are used via a barrier to prevent overly aggressive constant inlining. Special-case handlers are marked NOINLINE to avoid incurring the penalty of switching call standards unnecessarily. Reviewed-by: Szabolcs Nagy <szabolcs.nagy@arm.com>
2023-06-28 11:19:37 +00:00
GLIBC_2.38 _ZGVsMxv_sin F
GLIBC_2.38 _ZGVsMxv_sinf F
aarch64: Add vector implementations of acos routines
2023-11-03 12:12:20 +00:00
GLIBC_2.39 _ZGVnN2v_acos F
aarch64: Add half-width versions of AdvSIMD f32 libmvec routines Compilers may emit calls to 'half-width' routines (two-lane single-precision variants). These have been added in the form of wrappers around the full-width versions, where the low half of the vector is simply duplicated. This will perform poorly when one lane triggers the special-case handler, as there will be a redundant call to the scalar version, however this is expected to be rare at Ofast. Reviewed-by: Szabolcs Nagy <szabolcs.nagy@arm.com>
2023-12-19 16:44:01 +00:00
GLIBC_2.39 _ZGVnN2v_acosf F
aarch64: Add vector implementations of asin routines
2023-11-03 12:12:19 +00:00
GLIBC_2.39 _ZGVnN2v_asin F
aarch64: Add half-width versions of AdvSIMD f32 libmvec routines Compilers may emit calls to 'half-width' routines (two-lane single-precision variants). These have been added in the form of wrappers around the full-width versions, where the low half of the vector is simply duplicated. This will perform poorly when one lane triggers the special-case handler, as there will be a redundant call to the scalar version, however this is expected to be rare at Ofast. Reviewed-by: Szabolcs Nagy <szabolcs.nagy@arm.com>
2023-12-19 16:44:01 +00:00
GLIBC_2.39 _ZGVnN2v_asinf F
aarch64: Add vector implementations of atan routines
2023-11-03 12:12:21 +00:00
GLIBC_2.39 _ZGVnN2v_atan F
aarch64: Add half-width versions of AdvSIMD f32 libmvec routines Compilers may emit calls to 'half-width' routines (two-lane single-precision variants). These have been added in the form of wrappers around the full-width versions, where the low half of the vector is simply duplicated. This will perform poorly when one lane triggers the special-case handler, as there will be a redundant call to the scalar version, however this is expected to be rare at Ofast. Reviewed-by: Szabolcs Nagy <szabolcs.nagy@arm.com>
2023-12-19 16:44:01 +00:00
GLIBC_2.39 _ZGVnN2v_atanf F
GLIBC_2.39 _ZGVnN2v_cosf F
aarch64: Add vector implementations of exp10 routines Double-precision routines either reuse the exp table (AdvSIMD) or use SVE FEXPA intruction.
2023-10-05 16:10:52 +00:00
GLIBC_2.39 _ZGVnN2v_exp10 F
aarch64: Add half-width versions of AdvSIMD f32 libmvec routines Compilers may emit calls to 'half-width' routines (two-lane single-precision variants). These have been added in the form of wrappers around the full-width versions, where the low half of the vector is simply duplicated. This will perform poorly when one lane triggers the special-case handler, as there will be a redundant call to the scalar version, however this is expected to be rare at Ofast. Reviewed-by: Szabolcs Nagy <szabolcs.nagy@arm.com>
2023-12-19 16:44:01 +00:00
GLIBC_2.39 _ZGVnN2v_exp10f F
aarch64: Add vector implementations of exp2 routines Some routines reuse table from v_exp_data.c
2023-10-05 16:10:49 +00:00
GLIBC_2.39 _ZGVnN2v_exp2 F
aarch64: Add half-width versions of AdvSIMD f32 libmvec routines Compilers may emit calls to 'half-width' routines (two-lane single-precision variants). These have been added in the form of wrappers around the full-width versions, where the low half of the vector is simply duplicated. This will perform poorly when one lane triggers the special-case handler, as there will be a redundant call to the scalar version, however this is expected to be rare at Ofast. Reviewed-by: Szabolcs Nagy <szabolcs.nagy@arm.com>
2023-12-19 16:44:01 +00:00
GLIBC_2.39 _ZGVnN2v_exp2f F
GLIBC_2.39 _ZGVnN2v_expf F
aarch64: Add vector implementations of expm1 routines May discard sign of 0 - auto tests for -0 and -0x1p-10000 updated accordingly.
2023-11-16 13:24:18 +00:00
GLIBC_2.39 _ZGVnN2v_expm1 F
aarch64: Add half-width versions of AdvSIMD f32 libmvec routines Compilers may emit calls to 'half-width' routines (two-lane single-precision variants). These have been added in the form of wrappers around the full-width versions, where the low half of the vector is simply duplicated. This will perform poorly when one lane triggers the special-case handler, as there will be a redundant call to the scalar version, however this is expected to be rare at Ofast. Reviewed-by: Szabolcs Nagy <szabolcs.nagy@arm.com>
2023-12-19 16:44:01 +00:00
GLIBC_2.39 _ZGVnN2v_expm1f F
aarch64: Add vector implementations of log10 routines A table is also added, which is shared between AdvSIMD and SVE log10.
2023-10-05 16:10:51 +00:00
GLIBC_2.39 _ZGVnN2v_log10 F
aarch64: Add half-width versions of AdvSIMD f32 libmvec routines Compilers may emit calls to 'half-width' routines (two-lane single-precision variants). These have been added in the form of wrappers around the full-width versions, where the low half of the vector is simply duplicated. This will perform poorly when one lane triggers the special-case handler, as there will be a redundant call to the scalar version, however this is expected to be rare at Ofast. Reviewed-by: Szabolcs Nagy <szabolcs.nagy@arm.com>
2023-12-19 16:44:01 +00:00
GLIBC_2.39 _ZGVnN2v_log10f F
aarch64: Add vector implementations of log1p routines May discard sign of zero.
2023-11-03 12:12:23 +00:00
GLIBC_2.39 _ZGVnN2v_log1p F
aarch64: Add half-width versions of AdvSIMD f32 libmvec routines Compilers may emit calls to 'half-width' routines (two-lane single-precision variants). These have been added in the form of wrappers around the full-width versions, where the low half of the vector is simply duplicated. This will perform poorly when one lane triggers the special-case handler, as there will be a redundant call to the scalar version, however this is expected to be rare at Ofast. Reviewed-by: Szabolcs Nagy <szabolcs.nagy@arm.com>
2023-12-19 16:44:01 +00:00
GLIBC_2.39 _ZGVnN2v_log1pf F
aarch64: Add vector implementations of log2 routines A table is also added, which is shared between AdvSIMD and SVE log2.
2023-10-05 16:10:50 +00:00
GLIBC_2.39 _ZGVnN2v_log2 F
aarch64: Add half-width versions of AdvSIMD f32 libmvec routines Compilers may emit calls to 'half-width' routines (two-lane single-precision variants). These have been added in the form of wrappers around the full-width versions, where the low half of the vector is simply duplicated. This will perform poorly when one lane triggers the special-case handler, as there will be a redundant call to the scalar version, however this is expected to be rare at Ofast. Reviewed-by: Szabolcs Nagy <szabolcs.nagy@arm.com>
2023-12-19 16:44:01 +00:00
GLIBC_2.39 _ZGVnN2v_log2f F
GLIBC_2.39 _ZGVnN2v_logf F
GLIBC_2.39 _ZGVnN2v_sinf F
aarch64: Add vector implementations of tan routines This includes some utility headers for evaluating polynomials using various schemes.
2023-10-05 16:10:48 +00:00
GLIBC_2.39 _ZGVnN2v_tan F
aarch64: Add half-width versions of AdvSIMD f32 libmvec routines Compilers may emit calls to 'half-width' routines (two-lane single-precision variants). These have been added in the form of wrappers around the full-width versions, where the low half of the vector is simply duplicated. This will perform poorly when one lane triggers the special-case handler, as there will be a redundant call to the scalar version, however this is expected to be rare at Ofast. Reviewed-by: Szabolcs Nagy <szabolcs.nagy@arm.com>
2023-12-19 16:44:01 +00:00
GLIBC_2.39 _ZGVnN2v_tanf F
aarch64: Add vector implementations of atan2 routines
2023-11-03 12:12:22 +00:00
GLIBC_2.39 _ZGVnN2vv_atan2 F
aarch64: Add half-width versions of AdvSIMD f32 libmvec routines Compilers may emit calls to 'half-width' routines (two-lane single-precision variants). These have been added in the form of wrappers around the full-width versions, where the low half of the vector is simply duplicated. This will perform poorly when one lane triggers the special-case handler, as there will be a redundant call to the scalar version, however this is expected to be rare at Ofast. Reviewed-by: Szabolcs Nagy <szabolcs.nagy@arm.com>
2023-12-19 16:44:01 +00:00
GLIBC_2.39 _ZGVnN2vv_atan2f F
aarch64: Add vector implementations of acos routines
2023-11-03 12:12:20 +00:00
GLIBC_2.39 _ZGVnN4v_acosf F
aarch64: Add vector implementations of asin routines
2023-11-03 12:12:19 +00:00
GLIBC_2.39 _ZGVnN4v_asinf F
aarch64: Add vector implementations of atan routines
2023-11-03 12:12:21 +00:00
GLIBC_2.39 _ZGVnN4v_atanf F
aarch64: Add vector implementations of exp10 routines Double-precision routines either reuse the exp table (AdvSIMD) or use SVE FEXPA intruction.
2023-10-05 16:10:52 +00:00
GLIBC_2.39 _ZGVnN4v_exp10f F
aarch64: Add vector implementations of exp2 routines Some routines reuse table from v_exp_data.c
2023-10-05 16:10:49 +00:00
GLIBC_2.39 _ZGVnN4v_exp2f F
aarch64: Add vector implementations of expm1 routines May discard sign of 0 - auto tests for -0 and -0x1p-10000 updated accordingly.
2023-11-16 13:24:18 +00:00
GLIBC_2.39 _ZGVnN4v_expm1f F
aarch64: Add vector implementations of log10 routines A table is also added, which is shared between AdvSIMD and SVE log10.
2023-10-05 16:10:51 +00:00
GLIBC_2.39 _ZGVnN4v_log10f F
aarch64: Add vector implementations of log1p routines May discard sign of zero.
2023-11-03 12:12:23 +00:00
GLIBC_2.39 _ZGVnN4v_log1pf F
aarch64: Add vector implementations of log2 routines A table is also added, which is shared between AdvSIMD and SVE log2.
2023-10-05 16:10:50 +00:00
GLIBC_2.39 _ZGVnN4v_log2f F
aarch64: Add vector implementations of tan routines This includes some utility headers for evaluating polynomials using various schemes.
2023-10-05 16:10:48 +00:00
GLIBC_2.39 _ZGVnN4v_tanf F
aarch64: Add vector implementations of atan2 routines
2023-11-03 12:12:22 +00:00
GLIBC_2.39 _ZGVnN4vv_atan2f F
aarch64: Add vector implementations of acos routines
2023-11-03 12:12:20 +00:00
GLIBC_2.39 _ZGVsMxv_acos F
GLIBC_2.39 _ZGVsMxv_acosf F
aarch64: Add vector implementations of asin routines
2023-11-03 12:12:19 +00:00
GLIBC_2.39 _ZGVsMxv_asin F
GLIBC_2.39 _ZGVsMxv_asinf F
aarch64: Add vector implementations of atan routines
2023-11-03 12:12:21 +00:00
GLIBC_2.39 _ZGVsMxv_atan F
GLIBC_2.39 _ZGVsMxv_atanf F
aarch64: Add vector implementations of exp10 routines Double-precision routines either reuse the exp table (AdvSIMD) or use SVE FEXPA intruction.
2023-10-05 16:10:52 +00:00
GLIBC_2.39 _ZGVsMxv_exp10 F
GLIBC_2.39 _ZGVsMxv_exp10f F
aarch64: Add vector implementations of exp2 routines Some routines reuse table from v_exp_data.c
2023-10-05 16:10:49 +00:00
GLIBC_2.39 _ZGVsMxv_exp2 F
GLIBC_2.39 _ZGVsMxv_exp2f F
aarch64: Add vector implementations of expm1 routines May discard sign of 0 - auto tests for -0 and -0x1p-10000 updated accordingly.
2023-11-16 13:24:18 +00:00
GLIBC_2.39 _ZGVsMxv_expm1 F
GLIBC_2.39 _ZGVsMxv_expm1f F
aarch64: Add vector implementations of log10 routines A table is also added, which is shared between AdvSIMD and SVE log10.
2023-10-05 16:10:51 +00:00
GLIBC_2.39 _ZGVsMxv_log10 F
GLIBC_2.39 _ZGVsMxv_log10f F
aarch64: Add vector implementations of log1p routines May discard sign of zero.
2023-11-03 12:12:23 +00:00
GLIBC_2.39 _ZGVsMxv_log1p F
GLIBC_2.39 _ZGVsMxv_log1pf F
aarch64: Add vector implementations of log2 routines A table is also added, which is shared between AdvSIMD and SVE log2.
2023-10-05 16:10:50 +00:00
GLIBC_2.39 _ZGVsMxv_log2 F
GLIBC_2.39 _ZGVsMxv_log2f F
aarch64: Add vector implementations of tan routines This includes some utility headers for evaluating polynomials using various schemes.
2023-10-05 16:10:48 +00:00
GLIBC_2.39 _ZGVsMxv_tan F
GLIBC_2.39 _ZGVsMxv_tanf F
aarch64: Add vector implementations of atan2 routines
2023-11-03 12:12:22 +00:00
GLIBC_2.39 _ZGVsMxvv_atan2 F
GLIBC_2.39 _ZGVsMxvv_atan2f F
aarch64/fpu: Add vector variants of acosh Reviewed-by: Szabolcs Nagy <szabolcs.nagy@arm.com>
2024-02-20 16:59:40 +00:00
GLIBC_2.40 _ZGVnN2v_acosh F
GLIBC_2.40 _ZGVnN2v_acoshf F
aarch64/fpu: Add vector variants of asinh Reviewed-by: Szabolcs Nagy <szabolcs.nagy@arm.com>
2024-02-20 16:59:41 +00:00
GLIBC_2.40 _ZGVnN2v_asinh F
GLIBC_2.40 _ZGVnN2v_asinhf F
aarch64/fpu: Add vector variants of atanh Reviewed-by: Szabolcs Nagy <szabolcs.nagy@arm.com>
2024-04-03 11:13:53 +00:00
GLIBC_2.40 _ZGVnN2v_atanh F
GLIBC_2.40 _ZGVnN2v_atanhf F
aarch64/fpu: Add vector variants of cbrt Reviewed-by: Szabolcs Nagy <szabolcs.nagy@arm.com>
2024-04-30 12:49:59 +00:00
GLIBC_2.40 _ZGVnN2v_cbrt F
GLIBC_2.40 _ZGVnN2v_cbrtf F
aarch64/fpu: Add vector variants of cosh Reviewed-by: Szabolcs Nagy <szabolcs.nagy@arm.com>
2024-02-20 16:59:39 +00:00
GLIBC_2.40 _ZGVnN2v_cosh F
GLIBC_2.40 _ZGVnN2v_coshf F
aarch64/fpu: Add vector variants of erf Reviewed-by: Szabolcs Nagy <szabolcs.nagy@arm.com>
2024-02-20 16:59:38 +00:00
GLIBC_2.40 _ZGVnN2v_erf F
aarch64/fpu: Add vector variants of erfc Reviewed-by: Szabolcs Nagy <szabolcs.nagy@arm.com>
2024-02-20 16:59:45 +00:00
GLIBC_2.40 _ZGVnN2v_erfc F
GLIBC_2.40 _ZGVnN2v_erfcf F
aarch64/fpu: Add vector variants of erf Reviewed-by: Szabolcs Nagy <szabolcs.nagy@arm.com>
2024-02-20 16:59:38 +00:00
GLIBC_2.40 _ZGVnN2v_erff F
aarch64/fpu: Add vector variants of sinh Reviewed-by: Szabolcs Nagy <szabolcs.nagy@arm.com>
2024-04-03 11:15:41 +00:00
GLIBC_2.40 _ZGVnN2v_sinh F
GLIBC_2.40 _ZGVnN2v_sinhf F
aarch64/fpu: Add vector variants of tanh Reviewed-by: Szabolcs Nagy <szabolcs.nagy@arm.com>
2024-02-20 16:59:44 +00:00
GLIBC_2.40 _ZGVnN2v_tanh F
GLIBC_2.40 _ZGVnN2v_tanhf F
aarch64/fpu: Add vector variants of hypot Reviewed-by: Szabolcs Nagy <szabolcs.nagy@arm.com>
2024-04-30 12:49:58 +00:00
GLIBC_2.40 _ZGVnN2vv_hypot F
GLIBC_2.40 _ZGVnN2vv_hypotf F
aarch64/fpu: Add vector variants of acosh Reviewed-by: Szabolcs Nagy <szabolcs.nagy@arm.com>
2024-02-20 16:59:40 +00:00
GLIBC_2.40 _ZGVnN4v_acoshf F
aarch64/fpu: Add vector variants of asinh Reviewed-by: Szabolcs Nagy <szabolcs.nagy@arm.com>
2024-02-20 16:59:41 +00:00
GLIBC_2.40 _ZGVnN4v_asinhf F
aarch64/fpu: Add vector variants of atanh Reviewed-by: Szabolcs Nagy <szabolcs.nagy@arm.com>
2024-04-03 11:13:53 +00:00
GLIBC_2.40 _ZGVnN4v_atanhf F
aarch64/fpu: Add vector variants of cbrt Reviewed-by: Szabolcs Nagy <szabolcs.nagy@arm.com>
2024-04-30 12:49:59 +00:00
GLIBC_2.40 _ZGVnN4v_cbrtf F
aarch64/fpu: Add vector variants of cosh Reviewed-by: Szabolcs Nagy <szabolcs.nagy@arm.com>
2024-02-20 16:59:39 +00:00
GLIBC_2.40 _ZGVnN4v_coshf F
aarch64/fpu: Add vector variants of erfc Reviewed-by: Szabolcs Nagy <szabolcs.nagy@arm.com>
2024-02-20 16:59:45 +00:00
GLIBC_2.40 _ZGVnN4v_erfcf F
aarch64/fpu: Add vector variants of erf Reviewed-by: Szabolcs Nagy <szabolcs.nagy@arm.com>
2024-02-20 16:59:38 +00:00
GLIBC_2.40 _ZGVnN4v_erff F
aarch64/fpu: Add vector variants of sinh Reviewed-by: Szabolcs Nagy <szabolcs.nagy@arm.com>
2024-04-03 11:15:41 +00:00
GLIBC_2.40 _ZGVnN4v_sinhf F
aarch64/fpu: Add vector variants of tanh Reviewed-by: Szabolcs Nagy <szabolcs.nagy@arm.com>
2024-02-20 16:59:44 +00:00
GLIBC_2.40 _ZGVnN4v_tanhf F
aarch64/fpu: Add vector variants of hypot Reviewed-by: Szabolcs Nagy <szabolcs.nagy@arm.com>
2024-04-30 12:49:58 +00:00
GLIBC_2.40 _ZGVnN4vv_hypotf F
aarch64/fpu: Add vector variants of acosh Reviewed-by: Szabolcs Nagy <szabolcs.nagy@arm.com>
2024-02-20 16:59:40 +00:00
GLIBC_2.40 _ZGVsMxv_acosh F
GLIBC_2.40 _ZGVsMxv_acoshf F
aarch64/fpu: Add vector variants of asinh Reviewed-by: Szabolcs Nagy <szabolcs.nagy@arm.com>
2024-02-20 16:59:41 +00:00
GLIBC_2.40 _ZGVsMxv_asinh F
GLIBC_2.40 _ZGVsMxv_asinhf F
aarch64/fpu: Add vector variants of atanh Reviewed-by: Szabolcs Nagy <szabolcs.nagy@arm.com>
2024-04-03 11:13:53 +00:00
GLIBC_2.40 _ZGVsMxv_atanh F
GLIBC_2.40 _ZGVsMxv_atanhf F
aarch64/fpu: Add vector variants of cbrt Reviewed-by: Szabolcs Nagy <szabolcs.nagy@arm.com>
2024-04-30 12:49:59 +00:00
GLIBC_2.40 _ZGVsMxv_cbrt F
GLIBC_2.40 _ZGVsMxv_cbrtf F
aarch64/fpu: Add vector variants of cosh Reviewed-by: Szabolcs Nagy <szabolcs.nagy@arm.com>
2024-02-20 16:59:39 +00:00
GLIBC_2.40 _ZGVsMxv_cosh F
GLIBC_2.40 _ZGVsMxv_coshf F
aarch64/fpu: Add vector variants of erf Reviewed-by: Szabolcs Nagy <szabolcs.nagy@arm.com>
2024-02-20 16:59:38 +00:00
GLIBC_2.40 _ZGVsMxv_erf F
aarch64/fpu: Add vector variants of erfc Reviewed-by: Szabolcs Nagy <szabolcs.nagy@arm.com>
2024-02-20 16:59:45 +00:00
GLIBC_2.40 _ZGVsMxv_erfc F
GLIBC_2.40 _ZGVsMxv_erfcf F
aarch64/fpu: Add vector variants of erf Reviewed-by: Szabolcs Nagy <szabolcs.nagy@arm.com>
2024-02-20 16:59:38 +00:00
GLIBC_2.40 _ZGVsMxv_erff F
aarch64/fpu: Add vector variants of sinh Reviewed-by: Szabolcs Nagy <szabolcs.nagy@arm.com>
2024-04-03 11:15:41 +00:00
GLIBC_2.40 _ZGVsMxv_sinh F
GLIBC_2.40 _ZGVsMxv_sinhf F
aarch64/fpu: Add vector variants of tanh Reviewed-by: Szabolcs Nagy <szabolcs.nagy@arm.com>
2024-02-20 16:59:44 +00:00
GLIBC_2.40 _ZGVsMxv_tanh F
GLIBC_2.40 _ZGVsMxv_tanhf F
aarch64/fpu: Add vector variants of hypot Reviewed-by: Szabolcs Nagy <szabolcs.nagy@arm.com>
2024-04-30 12:49:58 +00:00
GLIBC_2.40 _ZGVsMxvv_hypot F
GLIBC_2.40 _ZGVsMxvv_hypotf F