219 lines
7.3 KiB
Rust
219 lines
7.3 KiB
Rust
// SPDX-License-Identifier: MPL-2.0
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#![allow(dead_code)]
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#![allow(unused_variables)]
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use alloc::vec::Vec;
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use core::fmt::Debug;
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use bitflags::bitflags;
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use log::info;
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use spin::Once;
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use trapframe::TrapFrame;
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use volatile::{access::ReadWrite, Volatile};
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use super::registers::Capability;
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use crate::{mm::Vaddr, trap::IrqLine};
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#[derive(Debug)]
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pub struct FaultEventRegisters {
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status: Volatile<&'static mut u32, ReadWrite>,
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/// bit31: Interrupt Mask; bit30: Interrupt Pending.
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control: Volatile<&'static mut u32, ReadWrite>,
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data: Volatile<&'static mut u32, ReadWrite>,
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address: Volatile<&'static mut u32, ReadWrite>,
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upper_address: Volatile<&'static mut u32, ReadWrite>,
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recordings: Vec<Volatile<&'static mut u128, ReadWrite>>,
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fault_irq: IrqLine,
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}
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impl FaultEventRegisters {
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pub fn status(&self) -> FaultStatus {
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FaultStatus::from_bits_truncate(self.status.read())
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}
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/// Create an instance from base address.
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///
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/// # Safety
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///
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/// User must ensure the base_register_vaddr is read from DRHD
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unsafe fn new(base_register_vaddr: Vaddr) -> Self {
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let capability_reg =
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Volatile::new_read_only(&*((base_register_vaddr + 0x08) as *const u64));
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let capability = Capability::new(capability_reg.read());
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let length = capability.fault_recording_number() + 1;
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let mut recordings = Vec::with_capacity(length as usize);
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let offset = capability.fault_recording_register_offset();
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for i in 0..length {
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recordings.push(Volatile::new(
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&mut *((base_register_vaddr + 16 * (offset + i) as usize) as *mut u128),
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))
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}
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let status = Volatile::new(&mut *((base_register_vaddr + 0x34) as *mut u32));
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let mut control = Volatile::new(&mut *((base_register_vaddr + 0x38) as *mut u32));
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let mut data = Volatile::new(&mut *((base_register_vaddr + 0x3c) as *mut u32));
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let mut address = Volatile::new(&mut *((base_register_vaddr + 0x40) as *mut u32));
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let upper_address = Volatile::new(&mut *((base_register_vaddr + 0x44) as *mut u32));
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let mut fault_irq = IrqLine::alloc().unwrap();
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// Set page fault interrupt vector and address
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data.write(fault_irq.num() as u32);
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address.write(0xFEE0_0000);
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control.write(0);
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fault_irq.on_active(iommu_page_fault_handler);
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FaultEventRegisters {
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status,
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control,
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data,
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address,
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upper_address,
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recordings,
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fault_irq,
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}
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}
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}
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pub struct FaultRecording(u128);
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impl FaultRecording {
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pub fn is_fault(&self) -> bool {
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self.0 & (1 << 127) != 0
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}
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pub fn request_type(&self) -> FaultRequestType {
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// bit 126 and bit 92
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let t1 = ((self.0 & (1 << 126)) >> 125) as u8;
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let t2 = ((self.0 & (1 << 92)) >> 92) as u8;
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let typ = t1 + t2;
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match typ {
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0 => FaultRequestType::Write,
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1 => FaultRequestType::Page,
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2 => FaultRequestType::Read,
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3 => FaultRequestType::AtomicOp,
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_ => unreachable!(),
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}
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}
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pub fn address_type(&self) -> FaultAddressType {
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match self.0 & (3 << 124) {
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0 => FaultAddressType::UntranslatedRequest,
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1 => FaultAddressType::TranslationRequest,
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2 => FaultAddressType::TranslatedRequest,
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_ => unreachable!(),
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}
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}
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pub fn source_identifier(&self) -> u16 {
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// bit 79:64
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((self.0 & 0xFFFF_0000_0000_0000_0000) >> 64) as u16
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}
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/// If fault reason is one of the address translation fault conditions, this field contains bits 63:12
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/// of the page address in the faulted request.
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///
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/// If fault reason is interrupt-remapping fault conditions other than fault reash 0x25, bits 63:48
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/// indicate the interrupt index computed for the faulted interrupt request, and bits 47:12 are cleared.
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///
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/// If fault reason is interrupt-remapping fault conditions of blocked compatibility mode interrupt (fault reason 0x25),
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/// this field is undefined.
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pub fn fault_info(&self) -> u64 {
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// bit 63:12
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((self.0 & 0xFFFF_FFFF_FFFF_F000) >> 12) as u64
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}
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pub fn pasid_value(&self) -> u32 {
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// bit 123:104
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((self.0 & 0x00FF_FFF0_0000_0000_0000_0000_0000_0000) >> 104) as u32
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}
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pub fn fault_reason(&self) -> u8 {
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// bit 103:96
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((self.0 & 0xF_0000_0000_0000_0000_0000_0000) >> 96) as u8
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}
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pub fn pasid_present(&self) -> bool {
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// bit 95
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(self.0 & 0x8000_0000_0000_0000_0000_0000) != 0
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}
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pub fn execute_permission_request(&self) -> bool {
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// bit 94
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(self.0 & 0x4000_0000_0000_0000_0000_0000) != 0
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}
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pub fn privilege_mode_request(&self) -> bool {
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// bit 93
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(self.0 & 0x2000_0000_0000_0000_0000_0000) != 0
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}
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}
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impl Debug for FaultRecording {
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fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
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f.debug_struct("FaultRecording")
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.field("Fault", &self.is_fault())
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.field("Request type", &self.request_type())
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.field("Address type", &self.address_type())
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.field("Source identifier", &self.source_identifier())
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.field("Fault Reason", &self.fault_reason())
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.field("Fault info", &self.fault_info())
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.field("Raw", &self.0)
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.finish()
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}
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}
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#[derive(Debug)]
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#[repr(u8)]
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pub enum FaultRequestType {
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Write = 0,
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Page = 1,
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Read = 2,
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AtomicOp = 3,
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}
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#[derive(Debug)]
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#[repr(u8)]
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#[allow(clippy::enum_variant_names)]
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pub enum FaultAddressType {
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UntranslatedRequest = 0,
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TranslationRequest = 1,
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TranslatedRequest = 2,
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}
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bitflags! {
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pub struct FaultStatus : u32{
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/// Primary Fault Overflow, indicates overflow of the fault recording registers.
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const PFO = 1 << 0;
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/// Primary Pending Fault, indicates there are one or more pending faults logged in the fault recording registers.
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const PPF = 1 << 1;
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/// Invalidation Queue Error.
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const IQE = 1 << 4;
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/// Invalidation Completion Error. Hardware received an unexpected or invalid Device-TLB invalidation completion.
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const ICE = 1 << 5;
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/// Invalidation Time-out Error. Hardware detected a Device-TLB invalidation completion time-out.
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const ITE = 1 << 6;
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/// Fault Record Index, valid only when PPF field is set. This field indicates the index (from base) of the fault recording register
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/// to which the first pending fault was recorded when the PPF field was Set by hardware.
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const FRI = (0xFF) << 8;
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}
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}
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pub(super) static FAULT_EVENT_REGS: Once<FaultEventRegisters> = Once::new();
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/// Initializes the fault reporting function.
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///
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/// # Safety
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///
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/// User must ensure the base_register_vaddr is read from DRHD
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pub(super) unsafe fn init(base_register_vaddr: Vaddr) {
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FAULT_EVENT_REGS.call_once(|| FaultEventRegisters::new(base_register_vaddr));
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}
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fn iommu_page_fault_handler(frame: &TrapFrame) {
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let fault_event = FAULT_EVENT_REGS.get().unwrap();
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let index = (fault_event.status().bits & FaultStatus::FRI.bits) >> 8;
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let recording = FaultRecording(fault_event.recordings[index as usize].read());
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info!("Catch iommu page fault, recording:{:x?}", recording)
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}
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