431 lines
15 KiB
Rust
431 lines
15 KiB
Rust
// SPDX-License-Identifier: MPL-2.0
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//! The PCI configuration space.
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//!
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//! Reference: <https://wiki.osdev.org/PCI>
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use alloc::sync::Arc;
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use bitflags::bitflags;
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use ostd::{
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arch::device::io_port::{PortRead, PortWrite},
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io::IoMem,
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mm::{PodOnce, VmIoOnce},
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Error, Result,
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};
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use spin::Once;
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use super::PciDeviceLocation;
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/// Offset in PCI device's common configuration space(Not the PCI bridge).
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#[repr(u16)]
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pub enum PciDeviceCommonCfgOffset {
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/// Vendor ID
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VendorId = 0x00,
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/// Device ID
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DeviceId = 0x02,
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/// PCI Command
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Command = 0x04,
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/// PCI Status
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Status = 0x06,
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/// Revision ID
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RevisionId = 0x08,
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/// Class code
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ClassCode = 0x09,
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/// Cache Line Size
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CacheLineSize = 0x0C,
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/// Latency Timer
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LatencyTimer = 0x0D,
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/// Header Type: Identifies the layout of the header.
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HeaderType = 0x0E,
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/// BIST: Represents the status and allows control of a devices BIST(built-in self test).
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Bist = 0x0F,
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/// Base Address Register #0
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Bar0 = 0x10,
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/// Base Address Register #1
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Bar1 = 0x14,
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/// Base Address Register #2
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Bar2 = 0x18,
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/// Base Address Register #3
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Bar3 = 0x1C,
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/// Base Address Register #4
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Bar4 = 0x20,
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/// Base Address Register #5
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Bar5 = 0x24,
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/// Cardbus CIS Pointer
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CardbusCisPtr = 0x28,
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/// Subsystem Vendor ID
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SubsystemVendorId = 0x2C,
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/// Subsystem ID
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SubsystemId = 0x2E,
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/// Expansion ROM base address
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XromBar = 0x30,
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/// Capabilities pointer
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CapabilitiesPointer = 0x34,
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/// Interrupt Line
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InterruptLine = 0x3C,
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/// INterrupt PIN
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InterruptPin = 0x3D,
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/// Min Grant
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MinGrant = 0x3E,
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/// Max latency
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MaxLatency = 0x3F,
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}
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bitflags! {
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/// PCI device common config space command register.
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pub struct Command: u16 {
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/// Sets to 1 if the device can respond to I/O Space accesses.
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const IO_SPACE = 1 << 0;
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/// Sets to 1 if the device can respond to Memory SPace accesses.
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const MEMORY_SPACE = 1 << 1;
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/// Sets to 1 if the device can behave as a bus master.
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const BUS_MASTER = 1 << 2;
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/// Sets to 1 if the device can monitor Special Cycle operations.
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const SPECIAL_CYCLES = 1 << 3;
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/// Memory Write and Invalidate Enable. Set to 1 if the device can
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/// generate the Memory Write and Invalidate command.
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const MWI_ENABLE = 1 << 4;
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/// Sets to 1 if the device does not respond to palette register writes
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/// and will snoop the data.
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const VGA_PALETTE_SNOOP = 1 << 5;
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/// Sets to 1 if the device will takes its normal action when a parity
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/// error is detected.
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const PARITY_ERROR_RESPONSE = 1 << 6;
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/// Sets to 1 if the SERR# driver is enabled.
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const SERR_ENABLE = 1 << 8;
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/// Sets to 1 if the device is allowed to generate fast back-to-back
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/// transactions
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const FAST_BACK_TO_BACK_ENABLE = 1 << 9;
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/// Sets to 1 if the assertion of the devices INTx# signal is disabled.
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const INTERRUPT_DISABLE = 1 << 10;
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}
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}
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bitflags! {
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/// PCI device common config space status register.
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pub struct Status: u16 {
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/// The status of the device's INTx# signal.
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const INTERRUPT_STATUS = 1 << 3;
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/// Sets to 1 if the device support capabilities.
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const CAPABILITIES_LIST = 1 << 4;
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/// Sets to 1 if the device is capable of running at 66 MHz.
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const MHZ66_CAPABLE = 1 << 5;
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/// Sets to 1 if the device can accept fast back-to-back transactions
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/// that are not from the same agent.
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const FAST_BACK_TO_BACK_CAPABLE = 1 << 7;
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/// This bit is only set when the following conditions are met:
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/// 1. The bus agent asserted PERR# on a read or observed an assertion
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/// of PERR# on a write
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/// 2. The agent setting the bit acted as the bus master for the
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/// operation in which the error occurred
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/// 3. Bit 6 of the Command register (Parity Error Response bit) is set
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/// to 1.
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const MASTER_DATA_PARITY_ERROR = 1 << 8;
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/// The read-only bit that represent the slowest time that a device will
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/// assert DEVSEL# for any bus command except Configuration Space read
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/// and writes.
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///
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/// If both `DEVSEL_MEDIUM_TIMING` and `DEVSEL_SLOW_TIMING` are not set,
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/// then it represents fast timing
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const DEVSEL_MEDIUM_TIMING = 1 << 9;
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/// Check `DEVSEL_MEDIUM_TIMING`
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const DEVSEL_SLOW_TIMING = 1 << 10;
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/// Sets to 1 when a target device terminates a transaction with Target-
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/// Abort.
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const SIGNALED_TARGET_ABORT = 1 << 11;
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/// Sets to 1 by a master device when its transaction is terminated with
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/// Target-Abort
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const RECEIVED_TARGET_ABORT = 1 << 12;
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/// Sets to 1 by a master device when its transaction (except for Special
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/// Cycle transactions) is terminated with Master-Abort.
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const RECEIVED_MASTER_ABORT = 1 << 13;
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/// Sets to 1 when the device asserts SERR#
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const SIGNALED_SYSTEM_ERROR = 1 << 14;
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/// Sets to 1 when the device detects a parity error, even if parity error
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/// handling is disabled.
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const DETECTED_PARITY_ERROR = 1 << 15;
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}
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}
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/// BAR space in PCI common config space.
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#[derive(Debug, Clone)]
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pub enum Bar {
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/// Memory BAR
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Memory(Arc<MemoryBar>),
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/// I/O BAR
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Io(Arc<IoBar>),
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}
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impl Bar {
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pub(super) fn new(location: PciDeviceLocation, index: u8) -> Result<Self> {
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if index >= 6 {
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return Err(Error::InvalidArgs);
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}
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let offset = index as u16 * 4 + PciDeviceCommonCfgOffset::Bar0 as u16;
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let raw = location.read32(offset);
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// Check the "Space Indicator" bit.
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let result = if raw & 1 == 0 {
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// Memory BAR
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Self::Memory(Arc::new(MemoryBar::new(&location, index, raw)?))
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} else {
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// I/O port BAR
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Self::Io(Arc::new(IoBar::new(&location, index, raw)?))
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};
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Ok(result)
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}
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/// Reads a value of a specified type at a specified offset.
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pub fn read_once<T: PodOnce + PortRead>(&self, offset: usize) -> Result<T> {
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match self {
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Bar::Memory(mem_bar) => mem_bar.io_mem().read_once(offset),
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Bar::Io(io_bar) => io_bar.read(offset as u32),
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}
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}
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/// Writes a value of a specified type at a specified offset.
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pub fn write_once<T: PodOnce + PortWrite>(&self, offset: usize, value: T) -> Result<()> {
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match self {
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Bar::Memory(mem_bar) => mem_bar.io_mem().write_once(offset, &value),
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Bar::Io(io_bar) => io_bar.write(offset as u32, value),
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}
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}
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}
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/// Memory BAR
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#[derive(Debug)]
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pub struct MemoryBar {
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base: u64,
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size: u64,
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prefetchable: bool,
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address_length: AddrLen,
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io_memory: Once<IoMem>,
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}
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impl MemoryBar {
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/// Memory BAR bits type
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pub fn address_length(&self) -> AddrLen {
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self.address_length
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}
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/// Whether this bar is prefetchable, allowing the CPU to get the data
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/// in advance.
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pub fn prefetchable(&self) -> bool {
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self.prefetchable
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}
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/// Base address
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pub fn base(&self) -> u64 {
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self.base
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}
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/// Size of the memory
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pub fn size(&self) -> u64 {
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self.size
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}
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/// Grants I/O memory access
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pub fn io_mem(&self) -> &IoMem {
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self.io_memory.call_once(|| {
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// Use the `Uncacheable` cache policy for PCI device BARs by default.
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// Device-specific drivers may remap with different cache policies if needed.
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IoMem::acquire((self.base as usize)..((self.base + self.size) as usize)).unwrap()
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})
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}
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/// Creates a memory BAR structure.
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fn new(location: &PciDeviceLocation, index: u8, raw: u32) -> Result<Self> {
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debug_assert_eq!(raw & 1, 0);
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// Quoted sentences below are from "7.5.1.2.1 Base Address Registers (Offset 10h - 24h)" in
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// "PCI Express(R) Base Specification Revision 5.0 Version 1.0".
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// Check the "Memory Type" bitfield.
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let address_length = match (raw >> 1) & 3 {
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// "Base register is 32 bits wide and can be mapped anywhere in the 32 address bit
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// Memory Space."
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0b00 => AddrLen::Bits32,
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// "Base register is 64 bits wide and can be mapped anywhere in the 64 address bit
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// Memory Space."
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0b10 => AddrLen::Bits64,
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// "Reserved."
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_ => return Err(Error::InvalidArgs),
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};
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let offset = index as u16 * 4 + PciDeviceCommonCfgOffset::Bar0 as u16;
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// "Software saves the original value of the Base Address register, writes a value of all
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// 1's to the register, then reads it back."
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location.write32(offset, !0);
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let size_encoded = location.read32(offset);
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// "Unimplemented Base Address registers are hardwired to zero."
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if size_encoded == 0 {
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return Err(Error::InvalidArgs);
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}
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// "64-bit (memory) Base Address registers can be handled the same, except that the second
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// 32 bit register is considered an extension of the first (i.e., bits 63:32). Software
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// writes a value of all 1's to both registers, reads them back, and combines the result
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// into a 64-bit value."
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#[cfg_attr(target_arch = "loongarch64", expect(unused_variables))]
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let (raw64, size_encoded64) = match address_length {
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AddrLen::Bits32 => (raw as u64, size_encoded as u64 | ((u32::MAX as u64) << 32)),
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AddrLen::Bits64 => {
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let raw64 = raw as u64 | ((location.read32(offset + 4) as u64) << 32);
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location.write32(offset + 4, !0);
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let size_encoded64 =
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size_encoded as u64 | ((location.read32(offset + 4) as u64) << 32);
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(raw64, size_encoded64)
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}
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};
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// "Size calculation can be done from the 32 bit value read by first clearing encoding
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// information bits (bits 1:0 for I/O, bits 3:0 for memory), inverting all 32 bits (logical
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// NOT), then incrementing by 1."
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let size = !(size_encoded64 & !0xF) + 1;
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// Restore the original base address.
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#[cfg(not(target_arch = "loongarch64"))]
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let base = raw64 & !0xF;
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// In LoongArch, the BAR base address needs to be allocated manually.
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#[cfg(target_arch = "loongarch64")]
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let base = {
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use core::alloc::Layout;
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crate::arch::alloc_mmio(Layout::from_size_align(size as usize, size as usize).unwrap())
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.unwrap() as u64
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};
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match address_length {
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AddrLen::Bits32 => location.write32(offset, base as u32),
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AddrLen::Bits64 => {
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location.write32(offset, base as u32);
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location.write32(offset + 4, (base >> 32) as u32);
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}
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}
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// FIXME: At least on some x86 laptops, it has been found that the BIOS does not properly
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// initialize all PCI devices. Consequently, the base address reported by uninitialized PCI
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// devices is zero. To address this, we may need to add the ability to manually allocate
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// the base address.
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#[cfg(not(target_arch = "loongarch64"))]
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if base == 0 {
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log::info!(
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"presumably uninitialized BAR {} (Memory {:?}, size={}) of PCI device {:?}",
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index,
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address_length,
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size,
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location,
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);
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return Err(Error::InvalidArgs);
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}
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// Check the "Prefetchable" bit.
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let prefetchable = raw & 0b1000 != 0;
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Ok(MemoryBar {
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base,
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size,
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prefetchable,
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address_length,
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io_memory: Once::new(),
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})
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}
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}
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/// Whether this BAR is 64bit address or 32bit address
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#[derive(Debug, Copy, Clone, PartialEq, Eq)]
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pub enum AddrLen {
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/// 32 bits
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Bits32,
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/// 64 bits
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Bits64,
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}
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/// I/O port BAR.
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#[derive(Debug, Clone, Copy)]
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pub struct IoBar {
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base: u32,
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size: u32,
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}
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impl IoBar {
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/// Base port
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pub fn base(&self) -> u32 {
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self.base
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}
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/// Size of the port
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pub fn size(&self) -> u32 {
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self.size
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}
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/// Reads from port
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pub fn read<T: PortRead>(&self, offset: u32) -> Result<T> {
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// Check alignment
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if (self.base + offset) % size_of::<T>() as u32 != 0 {
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return Err(Error::InvalidArgs);
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}
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// Check overflow
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if self.size < size_of::<T>() as u32 || offset > self.size - size_of::<T>() as u32 {
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return Err(Error::InvalidArgs);
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}
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// TODO: Implement the read operation based on `IoPortAllocator`.
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Err(Error::IoError)
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}
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/// Writes to port
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pub fn write<T: PortWrite>(&self, offset: u32, _value: T) -> Result<()> {
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// Check alignment
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if (self.base + offset) % size_of::<T>() as u32 != 0 {
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return Err(Error::InvalidArgs);
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}
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// Check overflow
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if size_of::<T>() as u32 > self.size || offset > self.size - size_of::<T>() as u32 {
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return Err(Error::InvalidArgs);
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}
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// TODO: Implement the write operation based on `IoPortAllocator`.
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Err(Error::IoError)
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}
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/// Creates an I/O port BAR structure.
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fn new(location: &PciDeviceLocation, index: u8, raw: u32) -> Result<Self> {
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debug_assert_eq!(raw & 1, 1);
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let offset = index as u16 * 4 + PciDeviceCommonCfgOffset::Bar0 as u16;
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// "Software saves the original value of the Base Address register, writes a value of all
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// 1's to the register, then reads it back."
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location.write32(offset, !0);
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let size_encoded = location.read32(offset);
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// "Size calculation can be done from the 32 bit value read by first clearing encoding
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// information bits (bits 1:0 for I/O, bits 3:0 for memory), inverting all 32 bits (logical
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// NOT), then incrementing by 1."
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let size = !(size_encoded & !0x3) + 1;
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// Restore the original base address.
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let base = raw & !0x3;
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location.write32(offset, base);
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// FIXME: As with the memory BAR check, we assume that a zero base address means that the
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// BAR has not been initialized. In the future, we may need to add the ability to manually
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// allocate the base address.
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if base == 0 {
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log::info!(
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"presumably uninitialized BAR {} (I/O, size={}) of PCI device {:?}",
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index,
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size,
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location,
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);
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return Err(Error::InvalidArgs);
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}
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Ok(Self { base, size })
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}
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}
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