asterinas/kernel
Arthur Paulino 6a67807fd0 Implement `IdSet::iter_in`
This patch enables more expressive ways to slice and iterate over
the `Id`s in an `IdSet` with `IdSet::iter_in`, which takes an arbitrary
`IdSetSlicer`.

`IdSet::iter_in` efficiently slices out unintended inner parts and
then, within the remaining parts, skips inactive bits by using
`BitSlice::iter_ones` from the `bitvec` crate.

It also delivers several implementations of `IdSetSlicer` so OSTD
consumers can represent `Id` ranges ergonomically.

In the Asterinas kernel, `CpuSet::iter_in` enables a cleaner way to
define an interator that cycles over the CPUs.
2025-10-25 11:23:13 +08:00
..
comps Add RISC-V PLIC support 2025-10-24 16:28:41 +08:00
libs Implement fixed_point module to replace the usage of fixed crate 2025-10-13 12:34:01 +08:00
src Implement `IdSet::iter_in` 2025-10-25 11:23:13 +08:00
Cargo.toml Implement fixed_point module to replace the usage of fixed crate 2025-10-13 12:34:01 +08:00