Ruihan Li
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d73f1016a1
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Set softfloat targets for ARM/LoongArch/RISC-V
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2025-07-29 11:13:59 +08:00 |
王英泰
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0370f8fdf3
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Update the init of pci device for LoongArch
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2025-07-25 17:37:24 +08:00 |
|
王英泰
|
3391863312
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Add the partial support for interrupt in LoongArch
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2025-07-25 17:37:24 +08:00 |
|
王英泰
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7bf716162a
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Finish the arch section for LoongArch in OSTD
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2025-07-25 17:37:24 +08:00 |
|
王英泰
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8b8bbad996
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Add the pci section for LoongArch in OSTD and kernel
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2025-07-25 17:37:24 +08:00 |
|
王英泰
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369c8656ee
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Add the io section for LoongArch in OSTD
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2025-07-25 17:37:24 +08:00 |
|
王英泰
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7e9f418caa
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Add the qemu exit method for LoongArch in OSTD
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2025-07-25 17:37:24 +08:00 |
|
王英泰
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25bbdd991f
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Add the irq section for LoongArch in OSTD
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2025-07-25 17:37:24 +08:00 |
|
王英泰
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3824af8c89
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Add the trap section for LoongArch in OSTD
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2025-07-25 17:37:24 +08:00 |
|
王英泰
|
b5c3eb8be8
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Add the timer section of LoongArch in OSTD
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2025-07-25 17:37:24 +08:00 |
|
王英泰
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93c562f5d2
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Add the task section of LoongArch in OSTD
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2025-07-25 17:37:24 +08:00 |
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王英泰
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e4db73e1a0
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Add the mm section of LoongArch in OSTD
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2025-07-25 17:37:24 +08:00 |
|
王英泰
|
d3538ec6df
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Add the iommu section of LoongArch in OSTD
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2025-07-25 17:37:24 +08:00 |
|
王英泰
|
c81ed0162c
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Add the device section of LoongArch in OSTD
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2025-07-25 17:37:24 +08:00 |
|
王英泰
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91e7785915
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Add the cpu section of LoongArch in OSTD and kernel
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2025-07-25 17:37:24 +08:00 |
|
王英泰
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ce22374b50
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Add the boot section of LoongArch in OSTD
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2025-07-25 17:37:24 +08:00 |
|
王英泰
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b0b242edbc
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Add the temporary panic support for LoongArch
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2025-07-25 17:37:24 +08:00 |
Hsy-Intel
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24d56cfde7
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adjust feature enabling sequence and fix xsave size function
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2025-07-22 17:15:53 +08:00 |
Marsman1996
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b04d62ae71
|
Use official minicov and add unit test for coverage feature
|
2025-07-22 10:31:56 +08:00 |
YanWQ-monad
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79335b272f
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Add coverage support
Co-authored-by: Marsman1996 <lqliuyuwei@outlook.com>
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2025-07-22 10:31:56 +08:00 |
Zhang Junyang
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6a4d8d113f
|
Fix missing updates of page table `Entry::pte`
Co-authored-by: Xungan2 <2100012996@stu.pku.edu.cn>
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2025-07-21 13:42:38 +08:00 |
|
Ruihan Li
|
bc7515389b
|
Create a RISC-V boot code and data section
|
2025-07-21 10:01:02 +08:00 |
|
Ruihan Li
|
e475009fe7
|
Optimize the x86 binary size
|
2025-07-21 10:01:02 +08:00 |
jiangjianfeng
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424fcda239
|
Use iret instead of sysret if the context is not clean
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2025-07-20 22:22:20 +08:00 |
Qingsong Chen
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6cd53fbb8a
|
Refactor FPU context using pre_schedule_handler
|
2025-07-18 11:40:16 +08:00 |
|
Ruihan Li
|
cdd7950d2e
|
Remove some variants in `ostd::Error`
|
2025-07-15 23:05:30 +08:00 |
|
Ruihan Li
|
e5c5bc7992
|
Clarify safety comments in `dyn_cpu_local.rs`
|
2025-07-11 14:10:46 +08:00 |
|
jiangjianfeng
|
665de6bd35
|
Make RISC-V code compile under new exception APIs
|
2025-07-09 10:49:43 +08:00 |
|
jiangjianfeng
|
7f3ca86467
|
Refactor x86 exception related code
|
2025-07-09 10:49:43 +08:00 |
|
Ruihan Li
|
801ab865b7
|
Make paths of `TrapFrame` unique
|
2025-07-05 18:19:26 +08:00 |
|
Ruihan Li
|
0fce977b40
|
Clean up `trapframe` items
|
2025-07-05 18:19:26 +08:00 |
|
Ruihan Li
|
6f2725419f
|
Always clear the need-preempt flag
|
2025-07-04 19:14:31 +08:00 |
Wang Siyuan
|
a13297ae4c
|
Add fields in `/proc/*/stat` and `/proc/*/status`
|
2025-07-02 20:13:47 +08:00 |
|
Ruihan Li
|
ac0d92d878
|
Fix minor issues of the CPU extension module
|
2025-07-02 07:54:40 +08:00 |
|
jiangjianfeng
|
49ef0e9f7a
|
Change the documentation website of OSTD
|
2025-07-01 17:07:28 +08:00 |
|
jiangjianfeng
|
2e09957ef9
|
Fix documentation check errors
|
2025-07-01 17:07:28 +08:00 |
|
jiangjianfeng
|
dc26e18310
|
Depend on int-to-c-enum instead of num crate
|
2025-06-30 15:48:40 +08:00 |
|
Zhang Junyang
|
c7f489b726
|
Bump version to 0.15.2
|
2025-06-26 08:16:22 +08:00 |
|
Ruihan Li
|
780b35848e
|
Remove `SameSizeAs`
|
2025-06-25 15:57:23 +08:00 |
|
Ruihan Li
|
59e7d268d7
|
Tidy up the `PageTableEntryTrait` comments
|
2025-06-25 15:57:23 +08:00 |
|
Ruihan Li
|
35e0918bce
|
Don't race between enabling IRQs and halting CPU
|
2025-06-23 22:53:35 +08:00 |
|
Ruihan Li
|
b96c8f9ed2
|
Make `ostd::trap::irq` public
|
2025-06-23 22:53:35 +08:00 |
|
Ruihan Li
|
a1accf4304
|
Do some miscellaneous page table cleanups
|
2025-06-22 16:46:07 +08:00 |
|
Ruihan Li
|
a3c5ab8cb4
|
Move virtio-mmio bus outside OSTD
|
2025-06-19 15:10:42 +08:00 |
|
Ruihan Li
|
238b89da46
|
Create `IrqChip` abstraction
|
2025-06-19 15:10:42 +08:00 |
|
Ruihan Li
|
76377f701b
|
Restrict some module visibility
|
2025-06-19 15:10:42 +08:00 |
Philipp Schuster
|
7a398167cf
|
ostd: update multiboot2 + use constant
|
2025-06-16 16:10:54 +08:00 |
|
Wang Siyuan
|
d5b12532a8
|
Require `T: Send` for `CpuLocal<T, S>`
|
2025-06-16 12:09:13 +08:00 |
|
Hsy-Intel
|
c2a49bca7c
|
Temporary fix for TDX MMIO assert issue
|
2025-06-13 10:31:25 +08:00 |
|
Wang Siyuan
|
614ac85bd4
|
Bump the project version
|
2025-06-12 22:35:54 +08:00 |