3f3838d3a3
Support reboot syscall
2025-11-28 11:32:16 +08:00
22adc64577
Support hypervisor CPUID
2025-11-28 11:32:16 +08:00
2892b8a977
Use `size_of` in preludes
2025-11-26 17:35:42 +08:00
7564314de3
Fix a misuse of `CommonSizeClass::from_size` in CPU local allocator
2025-11-26 16:41:04 +08:00
70eda539df
Refactor IoMem acquisition to use appropriate cache policies across multiple components
2025-11-25 10:24:54 +08:00
fb1cab9951
Enhance IoMem to support configurable cache policies
2025-11-25 10:24:54 +08:00
22dffcf8c2
Extend Cache Policies for the x86 Architecture
2025-11-25 10:24:54 +08:00
8096249765
Add a lock before capturing coverage
2025-11-20 14:36:30 +08:00
668876aeee
Check the existence of i8042 and RTC CMOS
2025-11-19 15:39:49 +08:00
bbe0e3f3bb
Reimplement `RtcCmos`
2025-11-19 15:39:49 +08:00
902106eb2e
Allow SBI system_reset to fail
2025-11-18 14:46:16 +08:00
314fbe285a
Check size and alignment for untyped metadata
2025-11-17 15:26:45 +08:00
9c8a8f8df9
Remove `PageProperty::new_absent`
2025-11-16 18:18:26 +08:00
963771fd32
Skip management hart while enumerating usable harts
2025-11-16 11:23:46 +08:00
69dc2479db
Rename initialization methods
2025-11-16 11:09:08 +08:00
19b1fe36c5
Remove outdated safety comments
2025-11-16 11:09:08 +08:00
e0dd647756
Remove `TIMER_IRQ_NUM` for RISC-V
2025-11-14 10:14:03 +08:00
b86aeffd53
Correct some hart ID usage
2025-11-14 10:14:03 +08:00
8148072984
Upgrade the `riscv` crate to fix the ssoft handling
...
3c61863630
2025-11-14 10:14:03 +08:00
7e7f6741c6
Setup RISC-V AP timer
2025-11-14 10:14:03 +08:00
7d21144da6
Add RISC-V IPI
2025-11-14 10:14:03 +08:00
73c0f34947
Remove `Arc` guards of locks that have no users
2025-11-13 23:32:36 +08:00
b69feb97c9
Rename some `init` to `init_on_cpu`
2025-11-12 17:57:36 +08:00
14aee3d5cc
Unify and fix RISC-V symbol names
2025-11-12 17:39:04 +08:00
121da78aa2
Revise names and comments in `ostd::arch`
2025-11-12 14:43:14 +08:00
d447fe0ca8
Update APICs' MMIO region sizes
2025-11-05 22:48:40 +08:00
3b4569e14d
Add RISC-V SMP boot entrypoint
2025-11-02 21:23:32 +08:00
431b6fdff7
Make riscv64's `PageTableEntry::set_prop` recognize A/D bit
2025-10-31 08:52:34 +08:00
9c70ac0f0a
Mark `sync_dma_range` as `unsafe`
2025-10-30 17:04:45 +08:00
d487e42b7c
Reunify the style of defining `arch` modules
2025-10-30 17:04:45 +08:00
6af524b451
Support RISC-V Sv39 Paging mode
2025-10-30 14:51:37 +08:00
577d8294d0
Use exception table to recover in RISC-V page fault handler
2025-10-30 11:27:08 +08:00
79992c66de
Implement fallible memory operations on RISC-V platform
2025-10-30 11:27:08 +08:00
629b053ea8
Make exception table arch-agnostic
2025-10-30 11:27:08 +08:00
bfcb1d2c00
Implement `DmaStream::sync` on RISC-V platforms
2025-10-30 10:47:53 +08:00
39a541fdeb
Add RISC-V FPU support
2025-10-29 13:24:30 +08:00
32581caa7a
Skip management hart when detecting available extensions
2025-10-28 09:32:12 +08:00
4996146a24
Add `.type` and `.size` directives
2025-10-28 09:21:44 +08:00
e61c8ce56a
Unify styles of assembly code
2025-10-28 09:21:44 +08:00
a6b01501ac
Load local addresses and define constants
2025-10-28 09:21:44 +08:00
0b597d84a0
Use `IoMem<Sensitive>` in local APIC
2025-10-28 09:12:02 +08:00
d42208b591
Use `IoMem<Sensitive>` in I/O APIC
2025-10-28 09:12:02 +08:00
dd8de9f381
Handle kernel page fault on RISC-V platforms
2025-10-27 11:25:59 +08:00
1e183825d3
Refactor RISC-V exception-related code
2025-10-27 11:25:59 +08:00
6a67807fd0
Implement `IdSet::iter_in`
...
This patch enables more expressive ways to slice and iterate over
the `Id`s in an `IdSet` with `IdSet::iter_in`, which takes an arbitrary
`IdSetSlicer`.
`IdSet::iter_in` efficiently slices out unintended inner parts and
then, within the remaining parts, skips inactive bits by using
`BitSlice::iter_ones` from the `bitvec` crate.
It also delivers several implementations of `IdSetSlicer` so OSTD
consumers can represent `Id` ranges ergonomically.
In the Asterinas kernel, `CpuSet::iter_in` enables a cleaner way to
define an interator that cycles over the CPUs.
2025-10-25 11:23:13 +08:00
8251d48bf2
Add RISC-V PLIC support
2025-10-24 16:28:41 +08:00
752f040368
Implement security-sensitive IoMem
2025-10-24 16:28:41 +08:00
68721b2365
Activate kernel page table earlier on BSP
2025-10-24 16:28:41 +08:00
72dbaa4b38
Use absolute time when setting up timer interrupt using SBI
2025-10-24 11:32:28 +08:00
c44e45ea78
Add the `IdSet<I>` utility type
2025-10-22 14:29:52 +08:00
d9a74c6cfc
Remove unit tests that instantiate invalid CpuId
2025-10-22 14:29:52 +08:00
6942bc6643
Extract CpuId into a sub-module of the `cpu` module
...
This prevents creating invalid instances of `CpuId` within the `cpu`
module by using `CpuId(raw_id)` directly. Another benefit is to
make the `cpu` module more modular, which is good for readability
and maintainability.
2025-10-22 14:29:52 +08:00
23f14df21f
[sched] Fix the missing of preemption check in RISC-V & loongarch
2025-10-20 11:17:24 +08:00
384e5bc70d
Fix an off-by-one bug in the trap frame
2025-10-16 22:28:29 +09:00
fe7dc1f83e
Adjust some symbol names
2025-10-16 22:28:29 +09:00
3673049620
Resolve minor issues in `ostd::src::arch`
2025-10-16 21:46:40 +09:00
bc6ef5231b
Reorangize `ostd::arch::irq`
2025-10-16 21:46:40 +09:00
c2adcf9944
Support accessing user spaces of other processes
2025-10-15 16:34:32 +08:00
51eb74250e
Fix several MMIO/PIO allocation bugs
2025-10-14 00:22:38 +09:00
7d86d326a3
Adjust the MMIO area alignment
2025-10-14 00:22:38 +09:00
fa59b8be2b
Adjust visibility marks in `ostd::io`
2025-10-14 00:22:38 +09:00
50eaffc731
Remove `RwLock.downgrade` due to potential contention with `RwLock.read`
2025-09-30 17:34:22 +08:00
e7ef7d5947
ostd: remove dead buddy_system_allocator dependency
...
cc https://github.com/asterinas/asterinas/issues/2480#issuecomment-3349718870
2025-09-30 11:44:24 +08:00
36a38c3f04
Bump `rand` version to 0.9.2
2025-09-30 11:36:37 +08:00
b76f11f7b3
Add an `irq_num` parameter to `bottom_half_handler` for IRQ counting statistics.
2025-09-27 21:02:23 +08:00
fc114019d6
Recompile bzImage if payload is changed
2025-09-26 15:35:14 +08:00
472edcf795
Clean up unnecessary features
2025-09-24 15:41:07 +08:00
48c7c37f50
Bump version to 0.16.1
2025-09-24 13:55:48 +08:00
a8070a62b6
Extract platform-specific code from ostd into PCI component
2025-09-21 10:32:23 +08:00
bb15d4591a
Extract `PciDeviceLocation` in ostd into PCI component
2025-09-21 10:32:23 +08:00
bb4c532b4e
Use custom `PciDeviceLocation` in x86 iommu
2025-09-21 10:32:23 +08:00
67050f3a8f
Change the position of debug log in `IoMemAllocator::acquire`
2025-09-21 10:32:23 +08:00
d60e2e2a6b
Align cap_ptr in PCI
2025-09-21 10:32:23 +08:00
48376efa52
Extract MSIX in ostd into PCI component
2025-09-21 10:32:23 +08:00
1a86bd2471
Move PCI bus in OSTD into PCI component
2025-09-21 10:32:23 +08:00
391f11f1aa
Make per-CPU callbacks explicit
2025-09-20 11:50:50 +08:00
011e2398af
Remove broken no-APIC support
2025-09-20 11:50:50 +08:00
421f36cc26
Make timer callbacks arch-agnostic
2025-09-20 11:50:50 +08:00
4b87dab86e
Unify CPU arch-specific logic that determines if the kernel is interrupted
2025-09-19 15:05:50 +08:00
bd0ab0b8aa
Fix an outdated example in Rust doc
2025-09-19 15:05:50 +08:00
ee21f2bdb6
Refactor OSTD irq module for improved clarity
2025-09-19 15:05:50 +08:00
3501ec72ee
Move disabled IRQ guards to a submodule
2025-09-19 15:05:50 +08:00
c485d512f6
Rename ostd::trap to ostd::irq
2025-09-19 15:05:50 +08:00
2e46edb68d
Register some timer callbacks on all CPUs
2025-09-19 14:40:33 +08:00
561ee206f5
Make metadata repurposing sound
2025-09-19 11:27:14 +08:00
c7429a7a5c
Allow to repurpose `?Sized` metadata
2025-09-19 11:27:14 +08:00
bf6efbabc7
Remove unused `has_guard_page` boolean
2025-09-14 22:42:48 +08:00
44145cdb53
Set CR0.WP/NE/MP explicitly to fix AP behavior
2025-09-12 08:43:35 +08:00
75ca7e0377
Add the `arch::cpu::extension` module
2025-09-10 12:10:40 +08:00
9de70e38de
Add the `arch::cpu::cpuid` module
2025-09-10 12:10:40 +08:00
652657fba5
Drop duplicate public re-exports
2025-09-10 12:10:40 +08:00
2796c8d1ad
Add unit tests for the newly implemented methods related to `IoMem`
2025-09-05 10:47:43 +08:00
877581f1a6
Add OSTD support for mapping `IoMem` in userspace
2025-09-05 10:47:43 +08:00
5a38c61c49
Ensure that OSTD users cannot modify the `PrivilegedPageFlags` in `PageProperty`
2025-09-05 10:47:43 +08:00
e11227c8da
Move the `AVAIL1` flag from `PageFlags` to `PrivilegedPageFlags` in `PageProperty`
2025-09-05 10:47:43 +08:00
3b606f5b6c
Use `size_of`/`align_of` in the prelude
2025-09-04 09:26:56 +08:00
45b5bd39f1
Disable I/O APIC entries in initialization
2025-09-02 18:03:24 +08:00
4e2bdc65de
Refactor implicit `Arc` APIs for DMA
2025-09-02 17:53:55 +08:00
a6520880ab
Unify memory object slicing
2025-09-02 17:53:55 +08:00
eb69aa4fb9
Unify address and size APIs for memory objects
2025-09-02 17:53:55 +08:00
Chen Chengjun
Ruihan Li
Zhang Junyang
Zhe Tang
Zejun Zhao
Tao Su
Arthur Paulino
Tate, Hongliang Tian
Yuke Peng
Wang Siyuan
Ruize Tang
zjp
Yang Zhichao
Zhe Tang