qiurui
/
asterinas
mirror of https://github.com/asterinas/asterinas.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity
2,716 Commits 1 Branch 35 Tags 60 MiB
Commit Graph

516 Commits

Author SHA1 Message Date
Ruihan Li 75ca7e0377 Add the `arch::cpu::extension` module 2025-09-10 12:10:40 +08:00
Ruihan Li 9de70e38de Add the `arch::cpu::cpuid` module 2025-09-10 12:10:40 +08:00
Ruihan Li 652657fba5 Drop duplicate public re-exports 2025-09-10 12:10:40 +08:00
Zhe Tang 2796c8d1ad Add unit tests for the newly implemented methods related to `IoMem` 2025-09-05 10:47:43 +08:00
Zhe Tang 877581f1a6 Add OSTD support for mapping `IoMem` in userspace 2025-09-05 10:47:43 +08:00
Zhe Tang 5a38c61c49 Ensure that OSTD users cannot modify the `PrivilegedPageFlags` in `PageProperty` 2025-09-05 10:47:43 +08:00
Zhe Tang e11227c8da Move the `AVAIL1` flag from `PageFlags` to `PrivilegedPageFlags` in `PageProperty` 2025-09-05 10:47:43 +08:00
Ruihan Li 3b606f5b6c Use `size_of`/`align_of` in the prelude 2025-09-04 09:26:56 +08:00
Ruihan Li 45b5bd39f1 Disable I/O APIC entries in initialization 2025-09-02 18:03:24 +08:00
Zhang Junyang 4e2bdc65de Refactor implicit `Arc` APIs for DMA 2025-09-02 17:53:55 +08:00
Zhang Junyang a6520880ab Unify memory object slicing 2025-09-02 17:53:55 +08:00
Zhang Junyang eb69aa4fb9 Unify address and size APIs for memory objects 2025-09-02 17:53:55 +08:00
Arthur Paulino f56d2f3bad `context.rs` enhancements 
* Improve the phrasing of some docstrings and comments
* Add warning comments about attempts to validate memory addresses
  at reader/writer instantiation time
* Create the `reader_writer` method for ergonomically instantiate
  a reader/writer pair covering the same memory region. This method
  is also slightly more efficient than calling `reader` and `writer`
  separately
* Clean up `check_vaddr` for clarity and rename it to `check_vaddr_lowerbound`
  for explicity
* Include the data length check before calling `check_vaddr_lowerbound`
  in `atomic_load` and `atomic_fetch_update` for further consistency
  with the delayed buffer validation
 2025-09-01 11:16:37 +08:00
Zejun Zhao bf25806fca Add an explicit end of call stack for x86_64 and loongarch64 2025-08-29 17:10:48 +08:00
Zejun Zhao fc61f4d1b8 Use `IrqLine` abstraction for RISC-V timer interrupt 2025-08-29 10:49:48 +08:00
Zejun Zhao aeaf103166 Add an explicit end of call stack for x86_64 2025-08-28 17:26:23 +08:00
Zejun Zhao 920ec7f521 Enable RISC-V stack unwinding on panic 2025-08-28 17:26:23 +08:00
Ruihan Li 924d87398a Introduce `first_context_switch` 2025-08-20 20:12:38 +08:00
Ruihan Li 2d3cfb53e0 Swap `context_switch` arguments 2025-08-20 20:12:38 +08:00
Ruihan Li 85f17ff159 Replace `parse_u32` with `u32::from_str_radix` 2025-08-20 13:19:50 +08:00
Ruihan Li 6b6c64c591 Rename `atomic_update` to `atomic_fetch_update` 2025-08-20 13:17:57 +08:00
Arthur Paulino a73f210c7a Make `wake_robust_futex` atomic 
Replace `VmWriter::atomic_update` with `VmWriter::atomic_compare_exchange`,
which takes the old value for comparison and new value instead of a
closure to compute it. This version has one less unsafe call.

Then use `atomic_compare_exchange` to reimplement the looping logic
of `wake_robust_futex` and make it atomic.
 2025-08-19 19:22:12 +08:00
Chen Chengjun fc5a12356a Fix LOONGARCH clippy warnings 2025-08-19 19:20:54 +08:00
Chen Chengjun 9507475102 Fix RISCV clippy warnings 2025-08-19 19:20:54 +08:00
Zhang Junyang 1452aab69c Optimize the space for `TlbFlushOp`s 2025-08-16 22:09:29 +08:00
Zhang Junyang d0b98130cf Don't use `map` to return values 2025-08-16 22:09:29 +08:00
Ruihan Li e4fafb13b1 Add atomic operations for VM readers/writers 2025-08-14 11:59:05 +08:00
Ruihan Li 6e6465942c Clean up comments and visibility 2025-08-12 19:19:34 +08:00
Ruihan Li bb279e6313 Clarify who loads the user TLS pointer 2025-08-12 19:19:34 +08:00
Ruihan Li 086a80c05f Drop unsound TLS methods from `Task` 2025-08-12 19:19:34 +08:00
Ruihan Li 923982c2e5 Remove `user_ctx` from `Task` 2025-08-12 19:19:34 +08:00
Ruihan Li 695bb1a0a7 Synchronize `{pci,io}.rs` between architectures 2025-08-12 14:00:28 +08:00
Tate, Hongliang Tian d481b10f63 Polish the Rust doc of OSTD's logger module 2025-08-12 10:55:24 +08:00
Zejun Zhao 597b0b5f25 Disable kernel traps before going to userspace 2025-08-10 17:09:22 +08:00
Ruihan Li cdd28787ed Replace `write_vals` by `fill_zeros` in `VmIo` 2025-08-10 16:40:11 +08:00
Ruihan Li 2700d88bef Provide efficient `VmIo` with VM readers/writers 2025-08-10 16:40:11 +08:00
Ruihan Li 894b942a79 Avoid all `Pod::new_uninit`s in OSTD 2025-08-10 16:40:11 +08:00
Ruihan Li 275fd21650 Retire missing `ptr::sub` in `mm/io.rs` 2025-08-10 16:40:11 +08:00
Ruihan Li aa7aca3dde Add `VmWriter::fill_zeros` 2025-08-10 16:40:11 +08:00
Ruihan Li d99c18d0be Remove `VmWriter::fill` 2025-08-10 16:40:11 +08:00
Ruihan Li db79aa2453 Remove `VmReader::collect` 2025-08-10 16:40:11 +08:00
Ruihan Li 6e597b40af Remove unsafe code in `mm/test.rs` 2025-08-10 16:40:11 +08:00
Ruihan Li 05990e743e Reimplement PCI BAR detection methods 2025-08-08 09:02:34 +08:00
Zejun Zhao b20d8461fd Fix discovery and access of PCIe (MMIO) configuration space 2025-08-06 02:11:21 +08:00
Zejun Zhao 19f7eea68b Don't assume SVPBMT's existence 2025-08-06 02:11:21 +08:00
Zejun Zhao 26b7428c8e Construct `IoMemAllocator` on RISC-V platforms 2025-08-06 02:11:21 +08:00
Wang Siyuan ffdfd01925 Refactor the core scheduling logic in OSTD 2025-08-05 13:37:01 +08:00
Wang Siyuan 3ebb5a25b2 Refactor task schedulers to conform with the new semantics 2025-08-05 13:37:01 +08:00
Tate, Hongliang Tian 659f079c2d Revise the doc of OSTD's scheduling module 2025-07-29 21:58:23 +08:00
王英泰 0370f8fdf3 Update the init of pci device for LoongArch 2025-07-25 17:37:24 +08:00