Zhang Junyang
|
d22277a3e6
|
Allow manually dispatching publishing workflows
|
2024-08-24 22:18:22 +08:00 |
|
Zhang Junyang
|
34b3aac2e3
|
Bump and publish `ostd-test` and `ostd-macros`
|
2024-08-24 17:18:24 +08:00 |
|
Zhang Junyang
|
e50b05d1ee
|
Bump version to 0.8.0
|
2024-08-23 23:37:50 +08:00 |
|
Zhang Junyang
|
be3492d7f0
|
Extract the OSTD test runner as a kernel
|
2024-08-23 23:37:50 +08:00 |
Yuke Peng
|
c2a8342752
|
Add lmbench fifo latency test
|
2024-08-23 19:56:36 +08:00 |
|
Yuke Peng
|
30726ad880
|
Add lmbench unix connect latency test
|
2024-08-23 19:55:25 +08:00 |
|
Yuke Peng
|
837c7bebb6
|
Add lmbench lmdd test
|
2024-08-22 12:51:42 +08:00 |
Cautreoxit
|
1833f8047e
|
Modify Dockerfile and bump the version file
|
2024-08-22 09:55:19 +08:00 |
Yuke Peng
|
dee0956921
|
Add lmbench file locking latency test
|
2024-08-18 23:20:57 +08:00 |
|
Yuke Peng
|
8ce86e4d98
|
Add lmbench signal protection test
|
2024-08-18 23:20:57 +08:00 |
|
Yuke Peng
|
21255655c0
|
Add lmbench mmap latency test
|
2024-08-18 23:20:57 +08:00 |
|
Yuke Peng
|
9e2956b4a3
|
Add lmbench mmap bandwidth test
|
2024-08-18 23:20:57 +08:00 |
|
Yuke Peng
|
6430ef1841
|
Add LMbench lat_sem test
|
2024-08-18 16:37:39 +08:00 |
Chen Chengjun
|
803f059493
|
Add page fault lmbench
|
2024-08-17 18:07:09 +08:00 |
Shaowei Song
|
720b952996
|
Add lmbench fs tests
|
2024-08-15 23:07:33 +08:00 |
Hsy-Intel
|
b6e4b36a51
|
Change Asterinas TDX CI scheduled time
|
2024-08-14 10:18:32 +08:00 |
|
Hsy-Intel
|
20d5212910
|
Use nightly toolchain for OSDK test
|
2024-08-13 20:27:21 +08:00 |
|
Hsy-Intel
|
e10eab6576
|
Add TDX CI for OSDK
|
2024-08-13 20:27:21 +08:00 |
|
Yuke Peng
|
6f8978193c
|
Add benchmarks to workflow
|
2024-08-02 23:03:06 +08:00 |
Fabing Li
|
c43c07c9fb
|
Enhance UI and functionality for benchmark
|
2024-08-02 15:55:36 +08:00 |
|
Shaowei Song
|
6847181553
|
Enable lmbench-write&lmbench-read in benchmark ci
|
2024-07-30 20:57:37 +08:00 |
|
Zhang Junyang
|
bdabea09c2
|
Add SMP boot options
|
2024-07-30 10:24:09 +08:00 |
|
Yuke Peng
|
6ab3373f9b
|
Add pipe benchmarks to workflow
|
2024-07-29 22:16:25 +08:00 |
|
Zhang Junyang
|
bb3f8f9c52
|
Cover debug assertions in intergration tests
|
2024-07-25 13:20:09 +08:00 |
|
Yuke Peng
|
34f6108f56
|
Add benchmarks to workflow
|
2024-07-18 18:20:28 +08:00 |
Jianfeng Jiang
|
3462da986e
|
Remove publish api docs CI
|
2024-07-18 18:18:05 +08:00 |
|
Jianfeng Jiang
|
f86583dbce
|
Make essential changes for publishing OSTD
|
2024-07-18 18:18:05 +08:00 |
Qingsong Chen
|
4ae59a8f2e
|
Add integration test with kvm enabled
|
2024-07-16 21:20:10 +08:00 |
|
Hsy-Intel
|
6ff6db2167
|
Add TDX CI
|
2024-07-09 19:43:55 +08:00 |
|
Yuke Peng
|
64c17f3853
|
Remove home-brewed getpid benchmark
|
2024-07-08 18:21:08 +08:00 |
|
Yuke Peng
|
b12a5d6770
|
Add lmbench scripts
|
2024-07-08 18:21:08 +08:00 |
|
Shaowei Song
|
02bf6a9b47
|
Bump version to 0.6.2
|
2024-07-08 17:13:16 +08:00 |
|
Yuke Peng
|
defb563541
|
Bump version to 0.6.1
|
2024-07-08 15:26:29 +08:00 |
|
Fabing Li
|
990bd846cd
|
Enhance the stability of Asterinas compiling
|
2024-07-05 20:03:10 +08:00 |
|
Jianfeng Jiang
|
f51e002bb2
|
Bump version to 0.6.0
|
2024-06-28 21:20:08 +08:00 |
|
Fabing Li
|
f675552c5a
|
Rename regression to test
|
2024-06-28 20:33:21 +08:00 |
Tate, Hongliang Tian
|
e8a3e00dec
|
Update the names of Github workflows for consistency
|
2024-06-27 21:56:55 +08:00 |
|
Jianfeng Jiang
|
59350a8578
|
Rename aster-frame to ostd
|
2024-06-27 15:45:49 +08:00 |
|
Jianfeng Jiang
|
fb59fa7a55
|
Use matrix to simplify osdk test
|
2024-06-27 15:44:29 +08:00 |
|
Fabing Li
|
36841c50d4
|
Add benchmark CI for sysbench and getpid
|
2024-06-26 20:58:12 +08:00 |
|
Fabing Li
|
4700ab71bc
|
Bumped Asterinas & OSDK version to 0.5.1
|
2024-06-26 19:12:17 +08:00 |
|
Jianfeng Jiang
|
9647e09863
|
Add CI to tag main branch when VERSION changes
|
2024-06-25 11:49:49 +08:00 |
Ruihan Li
|
284b8c28c8
|
Avoid long lines in `Makefile`s and workflows
|
2024-06-24 19:22:48 +08:00 |
|
Fabing Li
|
c75a3732b9
|
Add issue templates
|
2024-06-21 19:57:47 +08:00 |
|
Zhang Junyang
|
d2eb9e16ff
|
[chore] Bump to 0.5.0
|
2024-06-21 10:57:08 +08:00 |
|
Hsy-Intel
|
8c39309381
|
Add TDX dockerfile & CI for asterinas
|
2024-06-20 16:08:23 +08:00 |
|
Jianfeng Jiang
|
a997785166
|
Add CI to update API documentations
|
2024-06-18 15:15:08 +08:00 |
|
Hsy-Intel
|
bd1d076e8c
|
Update CI for website
|
2024-06-18 12:45:45 +08:00 |
|
Hsy-Intel
|
6014ecfc0f
|
Add tdx guide for osdk
|
2024-06-14 19:49:03 +08:00 |
Anmin Liu
|
7694c5a6b8
|
Convert vsock ci to manual trigger
|
2024-06-11 17:51:36 +08:00 |