Set softfloat targets for ARM/LoongArch/RISC-V

This commit is contained in:
Ruihan Li 2025-07-20 19:52:27 +08:00 committed by Tate, Hongliang Tian
parent 8a801676ab
commit d73f1016a1
4 changed files with 17 additions and 8 deletions

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@ -68,10 +68,10 @@ fixed = "1.28.0"
[target.x86_64-unknown-none.dependencies] [target.x86_64-unknown-none.dependencies]
tdx-guest = { version = "0.2.1", optional = true } tdx-guest = { version = "0.2.1", optional = true }
[target.riscv64gc-unknown-none-elf.dependencies] [target.riscv64imac-unknown-none-elf.dependencies]
riscv = { version = "0.11.1", features = ["s-mode"] } riscv = { version = "0.11.1", features = ["s-mode"] }
[target.loongarch64-unknown-none.dependencies] [target.loongarch64-unknown-none-softfloat.dependencies]
loongArch64 = "0.2.5" loongArch64 = "0.2.5"
[features] [features]

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@ -12,7 +12,7 @@ component = { path = "../../libs/comp-sys/component" }
log = "0.4" log = "0.4"
spin = "0.9.4" spin = "0.9.4"
[target.riscv64gc-unknown-none-elf.dependencies] [target.riscv64imac-unknown-none-elf.dependencies]
chrono = { version = "0.4.38", default-features = false } chrono = { version = "0.4.38", default-features = false }
[lints] [lints]

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@ -46,10 +46,10 @@ impl Arch {
/// Get the target triple for the architecture. /// Get the target triple for the architecture.
pub fn triple(&self) -> &'static str { pub fn triple(&self) -> &'static str {
match self { match self {
Arch::Aarch64 => "aarch64-unknown-none", Arch::Aarch64 => "aarch64-unknown-none-softfloat",
Arch::RiscV64 => "riscv64gc-unknown-none-elf", Arch::RiscV64 => "riscv64imac-unknown-none-elf",
Arch::X86_64 => "x86_64-unknown-none", Arch::X86_64 => "x86_64-unknown-none",
Arch::LoongArch64 => "loongarch64-unknown-none", Arch::LoongArch64 => "loongarch64-unknown-none-softfloat",
} }
} }

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@ -39,6 +39,15 @@ bitvec = { version = "1.0", default-features = false, features = ["alloc"] }
minicov = { version = "0.3", optional = true } minicov = { version = "0.3", optional = true }
# The targets are chosen to prevent the generated machine code from using any
# vector or floating-point registers.
#
# - `x86_64-unknown-none` satisfies this property, as explained by [the
# official documentation](https://doc.rust-lang.org/rustc/platform-support/x86_64-unknown-none.html).
# - `riscv64imac-unknown-none-elf` denotes a RISC-V ISA with only basic
# extensions (`imac`) and no floating-point-related extensions.
# - `loongarch64-unknown-none-softfloat` is rather self-explaining.
[target.x86_64-unknown-none.dependencies] [target.x86_64-unknown-none.dependencies]
x86_64 = "0.14.13" x86_64 = "0.14.13"
x86 = "0.52.0" x86 = "0.52.0"
@ -52,13 +61,13 @@ iced-x86 = { version = "1.21.0", default-features = false, features = [
tdx-guest = { version = "0.2.1", optional = true } tdx-guest = { version = "0.2.1", optional = true }
unwinding = { version = "=0.2.5", default-features = false, features = ["fde-gnu-eh-frame-hdr", "hide-trace", "panic", "personality", "unwinder"] } unwinding = { version = "=0.2.5", default-features = false, features = ["fde-gnu-eh-frame-hdr", "hide-trace", "panic", "personality", "unwinder"] }
[target.riscv64gc-unknown-none-elf.dependencies] [target.riscv64imac-unknown-none-elf.dependencies]
riscv = { version = "0.11.1", features = ["s-mode"] } riscv = { version = "0.11.1", features = ["s-mode"] }
sbi-rt = "0.0.3" sbi-rt = "0.0.3"
fdt = { version = "0.1.5", features = ["pretty-printing"] } fdt = { version = "0.1.5", features = ["pretty-printing"] }
unwinding = { version = "=0.2.5", default-features = false, features = ["fde-gnu-eh-frame-hdr", "hide-trace", "panic", "personality", "unwinder"] } unwinding = { version = "=0.2.5", default-features = false, features = ["fde-gnu-eh-frame-hdr", "hide-trace", "panic", "personality", "unwinder"] }
[target.loongarch64-unknown-none.dependencies] [target.loongarch64-unknown-none-softfloat.dependencies]
loongArch64 = "0.2.5" loongArch64 = "0.2.5"
fdt = { version = "0.1.5", features = ["pretty-printing"] } fdt = { version = "0.1.5", features = ["pretty-printing"] }