From 5630fa8b3693e01222ac12e1331cebf2f5609df1 Mon Sep 17 00:00:00 2001
From: Zejun Zhao <jelly.zhao.42@gmail.com>
Date: Tue, 25 Mar 2025 23:43:01 +0800
Subject: [PATCH] Disable RISC-V FPU by default

---
 ostd/src/arch/riscv/mod.rs | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/ostd/src/arch/riscv/mod.rs b/ostd/src/arch/riscv/mod.rs
index a030b5649..a6477a782 100644
--- a/ostd/src/arch/riscv/mod.rs
+++ b/ostd/src/arch/riscv/mod.rs
@@ -64,6 +64,8 @@ pub fn read_random() -> Option<u64> {
 
 pub(crate) fn enable_cpu_features() {
     unsafe {
-        riscv::register::sstatus::set_fs(riscv::register::sstatus::FS::Clean);
+        // We adopt a lazy approach to enable the floating-point unit; it's not
+        // enabled before the first FPU trap.
+        riscv::register::sstatus::set_fs(riscv::register::sstatus::FS::Off);
     }
 }