[sched] Fix the missing of preemption check in RISC-V & loongarch

ostd/src/arch/loongarch/cpu/context.rs

@@ -149,6 +149,7 @@ impl UserContextApiInternal for UserContext {
         F: FnMut() -> bool,
     {
         let ret = loop {
+            crate::task::scheduler::might_preempt();
             self.user_context.run();
 
             let cause = loongArch64::register::estat::read().cause();

ostd/src/arch/riscv/cpu/context.rs

@@ -144,7 +144,9 @@ impl UserContextApiInternal for UserContext {
         F: FnMut() -> bool,
     {
         let ret = loop {
+            crate::task::scheduler::might_preempt();
             self.user_context.run();
+
             match riscv::register::scause::read().cause() {
                 Trap::Interrupt(Interrupt::SupervisorTimer) => {
                     call_irq_callback_functions(

ostd/src/arch/x86/cpu/context/mod.rs

@@ -22,7 +22,6 @@ use crate::{
     cpu::PrivilegeLevel,
     irq::call_irq_callback_functions,
     mm::Vaddr,
-    task::scheduler,
     user::{ReturnReason, UserContextApi, UserContextApiInternal},
 };
 
@@ -271,7 +270,7 @@ impl UserContextApiInternal for UserContext {
 
         // Return when it is syscall or cpu exception type is Fault or Trap.
         loop {
-            scheduler::might_preempt();
+            crate::task::scheduler::might_preempt();
             self.user_context.run();
 
             let exception =