mirror of https://github.com/armbian/build.git
145 lines
3.8 KiB
Diff
145 lines
3.8 KiB
Diff
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
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From: Jernej Skrabec <jernej.skrabec@siol.net>
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Date: Fri, 16 Aug 2019 16:40:20 +0200
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Subject: arm64: dts: allwinner: h6: Add AC200 EPHY nodes
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All Allwinner H6 SoCs feature a co-packaged AC200 die, which replaces
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the integrated PHY and audio circuitry of its H3/H5 predecessors. It is
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using an internal I2C connection, but otherwise pretty much behaves as
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it would be externally connected.
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Since every H6 SoC contains this chip, add the required DT nodes to the
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SoC .dtsi, but keep them disabled. This is for now just covering the
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AC200 MFD parent and its EPHY child.
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Any board making use of one of the integrated PHY needs to enable it and
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connect the MAC and PHY accordingly.
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Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
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Signed-off-by: Andre Przywara <andre.przywara@arm.com>
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---
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arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 73 ++++++++++
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1 file changed, 73 insertions(+)
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diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
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index 111111111111..222222222222 100644
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--- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
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+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
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@@ -24,6 +24,16 @@ aliases {
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mmc2 = &mmc2;
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};
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+ ac200_pwm_clk: ac200_clk {
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+ compatible = "pwm-clock";
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+ #clock-cells = <0>;
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+ clock-frequency = <24000000>;
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&pwm1_pin>;
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+ pwms = <&pwm 1 42 0>;
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+ status = "disabled";
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+ };
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+
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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@@ -350,6 +360,14 @@ ths_calibration: thermal-sensor-calibration@14 {
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cpu_speed_grade: cpu-speed-grade@1c {
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reg = <0x1c 0x4>;
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};
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+
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+ ephy_calib: ephy_calib@2c {
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+ reg = <0x2c 0x2>;
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+ };
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+
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+ ac200_bg: ac200_bg@30 {
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+ reg = <0x30 0x2>;
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+ };
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};
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timer@3009000 {
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@@ -405,6 +423,13 @@ ext_rgmii_pins: rgmii-pins {
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drive-strength = <40>;
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};
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+ ext_rmii_pins: rmii_pins {
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+ pins = "PA0", "PA1", "PA2", "PA3", "PA4",
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+ "PA5", "PA6", "PA7", "PA8", "PA9";
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+ function = "emac";
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+ drive-strength = <40>;
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+ };
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+
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hdmi_pins: hdmi-pins {
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pins = "PH8", "PH9", "PH10";
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function = "hdmi";
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@@ -425,6 +450,12 @@ i2c2_pins: i2c2-pins {
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function = "i2c2";
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};
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+ i2c3_pins: i2c3-pins {
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+ pins = "PB17", "PB18";
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+ function = "i2c3";
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+ bias-pull-up;
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+ };
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+
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mmc0_pins: mmc0-pins {
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pins = "PF0", "PF1", "PF2", "PF3",
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"PF4", "PF5";
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@@ -452,6 +483,11 @@ mmc2_pins: mmc2-pins {
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bias-pull-up;
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};
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+ pwm1_pin: pwm1-pin {
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+ pins = "PB19";
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+ function = "pwm1";
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+ };
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+
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/omit-if-no-ref/
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spi0_pins: spi0-pins {
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pins = "PC0", "PC2", "PC3";
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@@ -664,6 +700,43 @@ i2c2: i2c@5002800 {
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#size-cells = <0>;
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};
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+ i2c3: i2c@5002c00 {
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+ compatible = "allwinner,sun50i-h6-i2c",
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+ "allwinner,sun6i-a31-i2c";
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+ reg = <0x05002c00 0x400>;
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+ interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
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+ clocks = <&ccu CLK_BUS_I2C3>;
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+ resets = <&ccu RST_BUS_I2C3>;
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&i2c3_pins>;
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+ clock-frequency = <100000>;
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+ status = "disabled";
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+
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+ ac200: mfd@10 {
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+ compatible = "x-powers,ac200";
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+ reg = <0x10>;
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+ clocks = <&ac200_pwm_clk>;
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+ interrupt-parent = <&pio>;
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+ interrupts = <1 20 IRQ_TYPE_LEVEL_LOW>;
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+ interrupt-controller;
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+ #interrupt-cells = <1>;
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+ nvmem-cells = <&ac200_bg>;
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+ nvmem-cell-names = "bandgap";
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+
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+ ac200_ephy_ctl: syscon {
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+ compatible = "x-powers,ac200-ephy-ctl";
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+ nvmem-cells = <&ephy_calib>;
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+ nvmem-cell-names = "calibration";
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+ #clock-cells = <0>;
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+ #reset-cells = <0>;
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+ phy-mode = "rmii";
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+ status = "disabled";
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+ };
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+ };
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+ };
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+
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spi0: spi@5010000 {
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compatible = "allwinner,sun50i-h6-spi",
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"allwinner,sun8i-h3-spi";
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--
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Armbian
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