// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/* Copyright (c) 2024 Spacemit, Inc */

&cpus {
	clst_core_opp_table0: opp_table0 {
		compatible = "operating-points-v2";
		opp-shared;

		clocks = <&ccu CLK_CPU_C0_ACE>, <&ccu CLK_CPU_C1_ACE>, <&ccu CLK_CPU_C0_TCM>,
			<&ccu CLK_CCI550>, <&ccu CLK_PLL3>;
		clock-names = "ace0","ace1","tcm","cci","pll3";
		cci-hz = /bits/ 64 <614000000>;

		opp1600000000 {
			opp-hz = /bits/ 64 <1600000000>, /bits/ 64 <1600000000>;
			tcm-hz = /bits/ 64 <800000000>;
			ace-hz = /bits/ 64 <800000000>;
			opp-microvolt = <1050000>;
			clock-latency-ns = <200000>;
		};

		opp1228800000 {
			opp-hz = /bits/ 64 <1228800000>, /bits/ 64 <1228800000>;
			tcm-hz = /bits/ 64 <614400000>;
			ace-hz = /bits/ 64 <614400000>;
			opp-microvolt = <950000>;
			clock-latency-ns = <200000>;
		};

		opp1000000000 {
			opp-hz = /bits/ 64 <1000000000>, /bits/ 64 <1000000000>;
			tcm-hz = /bits/ 64 <500000000>;
			ace-hz = /bits/ 64 <500000000>;
			opp-microvolt = <950000>;
			clock-latency-ns = <200000>;
		};

		opp819000000 {
			opp-hz = /bits/ 64 <819000000>, /bits/ 64 <819000000>;
			opp-microvolt = <950000>;
			tcm-hz = /bits/ 64 <409500000>;
			ace-hz = /bits/ 64 <409500000>;
			clock-latency-ns = <200000>;
		};

		opp614400000 {
			opp-hz = /bits/ 64 <614400000>, /bits/ 64 <614400000>;
			tcm-hz = /bits/ 64 <307200000>;
			ace-hz = /bits/ 64 <307200000>;
			opp-microvolt = <950000>;
			clock-latency-ns = <200000>;
		};
	};
};

&cpu_0 {
	clst-supply = <&dcdc_1>;
	clocks = <&ccu CLK_CPU_C0_CORE>, <&ccu CLK_CPU_C1_CORE>;
	clock-names = "cls0", "cls1";
	operating-points-v2 = <&clst_core_opp_table0>;
};

&cpu_1 {
	clst-supply = <&dcdc_1>;
	clocks = <&ccu CLK_CPU_C0_CORE>, <&ccu CLK_CPU_C1_CORE>;
	clock-names = "cls0", "cls1";
	operating-points-v2 = <&clst_core_opp_table0>;
};

&cpu_2 {
	clst-supply = <&dcdc_1>;
	clocks = <&ccu CLK_CPU_C0_CORE>, <&ccu CLK_CPU_C1_CORE>;
	clock-names = "cls0", "cls1";
	operating-points-v2 = <&clst_core_opp_table0>;
};

&cpu_3 {
	clst-supply = <&dcdc_1>;
	clocks = <&ccu CLK_CPU_C0_CORE>, <&ccu CLK_CPU_C1_CORE>;
	clock-names = "cls0", "cls1";
	operating-points-v2 = <&clst_core_opp_table0>;
};

&cpu_4 {
	clst-supply = <&dcdc_1>;
	clocks = <&ccu CLK_CPU_C0_CORE>, <&ccu CLK_CPU_C1_CORE>;
	clock-names = "cls0", "cls1";
	operating-points-v2 = <&clst_core_opp_table0>;
};

&cpu_5 {
	clst-supply = <&dcdc_1>;
	clocks = <&ccu CLK_CPU_C0_CORE>, <&ccu CLK_CPU_C1_CORE>;
	clock-names = "cls0", "cls1";
	operating-points-v2 = <&clst_core_opp_table0>;
};

&cpu_6 {
	clst-supply = <&dcdc_1>;
	clocks = <&ccu CLK_CPU_C0_CORE>, <&ccu CLK_CPU_C1_CORE>;
	clock-names = "cls0", "cls1";
	operating-points-v2 = <&clst_core_opp_table0>;
};

&cpu_7 {
	clst-supply = <&dcdc_1>;
	clocks = <&ccu CLK_CPU_C0_CORE>, <&ccu CLK_CPU_C1_CORE>;
	clock-names = "cls0", "cls1";
	operating-points-v2 = <&clst_core_opp_table0>;
};