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SpacemiT: Add SpacemiT Keystone K1 SoC dts files 

They will be applied on-the-fly by the dt auto-patcher.
This commit is contained in:
ColorfulRhino 2024-06-30 21:00:30 +02:00 committed by Igor
parent e7e9f5d6cf
commit c91039bc28
8 changed files with 5417 additions and 0 deletions
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187
patch/kernel/archive/spacemit-6.1/dt/k1-x-camera-sdk.dtsi Normal file
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// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2023 SPACEMIT Micro Limited
*/
//#include "k1-x-camera-reserved-mm.dtsi"
#include "k1-x-camera-sensor.dtsi"
&soc {
plat-cam {
compatible = "spacemit,plat-cam", "simple-bus";
#address-cells = <2>;
#size-cells = <2>;
interconnects = <&dram_range1>;
interconnect-names = "dma-mem";
status = "okay";
};
csiphy0: csiphy@d420a000 {
compatible = "spacemit,csi-dphy";
cell-index = <0>;
reg = <0x0 0xd420a000 0x0 0x13f>;
reg-names = "csiphy-regs";
clocks = <&ccu CLK_CCIC1PHY>;
clock-names = "csi_dphy";
resets = <&reset RESET_CCIC1_PHY>;
reset-names = "cphy_reset";
interconnects = <&dram_range1>;
interconnect-names = "dma-mem";
status = "okay";
};
csiphy1: csiphy@d420a800 {
compatible = "spacemit,csi-dphy";
cell-index = <1>;
reg = <0x0 0xd420a800 0x0 0x13f>;
reg-names = "csiphy-regs";
clocks = <&ccu CLK_CCIC2PHY>;
clock-names = "csi_dphy";
resets = <&reset RESET_CCIC2_PHY>;
reset-names = "cphy_reset";
interconnects = <&dram_range1>;
interconnect-names = "dma-mem";
status = "okay";
};
csiphy2: csiphy@d4206000 {
compatible = "spacemit,csi-dphy";
cell-index = <2>;
spacemit,bifmode-enable;
reg = <0x0 0xd4206000 0x0 0x13f>;
reg-names = "csiphy-regs";
clocks = <&ccu CLK_CCIC3PHY>;
clock-names = "csi_dphy";
resets = <&reset RESET_CCIC3_PHY>;
reset-names = "cphy_reset";
interconnects = <&dram_range1>;
interconnect-names = "dma-mem";
status = "okay";
};
ccic0: ccic@d420a000 {
compatible = "spacemit,k1xccic";
cell-index = <0>;
spacemit,csiphy = <&csiphy0>;
reg = <0x0 0xd420a000 0x0 0x3ff>;
reg-names = "ccic-regs";
interrupt-parent = <&intc>;
interrupts = <81>;
interrupt-names = "ipe-irq";
clocks = <&ccu CLK_CSI>,
<&ccu CLK_CCIC_4X>,
<&ccu CLK_ISP_BUS>;
clock-names = "csi_func", "ccic_func", "isp_axi";
resets = <&reset RESET_ISP_AHB>, <&reset RESET_CSI>,
<&reset RESET_CCIC_4X>, <&reset RESET_ISP_CI>;
reset-names = "isp_ahb_reset", "csi_reset",
"ccic_4x_reset", "isp_ci_reset";
interconnects = <&dram_range1>;
interconnect-names = "dma-mem";
status = "okay";
};
ccic1: ccic@d420a800 {
compatible = "spacemit,k1xccic";
cell-index = <1>;
spacemit,csiphy = <&csiphy2>;
reg = <0x0 0xd420a800 0x0 0x3ff>;
reg-names = "ccic-regs";
interrupt-parent = <&intc>;
interrupts = <82>;
interrupt-names = "ipe-irq";
clocks = <&ccu CLK_CSI>, <&ccu CLK_CCIC_4X>,
<&ccu CLK_ISP_BUS>;
clock-names = "csi_func", "ccic_func",
"isp_axi";
resets = <&reset RESET_ISP_AHB>, <&reset RESET_CSI>,
<&reset RESET_CCIC_4X>, <&reset RESET_ISP_CI>;
reset-names = "isp_ahb_reset", "csi_reset",
"ccic_4x_reset", "isp_ci_reset";
interconnects = <&dram_range1>;
interconnect-names = "dma-mem";
status = "okay";
};
ccic2: ccic@d4206000 {
compatible = "spacemit,k1xccic";
cell-index = <2>;
spacemit,csiphy = <&csiphy2>;
reg = <0x0 0xd4206000 0x0 0x3ff>;
reg-names = "ccic-regs";
interrupt-parent = <&intc>;
interrupts = <83>;
interrupt-names = "ipe-irq";
clocks = <&ccu CLK_CSI>, <&ccu CLK_CCIC_4X>,
<&ccu CLK_ISP_BUS>;
clock-names = "csi_func", "ccic_func",
"isp_axi";
resets = <&reset RESET_ISP_AHB>, <&reset RESET_CSI>,
<&reset RESET_CCIC_4X>, <&reset RESET_ISP_CI>;
reset-names = "isp_ahb_reset", "csi_reset",
"ccic_4x_reset", "isp_ci_reset";
interconnects = <&dram_range1>;
interconnect-names = "dma-mem";
status = "okay";
};
isp: isp@C0230000 {
compatible = "spacemit,k1xisp";
reg = <0x0 0xC0230000 0x0 0x12700>;
reg-names = "isp";
interrupt-parent = <&intc>;
interrupts = <79>, <85>;
interrupt-names = "feisp-irq", "feisp-dma-irq";
clocks = <&ccu CLK_ISP>,
<&ccu CLK_ISP_BUS>,
<&ccu CLK_DPU_MCLK>;
clock-names = "isp_func", "isp_axi", "dpu_mclk";
resets = <&reset RESET_ISP_AHB>, <&reset RESET_ISP>,
<&reset RESET_ISP_CI>, <&reset RESET_LCD_MCLK>;
reset-names = "isp_ahb_reset", "isp_reset",
"isp_ci_reset", "lcd_mclk_reset";
interconnects = <&dram_range1>;
interconnect-names = "dma-mem";
status = "okay";
};
vi: vi@C0230000 {
compatible = "spacemit,k1xvi";
reg = <0x0 0xc0230000 0x0 0x14000>;
reg-names = "vi";
interrupt-parent = <&intc>;
interrupts = <79>, <85>;
interrupt-names = "feisp-irq", "feisp-dma-irq";
clocks = <&ccu CLK_ISP>, <&ccu CLK_ISP_BUS>,
<&ccu CLK_DPU_MCLK>;
clock-names = "isp_func", "isp_axi",
"dpu_mclk";
resets = <&reset RESET_ISP_AHB>, <&reset RESET_ISP>,
<&reset RESET_ISP_CI>, <&reset RESET_LCD_MCLK>;
reset-names = "isp_ahb_reset", "isp_reset",
"isp_ci_reset", "lcd_mclk_reset";
interconnects = <&dram_range1>;
interconnect-names = "dma-mem";
status = "okay";
};
cpp: cpp@C02f0000 {
compatible = "spacemit,k1xcpp";
reg = <0x0 0xC02f0000 0x0 0x7fff>;
reg-names = "cpp";
interrupt-parent = <&intc>;
interrupts = <84>;
interrupt-names = "cpp";
clocks = <&ccu CLK_ISP_CPP>, <&ccu CLK_ISP_BUS>,
<&ccu CLK_DPU_MCLK>;
clock-names = "cpp_func", "isp_axi",
"dpu_mclk";
resets = <&reset RESET_ISP_AHB>, <&reset RESET_ISP_CPP>,
<&reset RESET_ISP_CI>, <&reset RESET_LCD_MCLK>;
reset-names = "isp_ahb_reset", "isp_cpp_reset",
"isp_ci_reset", "lcd_mclk_reset";
interconnects = <&dram_range1>;
interconnect-names = "dma-mem";
status = "okay";
};
}; /* soc */

73
patch/kernel/archive/spacemit-6.1/dt/k1-x-camera-sensor.dtsi Normal file
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// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2023 SPACEMIT Micro Limited
*/
#include <dt-bindings/gpio/gpio.h>
#include "k1-x_pinctrl.dtsi"
&soc {
/* imx315 */
backsensor: cam_sensor@0 {
cell-index = <0>;
twsi-index = <0>;
dphy-index = <0>;
compatible = "spacemit,cam-sensor";
clocks = <&ccu CLK_CAMM0>;
clock-names = "cam_mclk0";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_camera0>;
//pwdn-gpios = <&gpio 113 GPIO_ACTIVE_HIGH>;
//reset-gpios = <&gpio 111 GPIO_ACTIVE_HIGH>;
//dphy-entries = <5>;
//dphy-settings = <0x00000001 0xa2848888 0x00001500 0x000000ff 0x1001>;
/*
afvdd28-supply = <&ldo_12>;
avdd28-supply = <&ldo_10>;
dvdd12-supply = <&ldo_20>;
iovdd18-supply = <&ldo_11>;
cam-supply-names = "afvdd28", "avdd28", "dvdd12", "iovdd18";
*/
interconnects = <&dram_range1>;
interconnect-names = "dma-mem";
status = "okay";
};
/* gc2375h */
backsensor_aux: cam_sensor@1 {
cell-index = <1>;
twsi-index = <1>;
dphy-index = <2>;
compatible = "spacemit,cam-sensor";
clocks = <&ccu CLK_CAMM1>;
clock-names = "cam_mclk1";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_camera1>;
//dphy-entries = <5>;
//dphy-settings = <0x00000001 0xa2848888 0x00001500 0x000000ff 0x1001>;
//pwdn-gpios = <&gpio 114 GPIO_ACTIVE_HIGH>;
//reset-gpios = <&gpio 112 GPIO_ACTIVE_HIGH>;
interconnects = <&dram_range1>;
interconnect-names = "dma-mem";
status = "okay";
};
/* S5K5E3 */
frontsensor: cam_sensor@2 {
cell-index = <2>;
twsi-index = <1>;
dphy-index = <2>;
compatible = "spacemit,cam-sensor";
clocks = <&ccu CLK_CAMM2>;
clock-names = "cam_mclk2";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_camera2>;
//dphy-entries = <5>;
//dphy-settings = <0x00000001 0xa2848888 0x00001500 0x000000ff 0x1001>;
//pwdn-gpios = <&gpio 122 GPIO_ACTIVE_HIGH>;
//reset-gpios = <&gpio 121 GPIO_ACTIVE_HIGH>;
interconnects = <&dram_range1>;
interconnect-names = "dma-mem";
status = "okay";
};
};

62
patch/kernel/archive/spacemit-6.1/dt/k1-x-hdmi.dtsi Normal file
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// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/* Copyright (c) 2023 Spacemit, Inc */
&soc {
display-subsystem-hdmi {
compatible = "spacemit,saturn-hdmi";
reg = <0 0xc0440000 0 0x2A000>;
ports = <&dpu_online2_hdmi>;
interconnects = <&dram_range1>;
interconnect-names = "dma-mem";
};
dpu_online2_hdmi: port@c0440000 {
compatible = "spacemit,dpu-online2";
interrupt-parent = <&intc>;
interrupts = <139>, <138>;
interrupt-names = "ONLINE_IRQ", "OFFLINE_IRQ";
interconnects = <&dram_range1>;
interconnect-names = "dma-mem";
clocks = <&ccu CLK_HDMI>;
clock-names = "hmclk";
resets = <&reset RESET_HDMI>;
reset-names= "hdmi_reset";
power-domains = <&power K1X_PMU_HDMI_PWR_DOMAIN>;
pipeline-id = <ONLINE2>;
ip = "spacemit-saturn";
type = <HDMI>;
clk,pm-runtime,no-sleep;
status = "disabled";
dpu_online2_hdmi_out: endpoint@0 {
remote-endpoint = <&hdmi_in>;
};
dpu_offline0_hdmi_out: endpoint@1 {
/* remote-endpoint = <&wb0_in>; */
};
};
hdmi: hdmi@C0400500 {
compatible = "spacemit,hdmi";
reg = <0 0xC0400500 0 0x200>;
interrupt-parent = <&intc>;
interrupts = <136>;
clocks = <&ccu CLK_HDMI>;
clock-names = "hmclk";
resets = <&reset RESET_HDMI>;
reset-names= "hdmi_reset";
power-domains = <&power K1X_PMU_HDMI_PWR_DOMAIN>;
clk,pm-runtime,no-sleep;
status = "disabled";
port {
#address-cells = <1>;
#size-cells = <0>;
hdmi_in: endpoint@0 {
reg = <0>;
remote-endpoint = <&dpu_online2_hdmi_out>;
};
};
};
};

116
patch/kernel/archive/spacemit-6.1/dt/k1-x-lcd.dtsi Normal file
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// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/* Copyright (c) 2023 Spacemit, Inc */
&soc {
display-subsystem-dsi {
compatible = "spacemit,saturn-le";
reg = <0 0xC0340000 0 0x2A000>;
ports = <&dpu_online2_dsi>;
interconnects = <&dram_range1>;
interconnect-names = "dma-mem";
};
dpu_online2_dsi: port@c0340000 {
compatible = "spacemit,dpu-online2";
interrupt-parent = <&intc>;
interrupts = <90>, <89>;
interrupt-names = "ONLINE_IRQ", "OFFLINE_IRQ";
interconnects = <&dram_range1>;
interconnect-names = "dma-mem";
clocks = <&ccu CLK_DPU_PXCLK>,
<&ccu CLK_DPU_MCLK>,
<&ccu CLK_DPU_HCLK>,
<&ccu CLK_DPU_ESC>,
<&ccu CLK_DPU_BIT>;
clock-names = "pxclk", "mclk", "hclk", "escclk", "bitclk";
resets = <&reset RESET_MIPI>,
<&reset RESET_LCD_MCLK>,
<&reset RESET_LCD>,
<&reset RESET_DSI_ESC>;
reset-names= "dsi_reset", "mclk_reset", "lcd_reset","esc_reset";
power-domains = <&power K1X_PMU_LCD_PWR_DOMAIN>;
pipeline-id = <ONLINE2>;
ip = "spacemit-saturn";
spacemit-dpu-min-mclk = <40960000>;
type = <DSI>;
clk,pm-runtime,no-sleep;
status = "disabled";
dpu_online2_dsi_out: endpoint@0 {
remote-endpoint = <&dsi2_in>;
};
dpu_offline0_dsi_out: endpoint@1 {
remote-endpoint = <&wb0_in>;
};
};
dsi2: dsi2@d421a800 {
compatible = "spacemit,dsi2-host";
#address-cells = <1>;
#size-cells = <0>;
reg = <0 0xD421A800 0 0x200>;
interrupt-parent = <&intc>;
interrupts = <95>;
ip = "synopsys-dhost";
dev-id = <2>;
status = "disabled";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
#address-cells = <1>;
#size-cells = <0>;
dsi2_out: endpoint@0 {
reg = <0>;
remote-endpoint = <&dphy2_in>;
};
};
port@1 {
reg = <1>;
dsi2_in: endpoint {
remote-endpoint = <&dpu_online2_dsi_out>;
};
};
};
};
dphy2: dphy2@d421a800 {
compatible = "spacemit,dsi2-phy";
#address-cells = <1>;
#size-cells = <0>;
reg = <0 0xD421A800 0 0x200>;
ip = "spacemit-dphy";
dev-id = <2>;
status = "okay";
port@1 {
reg = <1>;
dphy2_in: endpoint {
remote-endpoint = <&dsi2_out>;
};
};
};
wb0 {
compatible = "spacemit,wb0";
dev-id = <2>;
status = "okay";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
wb0_in: endpoint {
remote-endpoint = <&dpu_offline0_dsi_out>;
};
};
};
};
};

2536
patch/kernel/archive/spacemit-6.1/dt/k1-x.dtsi Normal file
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File diff suppressed because it is too large Load Diff

1129
patch/kernel/archive/spacemit-6.1/dt/k1-x_deb1.dts Normal file
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File diff suppressed because it is too large Load Diff

1157
patch/kernel/archive/spacemit-6.1/dt/k1-x_pinctrl.dtsi Normal file
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File diff suppressed because it is too large Load Diff

157
patch/kernel/archive/spacemit-6.1/dt/lcd_gx09inx101_mipi.dtsi Normal file
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// SPDX-License-Identifier: GPL-2.0
/ { lcds: lcds {
lcd_gx09inx101_mipi: lcd_gx09inx101_mipi {
dsi-work-mode = <1>; /* video burst mode*/
dsi-lane-number = <4>;
dsi-color-format = "rgb888";
width-mm = <142>;
height-mm = <228>;
use-dcs-write;
/*mipi info*/
height = <1920>;
width = <1200>;
hfp = <80>;
hbp = <40>;
hsync = <10>;
vfp = <20>;
vbp = <16>;
vsync = <4>;
fps = <60>;
work-mode = <0>;
rgb-mode = <3>;
lane-number = <4>;
phy-bit-clock = <1000000000>;
phy-esc-clock = <76800000>;
split-enable = <0>;
eotp-enable = <0>;
burst-mode = <2>;
esd-check-enable = <0>;
/* DSI_CMD, DSI_MODE, timeout, len, cmd */
initial-command = [
39 01 00 02 B0 01
39 01 00 02 C3 4F
39 01 00 02 C4 40
39 01 00 02 C5 40
39 01 00 02 C6 40
39 01 00 02 C7 40
39 01 00 02 C8 4D
39 01 00 02 C9 52
39 01 00 02 CA 51
39 01 00 02 CD 5D
39 01 00 02 CE 5B
39 01 00 02 CF 4B
39 01 00 02 D0 49
39 01 00 02 D1 47
39 01 00 02 D2 45
39 01 00 02 D3 41
39 01 00 02 D7 50
39 01 00 02 D8 40
39 01 00 02 D9 40
39 01 00 02 DA 40
39 01 00 02 DB 40
39 01 00 02 DC 4E
39 01 00 02 DD 52
39 01 00 02 DE 51
39 01 00 02 E1 5E
39 01 00 02 E2 5C
39 01 00 02 E3 4C
39 01 00 02 E4 4A
39 01 00 02 E5 48
39 01 00 02 E6 46
39 01 00 02 E7 42
39 01 00 02 B0 03
39 01 00 02 BE 03
39 01 00 02 CC 44
39 01 00 02 C8 07
39 01 00 02 C9 05
39 01 00 02 CA 42
39 01 00 02 CD 3E
39 01 00 02 CF 60
39 01 00 02 D2 04
39 01 00 02 D3 04
39 01 00 02 D4 01
39 01 00 02 D5 00
39 01 00 02 D6 03
39 01 00 02 D7 04
39 01 00 02 D9 01
39 01 00 02 DB 01
39 01 00 02 E4 F0
39 01 00 02 E5 0A
39 01 00 02 B0 00
39 01 00 02 BD 50
39 01 00 02 C2 08
39 01 00 02 C4 10
39 01 00 02 CC 00
// 39 01 00 02 B2 41 // BIST pattern
39 01 00 02 B0 02
39 01 00 02 C0 00
39 01 00 02 C1 0A
39 01 00 02 C2 20
39 01 00 02 C3 24
39 01 00 02 C4 23
39 01 00 02 C5 29
39 01 00 02 C6 23
39 01 00 02 C7 1C
39 01 00 02 C8 19
39 01 00 02 C9 17
39 01 00 02 CA 17
39 01 00 02 CB 18
39 01 00 02 CC 1A
39 01 00 02 CD 1E
39 01 00 02 CE 20
39 01 00 02 CF 23
39 01 00 02 D0 07
39 01 00 02 D1 00
39 01 00 02 D2 00
39 01 00 02 D3 0A
39 01 00 02 D4 13
39 01 00 02 D5 1C
39 01 00 02 D6 1A
39 01 00 02 D7 13
39 01 00 02 D8 17
39 01 00 02 D9 1C
39 01 00 02 DA 19
39 01 00 02 DB 17
39 01 00 02 DC 17
39 01 00 02 DD 18
39 01 00 02 DE 1A
39 01 00 02 DF 1E
39 01 00 02 E0 20
39 01 00 02 E1 23
39 01 00 02 E2 07
39 01 F0 01 11
39 01 28 01 29
];
sleep-in-command = [
39 01 78 01 28
39 01 78 01 10
];
sleep-out-command = [
39 01 96 01 11
39 01 32 01 29
];
read-id-command = [
37 01 00 01 05
14 01 00 05 fb fc fd fe ff
];
display-timings {
timing0 {
clock-frequency = <143000000>;
hactive = <1200>;
hfront-porch = <80>;
hback-porch = <40>;
hsync-len = <10>;
vactive = <1920>;
vfront-porch = <20>;
vback-porch = <16>;
vsync-len = <4>;
vsync-active = <1>;
hsync-active = <1>;
};
};
};
};};