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Merge branch 'main' into v24.02

This commit is contained in:
Igor Pecovnik 2024-02-13 22:15:50 +01:00
parent 080d234467 fa3c79675a
commit c72537f21f
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GPG Key ID: 93D6889F9F0E78D5
36 changed files with 1388 additions and 55 deletions
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2
.github/workflows/scorecard.yml vendored
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@ -50,7 +50,7 @@ jobs:
# Upload the results as artifacts (optional). Commenting out will disable uploads of run results in SARIF
# format to the repository Actions tab.
- name: "Upload artifact"
uses: actions/upload-artifact@26f96dfa697d77e81fd5907df203aa23a56210a8 # v4.3.0
uses: actions/upload-artifact@5d5d22a31266ced268874388b861e4b58bb5c2f3 # v4.3.1
with:
name: SARIF file
path: results.sarif

0
config/boards/armsom-sige7.csc Executable file → Normal file
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0
config/boards/fxblox-rk1.wip → config/boards/fxblox-rk1.csc
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0
config/boards/helios4.csc → config/boards/helios4.conf
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0
config/boards/jp-tvbox-3566.tvb Executable file → Normal file
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0
config/boards/mekotronics-r58-minipc.wip → config/boards/mekotronics-r58-minipc.csc
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0
config/boards/mekotronics-r58x-4g.wip → config/boards/mekotronics-r58x-4g.csc
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0
config/boards/mekotronics-r58x.wip → config/boards/mekotronics-r58x.csc
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0
config/boards/mixtile-blade3.wip → config/boards/mixtile-blade3.csc
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0
config/boards/nanopct6.wip → config/boards/nanopct6.csc
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0
config/boards/nanopi-r5s.wip → config/boards/nanopi-r5s.csc
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0
config/boards/nanopi-r6s.conf → config/boards/nanopi-r6s.csc
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0
config/boards/orangepi-r1.conf → config/boards/orangepi-r1.csc
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0
config/boards/orangepi-r1plus-lts.conf → config/boards/orangepi-r1plus-lts.csc
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0
config/boards/qemu-uboot-arm64.wip → config/boards/qemu-uboot-arm64.csc
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0
config/boards/qemu-uboot-x86.wip → config/boards/qemu-uboot-x86.csc
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0
config/boards/radxa-e25.wip → config/boards/radxa-e25.csc
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0
config/boards/radxa-zero2.wip → config/boards/radxa-zero2.csc
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0
config/boards/rock-3a.conf → config/boards/rock-3a.csc
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0
config/boards/rock-5a.wip → config/boards/rock-5a.csc
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0
config/boards/rock-5b.conf → config/boards/rock-5b.csc
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15
config/boards/rock-s0.wip Normal file
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@ -0,0 +1,15 @@
# Rockchip RK3308 quad core 512MB SoC WiFi
# https://radxa.com/products/rocks/s0
BOARD_NAME="Rock S0"
BOARDFAMILY="rock-s0"
BOARD_MAINTAINER="brentr"
BOOTCONFIG="rock-s0-rk3308_defconfig"
DEFAULT_CONSOLE="serial"
SERIALCON="ttyS0"
KERNEL_TARGET="current,edge"
KERNEL_TEST_TARGET=$KERNEL_TARGET
BOOT_FDT_FILE="rockchip/rk3308-rock-s0.dtb"
MODULES_BLACKLIST="rockchipdrm analogix_dp dw_mipi_dsi dw_hdmi gpu_sched lima hantro_vpu panfrost"
HAS_VIDEO_OUTPUT="no"
BOOTBRANCH_BOARD="tag:v2022.04"
BOOTPATCHDIR="u-boot-rockchip64-v2022.04"

0
config/boards/rockpi-4a.conf → config/boards/rockpi-4a.csc
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1
config/boards/wdk2023.wip
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@ -1,6 +1,7 @@
# Qualcomm Snapdragon 8cx Gen 3 Adreno 690 Qualcomm WCN6855 Wi-Fi 6E Bluetooth 5.1
declare -g BOARD_NAME="Windows Dev Kit 2023"
declare -g BOARDFAMILY="uefi-arm64"
declare -g BOARD_MAINTAINER=""
declare -g KERNEL_TARGET="wdk2023"
declare -g BRANCH="wdk2023"

73
config/bootscripts/boot-rock-s0.cmd Normal file
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@ -0,0 +1,73 @@
# DO NOT EDIT THIS FILE
#
# Please edit /boot/armbianEnv.txt to set supported parameters
#
setenv load_addr "0x9000000"
# Ensure the ever expanding kernel never overlaps initial device tree load area
setenv fdt_addr_r "0x7800000"
setenv overlay_error "false"
# default values
setenv rootdev "/dev/mmcblk0p1"
setenv verbosity "1"
setenv console "both"
setenv rootfstype "ext4"
setenv docker_optimizations "on"
setenv earlycon "off"
echo "Boot script loaded from ${devtype} ${devnum}"
if test -e ${devtype} ${devnum} ${prefix}armbianEnv.txt; then
load ${devtype} ${devnum} ${load_addr} ${prefix}armbianEnv.txt
env import -t ${load_addr} ${filesize}
fi
if test "${logo}" = "disabled"; then setenv logo "logo.nologo"; fi
if test "${console}" = "display" || test "${console}" = "both"; then setenv consoleargs "console=tty1"; fi
if test "${console}" = "serial" || test "${console}" = "both"; then setenv consoleargs "console=ttyS0,1500000 ${consoleargs}"; fi
if test "${earlycon}" = "on"; then setenv consoleargs "earlycon ${consoleargs}"; fi
# get PARTUUID of first partition on SD/eMMC the boot script was loaded from
if test "${devtype}" = "mmc"; then part uuid mmc ${devnum}:1 partuuid; fi
setenv bootargs "root=${rootdev} rootwait rootfstype=${rootfstype} ${consoleargs} consoleblank=0 loglevel=${verbosity} ubootpart=${partuuid} usb-storage.quirks=${usbstoragequirks} ${extraargs} ${extraboardargs}"
if test "${docker_optimizations}" = "on"; then setenv bootargs "${bootargs} cgroup_enable=cpuset cgroup_memory=1 cgroup_enable=memory swapaccount=1"; fi
load ${devtype} ${devnum} ${ramdisk_addr_r} ${prefix}uInitrd
load ${devtype} ${devnum} ${kernel_addr_r} ${prefix}Image
load ${devtype} ${devnum} ${fdt_addr_r} ${prefix}dtb/${fdtfile}
fdt addr ${fdt_addr_r}
fdt resize 65536
for overlay_file in ${overlays}; do
if load ${devtype} ${devnum} ${load_addr} ${prefix}dtb/rockchip/overlay/${overlay_prefix}-${overlay_file}.dtbo; then
echo "Applying kernel provided DT overlay ${overlay_prefix}-${overlay_file}.dtbo"
fdt apply ${load_addr} || setenv overlay_error "true"
fi
done
for overlay_file in ${user_overlays}; do
if load ${devtype} ${devnum} ${load_addr} ${prefix}overlay-user/${overlay_file}.dtbo; then
echo "Applying user provided DT overlay ${overlay_file}.dtbo"
fdt apply ${load_addr} || setenv overlay_error "true"
fi
done
if test "${overlay_error}" = "true"; then
echo "Error applying DT overlays, restoring original DT"
load ${devtype} ${devnum} ${fdt_addr_r} ${prefix}dtb/${fdtfile}
else
if load ${devtype} ${devnum} ${load_addr} ${prefix}dtb/rockchip/overlay/${overlay_prefix}-fixup.scr; then
echo "Applying kernel provided DT fixup script (${overlay_prefix}-fixup.scr)"
source ${load_addr}
fi
if test -e ${devtype} ${devnum} ${prefix}fixup.scr; then
load ${devtype} ${devnum} ${load_addr} ${prefix}fixup.scr
echo "Applying user provided fixup script (fixup.scr)"
source ${load_addr}
fi
fi
booti ${kernel_addr_r} ${ramdisk_addr_r} ${fdt_addr_r}
# Recompile with:
# mkimage -C none -A arm -T script -d /boot/boot.cmd /boot/boot.scr

88
config/sources/families/include/rockchip64_common.inc
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@ -69,81 +69,65 @@ fi
CPUMIN=${CPUMIN:="408000"}
if [[ $BOOT_SOC == rk3399 ]]; then
CPUMAX=${CPUMAX:="2016000"}
elif [[ $BOOT_SOC == rk3328 || $BOOT_SOC == rk3308 ]]; then
CPUMAX=${CPUMAX:="1296000"}
elif [[ "${BOOT_SOC}" == rk3528 ]]; then
CPUMAX=${CPUMAX:="2016000"}
elif [[ "${BOOT_SOC}" == rk3566 ]]; then
CPUMAX=${CPUMAX:="1800000"}
elif [[ "${BOOT_SOC}" == rk3568 ]]; then
CPUMAX=${CPUMAX:="1992000"}
fi
# BOOT_SOC_MKIMAGE defaults to BOOT_SOC, but can be overriden. See rk3566
declare -g BOOT_SOC_MKIMAGE="${BOOT_SOC}"
if [[ $BOOT_SOC == rk3328 ]]; then
case "$BOOT_SOC" in
rk3328)
CPUMAX=${CPUMAX:="1296000"}
BOOT_SCENARIO="${BOOT_SCENARIO:=only-blobs}"
DDR_BLOB="${DDR_BLOB:-"rk33/rk3328_ddr_333MHz_v1.16.bin"}"
MINILOADER_BLOB="${MINILOADER_BLOB:-"rk33/rk322xh_miniloader_v2.50.bin"}"
BL31_BLOB="${BL31_BLOB:-"rk33/rk322xh_bl31_v1.44.elf"}"
;;
elif [[ $BOOT_SOC == rk3399 ]]; then
rk3399)
CPUMAX=${CPUMAX:="2016000"}
BOOT_SCENARIO="${BOOT_SCENARIO:=only-blobs}"
DDR_BLOB="${DDR_BLOB:-"rk33/rk3399_ddr_933MHz_v1.25.bin"}"
MINILOADER_BLOB="${MINILOADER_BLOB:-"rk33/rk3399_miniloader_v1.26.bin"}"
BL31_BLOB="${BL31_BLOB:-"rk33/rk3399_bl31_v1.35.elf"}"
;;
elif [[ $BOOT_SOC == rk3399pro ]]; then
rk3399pro)
CPUMAX=${CPUMAX:="2016000"}
BOOT_SCENARIO="${BOOT_SCENARIO:=only-blobs}"
DDR_BLOB="${DDR_BLOB:-"rk33/rk3399pro_npu_ddr_933MHz_v1.02.bin"}"
MINILOADER_BLOB="${MINILOADER_BLOB:-"rk33/rk3399pro_miniloader_v1.26.bin"}"
BL31_BLOB="${BL31_BLOB:-"rk33/rk3399pro_bl31_v1.35.elf"}"
;;
elif [[ $BOOT_SOC == rk3528 ]]; then
rk3528)
CPUMAX=${CPUMAX:="2016000"}
BOOT_SCENARIO="${BOOT_SCENARIO:=spl-blobs}"
DDR_BLOB="${DDR_BLOB:-"rk35/rk3528_ddr_1056MHz_v1.06.bin"}"
BL31_BLOB="${BL31_BLOB:-"rk35/rk3528_bl31_v1.16.elf"}"
;;
elif [[ $BOOT_SOC == rk3566 ]]; then
rk3566)
CPUMAX=${CPUMAX:="1800000"}
BOOT_SCENARIO="${BOOT_SCENARIO:=spl-blobs}"
DDR_BLOB="${DDR_BLOB:-"rk35/rk3566_ddr_1056MHz_v1.10.bin"}"
BL31_BLOB="${BL31_BLOB:-"rk35/rk3568_bl31_v1.29.elf"}"
BOOT_SOC_MKIMAGE="rk3568" # mkimage does not know about rk3566, and rk3568 works.
;;
elif [[ $BOOT_SOC == rk3568 ]]; then
rk3568)
CPUMAX=${CPUMAX:="1992000"}
BOOT_SCENARIO="${BOOT_SCENARIO:=spl-blobs}"
DDR_BLOB="${DDR_BLOB:-"rk35/rk3568_ddr_1560MHz_v1.13.bin"}"
BL31_BLOB="${BL31_BLOB:-"rk35/rk3568_bl31_v1.32.elf"}"
;;
elif [[ $BOOT_SOC == rk3588 ]]; then
rk3588) #CPUMAX undefined?
BOOT_SCENARIO="${BOOT_SCENARIO:=spl-blobs}"
DDR_BLOB="${DDR_BLOB:-"rk35/rk3588_ddr_lp4_2112MHz_lp5_2736MHz_v1.08.bin"}"
BL31_BLOB="${BL31_BLOB:-"rk35/rk3588_bl31_v1.28.elf"}"
;;
elif [[ $BOARD == rockpi-s ]]; then
rk3308)
CPUMAX=${CPUMAX:="1296000"}
BOOT_SCENARIO="${BOOT_SCENARIO:=only-blobs}"
BOOT_SOC=rk3308
DDR_BLOB="${DDR_BLOB:-"rk33/rk3308_ddr_589MHz_uart2_m1_v1.30.bin"}"
MINILOADER_BLOB="${MINILOADER_BLOB:-"rk33/rk3308_miniloader_v1.22.bin"}"
BL31_BLOB="${BL31_BLOB:-"rk33/rk3308_bl31_v2.22.elf"}"
@ -153,11 +137,11 @@ elif [[ $BOARD == rockpi-s ]]; then
MINILOADER_BLOB="${MINILOADER_BLOB:-"rk33/rk3308_miniloader_sd_nand_v1.13.bin"}"
BL31_BLOB="${BL31_BLOB:-"rk33/rk3308_bl31_v2.10.elf"}"
fi
fi
esac
prepare_boot_configuration() {
if [[ $BOOT_SCENARIO == "blobless" || $BOOT_SCENARIO == "tpl-blob-atf-mainline" ]]; then
case "$BOOT_SCENARIO" in
blobless|tpl-blob-atf-mainline)
UBOOT_TARGET_MAP="BL31=bl31.elf idbloader.img u-boot.itb;;idbloader.img u-boot.itb"
ATFSOURCE='https://github.com/ARM-software/arm-trusted-firmware'
ATF_COMPILER='aarch64-linux-gnu-'
@ -167,27 +151,26 @@ prepare_boot_configuration() {
ATF_TARGET_MAP="M0_CROSS_COMPILE=arm-linux-gnueabi- PLAT=$BOOT_SOC bl31;;build/$BOOT_SOC/release/bl31/bl31.elf:bl31.elf"
ATF_TOOLCHAIN2="arm-linux-gnueabi-:< 10.0"
[[ $BOOT_SCENARIO == "tpl-blob-atf-mainline" ]] && UBOOT_TARGET_MAP="BL31=bl31.elf idbloader.img u-boot.itb;;idbloader.img u-boot.itb"
elif [[ $BOOT_SCENARIO == "tpl-spl-blob" ]]; then
[[ $BOOT_SCENARIO == tpl-blob-atf-mainline ]] &&
UBOOT_TARGET_MAP="BL31=bl31.elf idbloader.img u-boot.itb;;idbloader.img u-boot.itb"
;;
tpl-spl-blob)
UBOOT_TARGET_MAP="BL31=$RKBIN_DIR/$BL31_BLOB idbloader.img u-boot.itb;;idbloader.img u-boot.itb"
ATFSOURCE=''
ATF_COMPILE='no'
elif [[ $BOOT_SCENARIO == "spl-blobs" ]]; then
;;
spl-blobs)
UBOOT_TARGET_MAP="BL31=$RKBIN_DIR/$BL31_BLOB spl/u-boot-spl.bin u-boot.dtb u-boot.itb;;idbloader.img u-boot.itb"
ATFSOURCE=''
ATF_COMPILE='no'
;;
elif [[ $BOOT_SCENARIO == "only-blobs" ]]; then
only-blobs)
UBOOT_TARGET_MAP="u-boot-dtb.bin;;idbloader.bin uboot.img trust.bin"
ATFSOURCE=''
ATF_COMPILE='no'
fi
esac
if [[ $BOOT_SUPPORT_SPI == yes ]]; then
@ -198,7 +181,6 @@ prepare_boot_configuration() {
fi
fi
}
uboot_custom_postprocess() {

64
config/sources/families/rock-s0.conf Normal file
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@ -0,0 +1,64 @@
#
# SPDX-License-Identifier: GPL-2.0
#
# Copyright (c) 2013-2024 Igor Pecovnik, igor@armbian.com
#
# This file is a part of the Armbian Build Framework
# https://github.com/armbian/build/
#
source "${BASH_SOURCE%/*}/include/rockchip64_common.inc"
BOOTENV_FILE='rockpis.txt'
OVERLAY_PREFIX='rk3308'
BOOTSCRIPT=boot-rock-s0.cmd:boot.cmd
#comment out line below for an image that will NOT boot from the built-in SDNAND
IDBLOADER_BLOB=$SRC/packages/blobs/rockchip/rk3308_idbloader_ddr589MHz_uart0_m0_v2.06.136sd.bin
#The SDNAND capabilty IDBLOADER_BLOB requires the U-Boot and Linux serial console on UART0
#Linux will hang on reboot if the console remains on UART2
#Note: IDBLOADER_BLOB is derived from
# https://dl.radxa.com/rockpis/images/loader/rk3308_loader_ddr589MHz_uart0_m0_v2.06.136sd.bin
#by using the rkdeveloptool to "upgrade" the previous DDR_BLOB loader on the SDNAND
#To recreate it, build the image with IDBLOADER_BLOB unset and boot Rock PI-S in MASKROM mode
#On your host (connected to the RockPi-S's USB-C port):
# rdeveloptool db rk3308_loader_ddr589MHz_uart0_m0_v2.06.136sd.bin
# rdeveloptool wl 0 newly_built_image.img
# rdeveloptool ul rk3308_loader_ddr589MHz_uart0_m0_v2.06.136sd.bin #this writes 280 sectors
#Then, reset the RockPi-S to boot from SDNAND. Using that running image:
# dd if=/dev/mmcblk0 of=rk3308_idbloader_ddr589MHz_uart0_m0_v2.06.136sd.bin skip=64 count=280
case $BRANCH in
legacy)
echo "Legacy not supported for rock-s0 board"
exit 99
;;
esac
prepare_boot_configuration
uboot_custom_postprocess() {
# TODO: remove this diversion from common caused by different loaderimage params
loaderimage --pack --uboot ./u-boot-dtb.bin uboot.img 0x600000 --size 1024 1 &&
if [ -r "$IDBLOADER_BLOB" ]; then
echo "Installing $IDBLOADER_BLOB"
echo "Capable of booting from built-in SDNAND"
cp $IDBLOADER_BLOB idbloader.bin
else
[ "$IDBLOADER_BLOB" ] && echo "Missing $IDBLOADER_BLOB"
echo "WARNING: This image will not boot from built-in SDNAND"
tools/mkimage -n rk3308 -T rksd -d $RKBIN_DIR/$DDR_BLOB idbloader.bin &&
cat $RKBIN_DIR/$MINILOADER_BLOB >> idbloader.bin
fi &&
trust_merger --replace bl31.elf $RKBIN_DIR/$BL31_BLOB trust.ini
}
family_tweaks_bsp() { #Install udev script that derives fixed, unique MAC addresses for net interfaces
#that are assigned random ones -- like RockPI-S's WiFi network interfaces
bsp=$SRC/packages/bsp/rockpis
rules=etc/udev/rules.d
install -m 755 $bsp/lib/udev/fixEtherAddr $destination/lib/udev &&
install -m 644 $bsp/$rules/05-fixMACaddress.rules $destination/$rules
}

2
packages/bsp/common/etc/apt/apt.conf.d/02-armbian-postupdate
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@ -1 +1 @@
DPkg::Post-Invoke {"/usr/lib/armbian/armbian-apt-updates";};
DPkg::Post-Invoke {"test -x /usr/lib/armbian/armbian-apt-updates && /usr/lib/armbian/armbian-apt-updates || true";};

366
patch/kernel/archive/rockchip64-6.6/board-rocks0-0001-deviceTree.patch Normal file
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@ -0,0 +1,366 @@
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
From: Brent Roman <genosenosor@gmail.com>
Date: Wed, 7 Feb 2024 18:02:07 -0800
Subject: Added Linux device tree for Rock S0
Signed-off-by: Brent Roman <genosenosor@gmail.com>
---
arch/arm64/boot/dts/rockchip/rk3308-rock-s0.dts | 347 ++++++++++
1 files changed, 347 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk3308-rock-s0.dts b/arch/arm64/boot/dts/rockchip/rk3308-rock-s0.dts
new file mode 100644
index 000000000..aded16959
--- /dev/null
+++ b/arch/arm64/boot/dts/rockchip/rk3308-rock-s0.dts
@@ -0,0 +1,347 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Akash Gajjar <akash@openedev.com>
+ * Copyright (c) 2019 Jagan Teki <jagan@openedev.com>
+ * Revised: 2024 Brent Roman <brent@mbari.org>
+ */
+
+/dts-v1/;
+#include "rk3308.dtsi"
+
+/ {
+ model = "Radxa ROCK S0";
+ compatible = "radxa,rock-s0", "rockchip,rk3308";
+
+ chosen {
+ stdout-path = "serial0:1500000n8";
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 = <&green_led_gio>;
+
+ green-led {
+ label = "rock-s0:green:power";
+ gpios = <&gpio0 RK_PB6 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "heartbeat";
+ default-state = "on";
+ };
+ };
+
+ codec: acodec-sound {
+ compatible = "simple-audio-card";
+ simple-audio-card,format = "i2s";
+ simple-audio-card,name = "rockchip,rk3308-acodec";
+ simple-audio-card,mclk-fs = <256>;
+ simple-audio-card,codec-hp-det;
+ simple-audio-card,widgets =
+ "Headphone", "Headphones";
+ simple-audio-card,cpu {
+ sound-dai = <&i2s_8ch_2>;
+ };
+ simple-audio-card,codec {
+ sound-dai = <&acodec>;
+ };
+ };
+
+ sound {
+ compatible = "simple-audio-card";
+ simple-audio-card,format = "i2s";
+ simple-audio-card,mclk-fs = <256>;
+ simple-audio-card,name = "i2s_8ch_0";
+
+ simple-audio-card,dai-link@1 {
+ format = "i2s";
+ cpu {
+ sound-dai = <&i2s_8ch_0>;
+ };
+
+ codec {
+ sound-dai = <&pcm5102a>;
+ };
+ };
+ };
+
+ pcm5102a: pcm5102a {
+ #sound-dai-cells = <0>;
+ compatible = "ti,pcm5102a";
+ pcm510x,format = "i2s";
+ };
+
+ sdio_pwrseq: sdio-pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ pinctrl-0 = <&wifi_enable_h>;
+ pinctrl-names = "default";
+ /*
+ * On the module itself this is one of these (depending
+ * on the actual card populated):
+ * - SDIO_RESET_L_WL_REG_ON
+ * - PDN (power down when low)
+ */
+ reset-gpios = <&gpio0 RK_PA2 GPIO_ACTIVE_LOW>;
+ };
+
+ vcc_1v8: vcc-1v8 {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc_1v8";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ vin-supply = <&vcc_io>;
+ };
+
+ vcc_io: vcc-io {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc_io";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <&vcc5v0_sys>;
+ };
+
+ vcc_ddr: vcc-ddr {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc_ddr";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1500000>;
+ regulator-max-microvolt = <1500000>;
+ vin-supply = <&vcc5v0_sys>;
+ };
+
+ vcc5v0_otg: vcc5v0-otg {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpio = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&otg_vbus_drv>;
+ regulator-name = "vcc5v0_otg";
+ regulator-always-on;
+ vin-supply = <&vcc5v0_sys>;
+ };
+
+ vcc5v0_sys: vcc5v0-sys {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc5v0_sys";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ };
+
+ vdd_core: vdd-core {
+ compatible = "pwm-regulator";
+ pwms = <&pwm0 0 5000 1>;
+ pwm-supply = <&vcc5v0_sys>;
+ regulator-name = "vdd_core";
+ regulator-min-microvolt = <827000>;
+ regulator-max-microvolt = <1340000>;
+ regulator-init-microvolt = <1015000>;
+ regulator-settling-time-up-us = <250>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ vdd_log: vdd-log {
+ compatible = "regulator-fixed";
+ regulator-name = "vdd_log";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1050000>;
+ regulator-max-microvolt = <1050000>;
+ vin-supply = <&vcc5v0_sys>;
+ };
+
+ board_antenna: board-antenna {
+ status = "okay";
+ compatible = "regulator-fixed";
+ enable-active-low;
+ gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>;
+ regulator-always-on;
+ regulator-boot-on;
+ pinctrl-0 = <&ant_1>;
+ pinctrl-names = "default";
+ regulator-name = "board_antenna";
+ };
+};
+
+&acodec {
+ status = "okay";
+ #sound-dai-cells = <0>;
+};
+
+&cpu0 {
+ cpu-supply = <&vdd_core>;
+};
+
+&emmc {
+ cap-mmc-highspeed;
+ mmc-hs200-1_8v;
+ non-removable;
+ vmmc-supply = <&vcc_io>; //was vin-supply
+ status = "okay";
+};
+
+&sdmmc {
+ cap-mmc-highspeed;
+ cap-sd-highspeed;
+ disable-wp;
+ card-detect-delay = <800>;
+ status = "okay";
+};
+
+&sdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ cap-sd-highspeed;
+ cap-sdio-irq;
+ keep-power-in-suspend;
+ mmc-pwrseq = <&sdio_pwrseq>;
+ non-removable;
+ no-mmc;
+ status = "okay";
+
+ AP6212: wifi@1 {
+ compatible = "brcm,bcm4329-fmac";
+ reg = <1>;
+ interrupt-parent = <&gpio0>;
+ interrupts = <RK_PA0 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "host-wake";
+ pinctrl-names = "default";
+ pinctrl-0 = <&wifi_host_wake>;
+ };
+};
+
+&gmac {
+ phy-supply = <&vcc_io>;
+ clock_in_out = "output";
+ assigned-clocks = <&cru SCLK_MAC>;
+ assigned-clock-parents = <&cru SCLK_MAC_SRC>;
+ snps,reset-gpio = <&gpio0 RK_PA7 GPIO_ACTIVE_LOW>;
+ snps,reset-active-low;
+ snps,reset-delays-us = <0 50000 50000>;
+ status = "okay";
+};
+
+&i2s_8ch_0 {
+ assigned-clocks = <&cru SCLK_I2S0_8CH_RX>;
+ assigned-clock-parents = <&cru SCLK_I2S0_8CH_TX_MUX>;
+ rockchip,clk-trcm = <1>;
+ #sound-dai-cells = <0>;
+};
+
+&i2s_8ch_2 {
+ status = "okay";
+ #sound-dai-cells = <0>;
+};
+
+&pinctrl {
+ pinctrl-names = "default";
+ pinctrl-0 = <&rtc_32k>;
+
+ leds {
+ green_led_gio: green-led-gpio {
+ rockchip,pins = <0 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ usb {
+ otg_vbus_drv: otg-vbus-drv {
+ rockchip,pins = <0 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ sdio-pwrseq {
+ wifi_enable_h: wifi-enable-h {
+ rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ wifi {
+ wifi_host_wake: wifi-host-wake {
+ rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_down>;
+ };
+
+ };
+ antenna {
+ ant_1: ant-1 {
+ rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_down>;
+ };
+ };
+};
+
+&pwm0 {
+ status = "okay";
+ pinctrl-0 = <&pwm0_pin_pull_down>;
+};
+
+&saradc {
+ vref-supply = <&vcc_1v8>;
+ status = "okay";
+};
+
+&tsadc {
+ rockchip,hw-tshut-mode = <0>; /* 0:CRU */
+ rockchip,hw-tshut-polarity = <1>; /* 1:HIGH */
+ status = "okay";
+};
+
+&i2c1 {
+ status = "okay";
+};
+
+&spi2 {
+// status = "okay"; //conflicts with UART2
+ max-freq = <10000000>;
+};
+
+&uart0 {
+ status = "okay";
+};
+
+&uart2 {
+ status = "okay";
+};
+
+&uart4 {
+ status = "okay";
+
+ bluetooth {
+ compatible = "realtek,rtl8723bs-bt";
+ device-wake-gpios = <&gpio4 RK_PB3 GPIO_ACTIVE_HIGH>;
+ host-wake-gpios = <&gpio4 RK_PB4 GPIO_ACTIVE_HIGH>;
+ };
+};
+
+&u2phy {
+ status = "okay";
+
+ u2phy_host: host-port {
+ phy-supply = <&vcc5v0_otg>;
+ status = "okay";
+ };
+
+ u2phy_otg: otg-port {
+ status = "okay";
+ };
+};
+
+&usb20_otg {
+ status = "okay";
+};
+
+&usb_host_ehci {
+ status = "okay";
+};
+
+&usb_host_ohci{
+ status = "okay";
+};
+
+&wdt {
+ status = "okay";
+};
+
--
Created with Armbian build tools https://github.com/armbian/build

1
patch/kernel/archive/rockchip64-6.6/overlay/Makefile
View File

@ -1,5 +1,6 @@
# SPDX-License-Identifier: GPL-2.0
dtbo-$(CONFIG_ARCH_ROCKCHIP) += \
rk3308-s0-ext-antenna.dtbo \
rk3308-bs.dtbo rk3308-bs@1.3ghz.dtbo \
rk3308-emmc.dtbo \
rk3308-sdio@10mhz.dtbo rk3308-sdio@4mhz.dtbo \

13
patch/kernel/archive/rockchip64-6.6/overlay/README.rockchip-overlays
View File

@ -228,3 +228,16 @@ increases the SDIO clock to only 4Mhz, providing about 1MB/s WiFi throughput.
use this only if 10Mhz SDIO clock is unstable
Note that older mainline kernels cannot drive the SDIO clock faster than 10Mhz.
**********************************
Details for Rock S 0 overlays (7 Feb 2024):
Note thaat rk3308-bs* overlays crash the s0 for some strange reason
So, the max CPU clock is currently limited to 1ghz :-(
(under investigation...)
### rk3308-s0-ext-antenna
Select Rock S0's external WiFi antenna input
(instead of its internal WiFi antenna)
The internal antenna is very weak. Use an external one if convenient.

48
patch/kernel/archive/rockchip64-6.6/overlay/rk3308-s0-ext-antenna.dts Normal file
View File

@ -0,0 +1,48 @@
//Select Rock S0's external WiFi antenna input
//(instead of default internal WiFi antenna)
/dts-v1/;
/plugin/;
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/pinctrl/rockchip.h>
/ {
fragment@0 {
target-path = "/";
__overlay__ {
ext_antenna: ext-antenna {
status = "okay";
compatible = "regulator-fixed";
enable-active-low;
gpio = <&gpio0 RK_PA6 GPIO_ACTIVE_LOW>;
regulator-always-on;
regulator-boot-on;
pinctrl-0 = <&ant_2>;
pinctrl-names = "default";
regulator-name = "ext_antenna";
};
};
};
fragment@1 {
target = <&board_antenna>;
__overlay__ {
status = "disabled";
};
};
fragment@2 {
target = <&pinctrl>;
__overlay__ {
antenna {
ant_2: ant-2 {
rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_down>;
};
};
};
};
};

366
patch/kernel/archive/rockchip64-6.7/board-rocks0-0001-deviceTree.patch Normal file
View File

@ -0,0 +1,366 @@
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
From: Brent Roman <genosenosor@gmail.com>
Date: Wed, 7 Feb 2024 18:02:07 -0800
Subject: Added Linux device tree for Rock S0
Signed-off-by: Brent Roman <genosenosor@gmail.com>
---
arch/arm64/boot/dts/rockchip/rk3308-rock-s0.dts | 347 ++++++++++
1 files changed, 347 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk3308-rock-s0.dts b/arch/arm64/boot/dts/rockchip/rk3308-rock-s0.dts
new file mode 100644
index 000000000..aded16959
--- /dev/null
+++ b/arch/arm64/boot/dts/rockchip/rk3308-rock-s0.dts
@@ -0,0 +1,347 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Akash Gajjar <akash@openedev.com>
+ * Copyright (c) 2019 Jagan Teki <jagan@openedev.com>
+ * Revised: 2024 Brent Roman <brent@mbari.org>
+ */
+
+/dts-v1/;
+#include "rk3308.dtsi"
+
+/ {
+ model = "Radxa ROCK S0";
+ compatible = "radxa,rock-s0", "rockchip,rk3308";
+
+ chosen {
+ stdout-path = "serial0:1500000n8";
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 = <&green_led_gio>;
+
+ green-led {
+ label = "rock-s0:green:power";
+ gpios = <&gpio0 RK_PB6 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "heartbeat";
+ default-state = "on";
+ };
+ };
+
+ codec: acodec-sound {
+ compatible = "simple-audio-card";
+ simple-audio-card,format = "i2s";
+ simple-audio-card,name = "rockchip,rk3308-acodec";
+ simple-audio-card,mclk-fs = <256>;
+ simple-audio-card,codec-hp-det;
+ simple-audio-card,widgets =
+ "Headphone", "Headphones";
+ simple-audio-card,cpu {
+ sound-dai = <&i2s_8ch_2>;
+ };
+ simple-audio-card,codec {
+ sound-dai = <&acodec>;
+ };
+ };
+
+ sound {
+ compatible = "simple-audio-card";
+ simple-audio-card,format = "i2s";
+ simple-audio-card,mclk-fs = <256>;
+ simple-audio-card,name = "i2s_8ch_0";
+
+ simple-audio-card,dai-link@1 {
+ format = "i2s";
+ cpu {
+ sound-dai = <&i2s_8ch_0>;
+ };
+
+ codec {
+ sound-dai = <&pcm5102a>;
+ };
+ };
+ };
+
+ pcm5102a: pcm5102a {
+ #sound-dai-cells = <0>;
+ compatible = "ti,pcm5102a";
+ pcm510x,format = "i2s";
+ };
+
+ sdio_pwrseq: sdio-pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ pinctrl-0 = <&wifi_enable_h>;
+ pinctrl-names = "default";
+ /*
+ * On the module itself this is one of these (depending
+ * on the actual card populated):
+ * - SDIO_RESET_L_WL_REG_ON
+ * - PDN (power down when low)
+ */
+ reset-gpios = <&gpio0 RK_PA2 GPIO_ACTIVE_LOW>;
+ };
+
+ vcc_1v8: vcc-1v8 {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc_1v8";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ vin-supply = <&vcc_io>;
+ };
+
+ vcc_io: vcc-io {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc_io";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <&vcc5v0_sys>;
+ };
+
+ vcc_ddr: vcc-ddr {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc_ddr";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1500000>;
+ regulator-max-microvolt = <1500000>;
+ vin-supply = <&vcc5v0_sys>;
+ };
+
+ vcc5v0_otg: vcc5v0-otg {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpio = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&otg_vbus_drv>;
+ regulator-name = "vcc5v0_otg";
+ regulator-always-on;
+ vin-supply = <&vcc5v0_sys>;
+ };
+
+ vcc5v0_sys: vcc5v0-sys {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc5v0_sys";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ };
+
+ vdd_core: vdd-core {
+ compatible = "pwm-regulator";
+ pwms = <&pwm0 0 5000 1>;
+ pwm-supply = <&vcc5v0_sys>;
+ regulator-name = "vdd_core";
+ regulator-min-microvolt = <827000>;
+ regulator-max-microvolt = <1340000>;
+ regulator-init-microvolt = <1015000>;
+ regulator-settling-time-up-us = <250>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ vdd_log: vdd-log {
+ compatible = "regulator-fixed";
+ regulator-name = "vdd_log";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1050000>;
+ regulator-max-microvolt = <1050000>;
+ vin-supply = <&vcc5v0_sys>;
+ };
+
+ board_antenna: board-antenna {
+ status = "okay";
+ compatible = "regulator-fixed";
+ enable-active-low;
+ gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>;
+ regulator-always-on;
+ regulator-boot-on;
+ pinctrl-0 = <&ant_1>;
+ pinctrl-names = "default";
+ regulator-name = "board_antenna";
+ };
+};
+
+&acodec {
+ status = "okay";
+ #sound-dai-cells = <0>;
+};
+
+&cpu0 {
+ cpu-supply = <&vdd_core>;
+};
+
+&emmc {
+ cap-mmc-highspeed;
+ mmc-hs200-1_8v;
+ non-removable;
+ vmmc-supply = <&vcc_io>; //was vin-supply
+ status = "okay";
+};
+
+&sdmmc {
+ cap-mmc-highspeed;
+ cap-sd-highspeed;
+ disable-wp;
+ card-detect-delay = <800>;
+ status = "okay";
+};
+
+&sdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ cap-sd-highspeed;
+ cap-sdio-irq;
+ keep-power-in-suspend;
+ mmc-pwrseq = <&sdio_pwrseq>;
+ non-removable;
+ no-mmc;
+ status = "okay";
+
+ AP6212: wifi@1 {
+ compatible = "brcm,bcm4329-fmac";
+ reg = <1>;
+ interrupt-parent = <&gpio0>;
+ interrupts = <RK_PA0 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "host-wake";
+ pinctrl-names = "default";
+ pinctrl-0 = <&wifi_host_wake>;
+ };
+};
+
+&gmac {
+ phy-supply = <&vcc_io>;
+ clock_in_out = "output";
+ assigned-clocks = <&cru SCLK_MAC>;
+ assigned-clock-parents = <&cru SCLK_MAC_SRC>;
+ snps,reset-gpio = <&gpio0 RK_PA7 GPIO_ACTIVE_LOW>;
+ snps,reset-active-low;
+ snps,reset-delays-us = <0 50000 50000>;
+ status = "okay";
+};
+
+&i2s_8ch_0 {
+ assigned-clocks = <&cru SCLK_I2S0_8CH_RX>;
+ assigned-clock-parents = <&cru SCLK_I2S0_8CH_TX_MUX>;
+ rockchip,clk-trcm = <1>;
+ #sound-dai-cells = <0>;
+};
+
+&i2s_8ch_2 {
+ status = "okay";
+ #sound-dai-cells = <0>;
+};
+
+&pinctrl {
+ pinctrl-names = "default";
+ pinctrl-0 = <&rtc_32k>;
+
+ leds {
+ green_led_gio: green-led-gpio {
+ rockchip,pins = <0 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ usb {
+ otg_vbus_drv: otg-vbus-drv {
+ rockchip,pins = <0 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ sdio-pwrseq {
+ wifi_enable_h: wifi-enable-h {
+ rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ wifi {
+ wifi_host_wake: wifi-host-wake {
+ rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_down>;
+ };
+
+ };
+ antenna {
+ ant_1: ant-1 {
+ rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_down>;
+ };
+ };
+};
+
+&pwm0 {
+ status = "okay";
+ pinctrl-0 = <&pwm0_pin_pull_down>;
+};
+
+&saradc {
+ vref-supply = <&vcc_1v8>;
+ status = "okay";
+};
+
+&tsadc {
+ rockchip,hw-tshut-mode = <0>; /* 0:CRU */
+ rockchip,hw-tshut-polarity = <1>; /* 1:HIGH */
+ status = "okay";
+};
+
+&i2c1 {
+ status = "okay";
+};
+
+&spi2 {
+// status = "okay"; //conflicts with UART2
+ max-freq = <10000000>;
+};
+
+&uart0 {
+ status = "okay";
+};
+
+&uart2 {
+ status = "okay";
+};
+
+&uart4 {
+ status = "okay";
+
+ bluetooth {
+ compatible = "realtek,rtl8723bs-bt";
+ device-wake-gpios = <&gpio4 RK_PB3 GPIO_ACTIVE_HIGH>;
+ host-wake-gpios = <&gpio4 RK_PB4 GPIO_ACTIVE_HIGH>;
+ };
+};
+
+&u2phy {
+ status = "okay";
+
+ u2phy_host: host-port {
+ phy-supply = <&vcc5v0_otg>;
+ status = "okay";
+ };
+
+ u2phy_otg: otg-port {
+ status = "okay";
+ };
+};
+
+&usb20_otg {
+ status = "okay";
+};
+
+&usb_host_ehci {
+ status = "okay";
+};
+
+&usb_host_ohci{
+ status = "okay";
+};
+
+&wdt {
+ status = "okay";
+};
+
--
Created with Armbian build tools https://github.com/armbian/build

1
patch/kernel/archive/rockchip64-6.7/overlay/Makefile
View File

@ -1,5 +1,6 @@
# SPDX-License-Identifier: GPL-2.0
dtbo-$(CONFIG_ARCH_ROCKCHIP) += \
rk3308-s0-ext-antenna.dtbo \
rk3308-bs.dtbo rk3308-bs@1.3ghz.dtbo \
rk3308-emmc.dtbo \
rk3308-sdio@10mhz.dtbo rk3308-sdio@4mhz.dtbo \

48
patch/kernel/archive/rockchip64-6.7/overlay/rk3308-s0-ext-antenna.dts Normal file
View File

@ -0,0 +1,48 @@
//Select Rock S0's external WiFi antenna input
//(instead of default internal WiFi antenna)
/dts-v1/;
/plugin/;
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/pinctrl/rockchip.h>
/ {
fragment@0 {
target-path = "/";
__overlay__ {
ext_antenna: ext-antenna {
status = "okay";
compatible = "regulator-fixed";
enable-active-low;
gpio = <&gpio0 RK_PA6 GPIO_ACTIVE_LOW>;
regulator-always-on;
regulator-boot-on;
pinctrl-0 = <&ant_2>;
pinctrl-names = "default";
regulator-name = "ext_antenna";
};
};
};
fragment@1 {
target = <&board_antenna>;
__overlay__ {
status = "disabled";
};
};
fragment@2 {
target = <&pinctrl>;
__overlay__ {
antenna {
ant_2: ant-2 {
rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_down>;
};
};
};
};
};

355
patch/u-boot/u-boot-rockchip64-v2022.04/board_rock-s0/add-board-rock-s0.patch Normal file
View File

@ -0,0 +1,355 @@
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
From: Brent Roman <brent@mbari.org>
Date: Mon, 5 Feb 2024 14:21:27 -0800
Subject: Initial Armbian support for Radxa Rock S0
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 11dcac8fea..0b46fec9b5 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -116,11 +116,12 @@ dtb-$(CONFIG_ROCKCHIP_RK3288) += \
rk3288-vyasa.dtb
dtb-$(CONFIG_ROCKCHIP_RK3308) += \
rk3308-evb.dtb \
rk3308-roc-cc.dtb \
- rk3308-rock-pi-s.dtb
+ rk3308-rock-pi-s.dtb \
+ rk3308-rock-s0.dtb
dtb-$(CONFIG_ROCKCHIP_RK3328) += \
rk3328-evb.dtb \
rk3328-nanopi-r2s.dtb \
rk3328-orangepi-r1-plus.dtb \
diff -u a/configs/rock-s0-rk3308_defconfig b/configs/rock-s0-rk3308_defconfig
--- /dev/null
+++ b/configs/rock-s0-rk3308_defconfig
@@ -0,0 +1,105 @@
+CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
+CONFIG_ARCH_ROCKCHIP=y
+CONFIG_SYS_TEXT_BASE=0x00600000
+CONFIG_SPL_GPIO_SUPPORT=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_ROCKCHIP_RK3308=y
+CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x0
+CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
+CONFIG_TARGET_EVB_RK3308=y
+CONFIG_SPL_STACK_R_ADDR=0xc00000
+CONFIG_PRE_CON_BUF_ADDR=0x0f200000
+CONFIG_DEBUG_UART_BASE=0xFF0A0000
+CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_SPL_LIBDISK_SUPPORT=y
+CONFIG_DEFAULT_DEVICE_TREE="rk3308-rock-s0"
+CONFIG_DEBUG_UART=y
+CONFIG_SYS_LOAD_ADDR=0x800800
+CONFIG_BAUDRATE=1500000
+# CONFIG_LOCALVERSION_AUTO is not set
+CONFIG_ANDROID_BOOT_IMAGE=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_PRE_CONSOLE_BUFFER=y
+CONFIG_CONSOLE_MUX=y
+CONFIG_SYS_CONSOLE_ENV_OVERWRITE=y
+# CONFIG_SYS_DEVICE_NULLDEV is not set
+CONFIG_DEFAULT_FDT_FILE="rk3308-rock-s0.dtb"
+CONFIG_MISC_INIT_R=y
+CONFIG_VERSION_VARIABLE=y
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_BOARD_TYPES=y
+CONFIG_SPL_STACK_R=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION=y
+CONFIG_CMD_CONFIG=y
+# CONFIG_CMD_ELF is not set
+# CONFIG_CMD_IMI is not set
+# CONFIG_CMD_XIMG is not set
+CONFIG_CMD_GPT=y
+# CONFIG_CMD_LOADB is not set
+# CONFIG_CMD_LOADS is not set
+CONFIG_CMD_MMC=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+# CONFIG_CMD_ITEST is not set
+# CONFIG_CMD_SETEXPR is not set
+# CONFIG_ISO_PARTITION is not set
+CONFIG_EFI_PARTITION_ENTRIES_NUMBERS=64
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_OF_LIVE=y
+CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_CLK=y
+# CONFIG_USB_FUNCTION_FASTBOOT is not set
+CONFIG_SPL_FIRMWARE=y
+CONFIG_ROCKCHIP_GPIO=y
+CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_LED=y
+CONFIG_LED_GPIO=y
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_ROCKCHIP=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_ROCKCHIP=y
+CONFIG_PHY_REALTEK=y
+CONFIG_DM_ETH=y
+CONFIG_PHY_GIGE=y
+CONFIG_ETH_DESIGNWARE=y
+CONFIG_RGMII=y
+CONFIG_MII=y
+CONFIG_GMAC_ROCKCHIP=y
+CONFIG_PHY_ROCKCHIP_INNO_USB2=y
+CONFIG_PINCTRL=y
+CONFIG_DM_PMIC=y
+CONFIG_PMIC_RK8XX=y
+CONFIG_REGULATOR_PWM=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_PWM_ROCKCHIP=y
+CONFIG_RAM=y
+CONFIG_ROCKCHIP_SDRAM_COMMON=y
+CONFIG_DM_RESET=y
+CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_ROCKCHIP_SPI=y
+CONFIG_SYSRESET=y
+CONFIG_USB=y
+CONFIG_DM_USB_GADGET=y
+CONFIG_SPL_DM_USB_GADGET=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_GENERIC=y
+CONFIG_USB_DWC2=y
+CONFIG_USB_DWC3=y
+CONFIG_ROCKCHIP_USB2_PHY=y
+CONFIG_USB_KEYBOARD=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DWC2_OTG=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_EXT4_WRITE=y
+CONFIG_SPL_TINY_MEMSET=y
+CONFIG_LZO=y
+CONFIG_ERRNO_STR=y
+# CONFIG_EFI_LOADER is not set
diff -u a/arch/arm/dts/rk3308-rock-s0.dts b/arch/arm/dts/rk3308-rock-s0.dts
--- /dev/null
+++ b/arch/arm/dts/rk3308-rock-s0.dts
@@ -0,0 +1,219 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Akash Gajjar <akash@openedev.com>
+ * Copyright (c) 2023 Jagan Teki <jagan@openedev.com>
+ * Revised: 2/5/2024 Brent Roman <brent@mbari.org>
+ */
+
+/dts-v1/;
+#include "rk3308.dtsi"
+
+/ {
+ model = "Radxa ROCK S0";
+ compatible = "radxa,rock-s0", "rockchip,rk3308";
+
+ aliases {
+ ethernet0 = &mac;
+ mmc0 = &emmc;
+ mmc1 = &sdmmc;
+ };
+
+ chosen {
+ stdout-path = "serial0:1500000n8";
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 = <&heartbeat_led_gpio>;
+ };
+
+
+ sdio_pwrseq: sdio-pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ pinctrl-0 = <&wifi_enable_h>;
+ pinctrl-names = "default";
+ reset-gpios = <&gpio0 RK_PA2 GPIO_ACTIVE_LOW>;
+ };
+
+ vcc_1v8: vcc-1v8 {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc_1v8";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ vin-supply = <&vcc_io>;
+ };
+
+ vcc_io: vcc-io {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc_io";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <&vcc5v0_sys>;
+ };
+
+ vcc_ddr: vcc-ddr {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc_ddr";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1500000>;
+ regulator-max-microvolt = <1500000>;
+ vin-supply = <&vcc5v0_sys>;
+ };
+
+ vcc5v0_otg: vcc5v0-otg {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpio = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&otg_vbus_drv>;
+ regulator-name = "vcc5v0_otg";
+ regulator-always-on;
+ vin-supply = <&vcc5v0_sys>;
+ };
+
+ vcc5v0_sys: vcc5v0-sys {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc5v0_sys";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ };
+
+ vdd_core: vdd-core {
+ compatible = "pwm-regulator";
+ pwms = <&pwm0 0 5000 1>;
+ pwm-supply = <&vcc5v0_sys>;
+ regulator-name = "vdd_core";
+ regulator-min-microvolt = <827000>;
+ regulator-max-microvolt = <1340000>;
+ regulator-init-microvolt = <1015000>;
+ regulator-settling-time-up-us = <250>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ vdd_log: vdd-log {
+ compatible = "regulator-fixed";
+ regulator-name = "vdd_log";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1050000>;
+ regulator-max-microvolt = <1050000>;
+ vin-supply = <&vcc5v0_sys>;
+ };
+};
+
+&cpu0 {
+ cpu-supply = <&vdd_core>;
+};
+
+&emmc {
+ cap-mmc-highspeed;
+ mmc-hs200-1_8v;
+ non-removable;
+ vmmc-supply = <&vcc_io>; //was vin-supply
+ status = "okay";
+};
+
+&mac {
+ clock_in_out = "output";
+ phy-supply = <&vcc_io>;
+ assigned-clocks = <&cru SCLK_MAC>;
+ assigned-clock-parents = <&cru SCLK_MAC_SRC>;
+ snps,reset-gpio = <&gpio0 RK_PA7 GPIO_ACTIVE_LOW>;
+ snps,reset-active-low;
+ snps,reset-delays-us = <0 50000 50000>;
+ status = "okay";
+};
+
+&i2c1 {
+ status = "okay";
+};
+
+&spi2 {
+ status = "okay";
+ max-freq = <10000000>;
+};
+
+&pinctrl {
+ pinctrl-names = "default";
+ pinctrl-0 = <&rtc_32k>;
+
+ leds {
+ heartbeat_led_gpio: heartbeat-led-gpio {
+ rockchip,pins = <0 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ usb {
+ otg_vbus_drv: otg-vbus-drv {
+ rockchip,pins = <0 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ sdmmc {
+ sdmmc_pwren: sdmmc-pwren {
+ rockchip,pins =
+ <4 RK_PD6 0 &pcfg_pull_down>;
+ };
+ };
+
+ sdio-pwrseq {
+ wifi_enable_h: wifi-enable-h {
+ rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
+ wifi_host_wake: wifi-host-wake {
+ rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_down>;
+ };
+ };
+};
+
+&pwm0 {
+ status = "okay";
+ pinctrl-0 = <&pwm0_pin_pull_down>;
+};
+
+&saradc {
+ vref-supply = <&vcc_1v8>;
+ status = "okay";
+};
+
+&sdmmc {
+ cap-mmc-highspeed;
+ cap-sd-highspeed;
+ disable-wp;
+ sd-uhs-sdr12;
+ sd-uhs-sdr25;
+ sd-uhs-sdr50;
+ sd-uhs-sdr104;
+ pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_det &sdmmc_pwren &sdmmc_bus4>;
+ status = "okay";
+};
+
+&uart0 {
+ uboot,dm-pre-reloc;
+ clock-frequency = <24000000>;
+ status = "okay";
+};
+
+&uart2 {
+ status = "okay";
+};
+
+&uart4 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart4_xfer &uart4_rts &uart4_cts>;
+ status = "okay";
+};
+
+&wdt {
+ status = "okay";
+};