mirror of https://github.com/armbian/build.git
SpacemiT: BananaPi F3: `update to BL v1.0.8`
Legacy: use TAG instead of BRANCH (gives us more control) Current: update DTS files Current: add needed patches up to v1.0.8 Fixup bluetooth node and disable by default (half broke anyway) Misc fixups to bananapif3.wip and spacemit.conf file Signed-off-by: Patrick Yavitz <pyavitz@armbian.com>
This commit is contained in:
Patrick Yavitz
c0rnelius
parent
36016c8525
commit
c5be5a8537
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@ -28,8 +28,6 @@ function post_family_tweaks_bsp__bananapi_f3_extras() {
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display_alert "$BOARD" "Force load wireless" "info"
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run_host_command_logged mkdir -pv "${destination}"/etc/modprobe.d
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run_host_command_logged echo "options 8852bs rtw_drv_log_level=0 rtw_phl_log_level=0" > "${destination}"/etc/modprobe.d/50-8852bs.conf
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run_host_command_logged mkdir -pv "${destination}"/etc/modules-load.d
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run_host_command_logged echo "8852bs" > "${destination}"/etc/modules-load.d/${BOARD}.conf
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}
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@ -38,7 +38,7 @@ case "${BRANCH}" in
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legacy)
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# Kernel
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declare -g KERNELSOURCE='https://gitee.com/bianbu-linux/linux-6.1.git'
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declare -g KERNELBRANCH='branch:bl-v1.0.y'
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declare -g KERNELBRANCH='tag:v1.0.8'
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declare -g KERNEL_MAJOR_MINOR="6.1"
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declare -g LINUXCONFIG="linux-${LINUXFAMILY}-${BRANCH}"
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declare -g KERNELPATCHDIR="${LINUXFAMILY}-legacy-${KERNEL_MAJOR_MINOR}" # Needed as long as both legacy and current are 6.1 kernels
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@ -65,7 +65,7 @@ function custom_kernel_config__spacemit_k1_firmware() {
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}
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pre_prepare_partitions() {
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declare -g OFFSET="100"
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declare -g OFFSET="4"
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declare -g IMAGE_PARTITION_TABLE="msdos"
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}
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File diff suppressed because it is too large
Load Diff
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@ -0,0 +1,443 @@
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From 05bebc19949413beb180f86c3efb10957713658a Mon Sep 17 00:00:00 2001
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From: Patrick Yavitz <pyavitz@armbian.com>
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Date: Tue, 16 Jul 2024 08:47:05 -0400
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Subject: [PATCH] update to v1.0.8
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source: https://gitee.com/bianbu-linux/linux-6.1
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Signed-off-by: James Deng <james.deng@spacemit.com>
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Signed-off-by: Patrick Yavitz <pyavitz@armbian.com>
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---
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drivers/cpufreq/spacemit-cpufreq.c | 35 +++-
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drivers/crypto/spacemit/spacemit_ce_engine.c | 13 +-
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drivers/i2c/busses/i2c-k1x.c | 5 +-
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drivers/pwm/pwm-pxa.c | 6 +-
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.../soc/spacemit/pm_domain/k1x-pm_domain.c | 8 +
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drivers/usb/phy/Makefile | 2 +-
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scripts/package/generic | 16 ++
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sound/soc/spacemit/spacemit-snd-pcm-dma.c | 150 +++++++-----------
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8 files changed, 124 insertions(+), 111 deletions(-)
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create mode 100644 scripts/package/generic
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diff --git a/drivers/cpufreq/spacemit-cpufreq.c b/drivers/cpufreq/spacemit-cpufreq.c
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index 52d40d7f25fe..ce81b344a1c6 100644
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--- a/drivers/cpufreq/spacemit-cpufreq.c
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+++ b/drivers/cpufreq/spacemit-cpufreq.c
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@@ -36,9 +36,15 @@ of_hotplug_cooling_register(struct cpufreq_policy *policy);
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#define TURBO_FREQUENCY (1600000000)
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#define STABLE_FREQUENCY (1200000000)
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-#define FILTER_POINTS (140)
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+
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+#define FILTER_POINTS_0 (135)
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+#define FILTER_POINTS_1 (142)
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+
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#define FREQ_TABLE_0 (0)
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#define FREQ_TABLE_1 (1)
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+#define FREQ_TABLE_2 (2)
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+
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+#define PRODUCT_ID_M1 (0x36070000)
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static int spacemit_policy_notifier(struct notifier_block *nb,
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unsigned long event, void *data)
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@@ -390,7 +396,9 @@ static int spacemit_dt_cpufreq_pre_probe(struct platform_device *pdev)
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{
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int cpu;
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struct device_node *cpus;
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+ struct device_node *product_id, *wafer_id;
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u32 prop = 0;
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+ u32 product_prop, wafer_prop;
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if (strncmp(pdev->name, "cpufreq-dt", 10) != 0)
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return 0;
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@@ -400,8 +408,29 @@ static int spacemit_dt_cpufreq_pre_probe(struct platform_device *pdev)
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pr_info("Spacemit Platform with no 'svt-dro' in DTS, using defualt frequency Table0\n");
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}
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- for_each_possible_cpu(cpu) {
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- spacemit_dt_cpufreq_pre_early_init(&pdev->dev, cpu, prop >= FILTER_POINTS ? FREQ_TABLE_1 : FREQ_TABLE_0);
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+ product_id = of_find_node_by_path("/");
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+ if (!product_id || of_property_read_u32(product_id, "product-id", &product_prop)) {
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+ pr_info("Spacemit Platform with no 'product-id' in DTS\n");
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+ }
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+
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+ wafer_id = of_find_node_by_path("/");
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+ if (!wafer_id || of_property_read_u32(product_id, "wafer-id", &wafer_prop)) {
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+ pr_info("Spacemit Platform with no 'product-id' in DTS\n");
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+ }
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+
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+ if ((wafer_prop << 16 | product_prop) == PRODUCT_ID_M1) {
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+ for_each_possible_cpu(cpu) {
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+ if (prop <= FILTER_POINTS_0)
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+ spacemit_dt_cpufreq_pre_early_init(&pdev->dev, cpu, FREQ_TABLE_0);
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+ else if (prop <= FILTER_POINTS_1)
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+ spacemit_dt_cpufreq_pre_early_init(&pdev->dev, cpu, FREQ_TABLE_1);
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+ else
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+ spacemit_dt_cpufreq_pre_early_init(&pdev->dev, cpu, FREQ_TABLE_2);
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+ }
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+ } else {
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+ for_each_possible_cpu(cpu) {
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+ spacemit_dt_cpufreq_pre_early_init(&pdev->dev, cpu, FREQ_TABLE_0);
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+ }
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}
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return 0;
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diff --git a/drivers/crypto/spacemit/spacemit_ce_engine.c b/drivers/crypto/spacemit/spacemit_ce_engine.c
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index 8623eb4843dd..8ebdd842532b 100644
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--- a/drivers/crypto/spacemit/spacemit_ce_engine.c
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+++ b/drivers/crypto/spacemit/spacemit_ce_engine.c
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@@ -1733,6 +1733,12 @@ static int crypto_engine_probe(struct platform_device *pdev)
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return -ENODEV;
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}
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+ ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32));
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+ if (ret) {
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+ dev_err(dev, "Unable to set dma mask\n");
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+ return ret;
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+ }
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+
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in_buffer = dma_alloc_noncoherent(dev, SPACEMIT_AES_BUFFER_LEN, &dma_addr_in, DMA_TO_DEVICE, GFP_KERNEL);
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out_buffer = dma_alloc_noncoherent(dev, SPACEMIT_AES_BUFFER_LEN, &dma_addr_out, DMA_FROM_DEVICE, GFP_KERNEL);
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ctrl = kmalloc(sizeof(struct aes_clk_reset_ctrl), GFP_KERNEL);
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@@ -1829,13 +1835,6 @@ static int crypto_engine_probe(struct platform_device *pdev)
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return ret;
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}
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-
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- ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32));
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- if (ret) {
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- dev_err(dev, "Unable to set dma mask\n");
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- return ret;
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- }
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-
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#ifdef CONFIG_SPACEMIT_CRYPTO_SELF_TEST
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ce_aes_test(num_engines);
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#endif
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diff --git a/drivers/i2c/busses/i2c-k1x.c b/drivers/i2c/busses/i2c-k1x.c
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index eda79cfb2422..f0b6e9d36fe3 100644
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--- a/drivers/i2c/busses/i2c-k1x.c
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+++ b/drivers/i2c/busses/i2c-k1x.c
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@@ -1245,15 +1245,12 @@ spacemit_i2c_xfer(struct i2c_adapter *adapt, struct i2c_msg msgs[], int num)
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* software power down command to pmic via i2c interface
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* with local irq disabled, so just enter PIO mode at once
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*/
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- if (unlikely(irqs_disabled()
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+ if (unlikely(spacemit_i2c_restart_notify == true
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#ifdef CONFIG_DEBUG_FS
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|| spacemit_i2c->dbgfs_mode == SPACEMIT_I2C_MODE_PIO
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#endif
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)) {
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- if(!spacemit_i2c_restart_notify)
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- dev_warn(spacemit_i2c->dev, "%s: i2c transfer called with irq off!\n", __func__);
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-
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spacemit_i2c->msgs = msgs;
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spacemit_i2c->num = num;
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diff --git a/drivers/pwm/pwm-pxa.c b/drivers/pwm/pwm-pxa.c
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index 4fd778f7a608..a571c207c1a9 100644
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--- a/drivers/pwm/pwm-pxa.c
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+++ b/drivers/pwm/pwm-pxa.c
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@@ -308,10 +308,6 @@ static struct platform_driver pwm_driver = {
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.id_table = pwm_id_table,
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};
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-static int k1x_pwm_driver_init(void)
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-{
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- return platform_driver_register(&pwm_driver);
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-}
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-late_initcall_sync(k1x_pwm_driver_init);
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+module_platform_driver(pwm_driver);
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MODULE_LICENSE("GPL v2");
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diff --git a/drivers/soc/spacemit/pm_domain/k1x-pm_domain.c b/drivers/soc/spacemit/pm_domain/k1x-pm_domain.c
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index de03e2e2e5d9..5cb23eb36019 100644
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--- a/drivers/soc/spacemit/pm_domain/k1x-pm_domain.c
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+++ b/drivers/soc/spacemit/pm_domain/k1x-pm_domain.c
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@@ -45,6 +45,9 @@
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/* gpio */
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#define WAKEUP_SOURCE_WAKEUP_2 2
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+/* usb & others */
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+#define WAKEUP_SOURCE_WAKEUP_5 5
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+
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#define PM_QOS_BLOCK_C1 0x0 /* core wfi */
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#define PM_QOS_BLOCK_C2 0x2 /* core power off */
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#define PM_QOS_BLOCK_M2 0x6 /* core l2 off */
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@@ -818,6 +821,11 @@ static int acpr_per_suspend(void)
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apcr_per |= (1 << WAKEUP_SOURCE_WAKEUP_2);
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regmap_write(gpmu->regmap[MPMU_REGMAP_INDEX], MPMU_AWUCRM_REG, apcr_per);
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+ /* enable usb/rcpu/ap2audio */
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+ regmap_read(gpmu->regmap[MPMU_REGMAP_INDEX], MPMU_AWUCRM_REG, &apcr_per);
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+ apcr_per |= (1 << WAKEUP_SOURCE_WAKEUP_5);
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+ regmap_write(gpmu->regmap[MPMU_REGMAP_INDEX], MPMU_AWUCRM_REG, apcr_per);
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+
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return 0;
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}
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diff --git a/drivers/usb/phy/Makefile b/drivers/usb/phy/Makefile
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index 01b40aa3f8b7..b6d549df71f4 100644
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--- a/drivers/usb/phy/Makefile
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+++ b/drivers/usb/phy/Makefile
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@@ -25,5 +25,5 @@ obj-$(CONFIG_USB_ULPI) += phy-ulpi.o
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obj-$(CONFIG_USB_ULPI_VIEWPORT) += phy-ulpi-viewport.o
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obj-$(CONFIG_KEYSTONE_USB_PHY) += phy-keystone.o
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obj-$(CONFIG_JZ4770_PHY) += phy-jz4770.o
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-obj-$(CONFIG_USB_K1XCI_OTG) += phy-k1x-ci-otg.o
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obj-$(CONFIG_K1XCI_USB2_PHY) += phy-k1x-ci-usb2.o
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+obj-$(CONFIG_USB_K1XCI_OTG) += phy-k1x-ci-otg.o
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diff --git a/scripts/package/generic b/scripts/package/generic
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new file mode 100644
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index 000000000000..3b0286cd0e5a
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--- /dev/null
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+++ b/scripts/package/generic
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@@ -0,0 +1,16 @@
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+#!/bin/bash
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+full_version=`uname -r`
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+
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+# First check for a fully qualified version.
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+this="/usr/lib/linux-tools/$full_version/`basename $0`"
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+if [ -f "$this" ]; then
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+ exec "$this" "$@"
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+fi
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+
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+# Give them a hint as to what to install.
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+echo "WARNING: `basename $0` not found for kernel $full_version" >&2
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+echo "" >&2
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+echo " You may need to install the following packages for this specific kernel:" >&2
|
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+echo " linux-tools-$full_version" >&2
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+
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+exit 2
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\ No newline at end of file
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diff --git a/sound/soc/spacemit/spacemit-snd-pcm-dma.c b/sound/soc/spacemit/spacemit-snd-pcm-dma.c
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index 4dbd81098f7f..192927837cf6 100644
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--- a/sound/soc/spacemit/spacemit-snd-pcm-dma.c
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+++ b/sound/soc/spacemit/spacemit-snd-pcm-dma.c
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@@ -34,32 +34,18 @@
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#define HDMI_TXDATA 0x80
|
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#define HDMI_PERIOD_SIZE 480
|
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|
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-#define L_CH 0
|
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-#define R_CH 1
|
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#define SAMPLE_PRESENT_FLAG_OFFSET 31
|
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#define AUDIO_FRAME_START_BIT_OFFSET 30
|
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-#define SAMPLE_FLAT_BIT_OFFSET 29
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-#define NOT_USED_OFFSET 28
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#define PARITY_BIT_OFFSET 27
|
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#define CHANNEL_STATUS_OFFSET 26
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-#define USER_DATA_OFFSET 25
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#define VALID_OFFSET 24
|
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-#define IEC958_AES0_CONSUMER (0<<0) /* 0 = consumer, 1 = professional */
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-#define IEC958_AES0_AUDIO (0<<1) /* 0 = audio, 1 = non-audio */
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-#define IEC958_AES3_CON_FS_48000 (2<<0) /* 48kHz */
|
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-#define IEC958_AES0_CON_NOT_COPYRIGHT (1<<2) /* 0 = copyright, 1 = not copyright */
|
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-#define IEC958_AES0_CON_EMPHASIS_NONE (0<<3) /* none emphasis */
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-#define IEC958_AES1_CON_GENERAL (0x00)
|
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-#define IEC958_AES2_CON_SOURCE_UNSPEC (0<<0) /* unspecified */
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-#define IEC958_AES2_CON_CHANNEL_UNSPEC (0<<4) /* unspecified */
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-#define IEC958_AES3_CON_CLOCK_1000PPM (0<<4) /* 1000 ppm */
|
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-#define IEC958_AES4_CON_WORDLEN_24_20 (5<<1) /* 24-bit or 20-bit */
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-#define IEC958_AES4_CON_MAX_WORDLEN_24 (1<<0) /* 0 = 20-bit, 1 = 24-bit */
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-
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#define CS_CTRL1 ((1 << SAMPLE_PRESENT_FLAG_OFFSET) | (1 << AUDIO_FRAME_START_BIT_OFFSET))
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#define CS_CTRL2 ((1 << SAMPLE_PRESENT_FLAG_OFFSET) | (0 << AUDIO_FRAME_START_BIT_OFFSET))
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+#define CS_SAMPLING_FREQUENCY 25
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+#define CS_MAX_SAMPLE_WORD 32
|
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+
|
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#define P2(n) n, n^1, n^1, n
|
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#define P4(n) P2(n), P2(n^1), P2(n^1), P2(n)
|
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#define P6(n) P4(n), P4(n^1), P4(n^1), P4(n)
|
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@@ -96,11 +82,9 @@ struct hdmi_codec_priv {
|
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uint32_t srate;
|
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uint32_t channels;
|
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uint8_t iec_offset;
|
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- uint8_t ch_sn;
|
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- uint8_t cs[24];
|
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};
|
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|
||||
-struct hdmi_codec_priv hdmi_ptr = {0};
|
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+static struct hdmi_codec_priv hdmi_ptr = {0};
|
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static const bool ParityTable256[256] =
|
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{
|
||||
P6(0), P6(1), P6(1), P6(0)
|
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@@ -567,8 +551,12 @@ static int spacemit_snd_pcm_trigger(struct snd_soc_component *component, struct
|
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case SNDRV_PCM_TRIGGER_SUSPEND:
|
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if (runtime->info & SNDRV_PCM_INFO_PAUSE)
|
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dmaengine_pause(dmadata->dma_chan);
|
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- else
|
||||
+ else {
|
||||
dmaengine_terminate_async(dmadata->dma_chan);
|
||||
+ dmadata->playback_data = 0;
|
||||
+ dmadata->pos = 0;
|
||||
+ spacemit_update_stream_status(dev, dmadata->stream, false);
|
||||
+ }
|
||||
break;
|
||||
case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
|
||||
case SNDRV_PCM_TRIGGER_RESUME:
|
||||
@@ -623,18 +611,7 @@ spacemit_snd_pcm_hdmi_pointer(struct snd_soc_component *component, struct snd_pc
|
||||
struct spacemit_snd_dmadata *dmadata = substream->runtime->private_data;
|
||||
return bytes_to_frames(substream->runtime, dmadata->pos);
|
||||
}
|
||||
-static void hdmi_create_cs(struct hdmi_codec_priv *hdmi_priv)
|
||||
-{
|
||||
- uint8_t *cs;
|
||||
- memset(hdmi_priv->cs, 0, sizeof(hdmi_priv->cs));
|
||||
- cs = hdmi_priv->cs;
|
||||
- cs[0] = IEC958_AES0_CONSUMER | IEC958_AES0_AUDIO | IEC958_AES0_CON_NOT_COPYRIGHT | IEC958_AES0_CON_EMPHASIS_NONE;
|
||||
- cs[1] = IEC958_AES1_CON_GENERAL;
|
||||
- cs[2] = IEC958_AES2_CON_SOURCE_UNSPEC | IEC958_AES2_CON_CHANNEL_UNSPEC;
|
||||
- cs[3] = IEC958_AES3_CON_CLOCK_1000PPM | IEC958_AES3_CON_FS_48000;
|
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- cs[4] = IEC958_AES4_CON_WORDLEN_24_20 | IEC958_AES4_CON_MAX_WORDLEN_24; //24bits
|
||||
|
||||
-}
|
||||
static int spacemit_snd_pcm_open(struct snd_soc_component *component, struct snd_pcm_substream *substream)
|
||||
{
|
||||
int ret = 0;
|
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@@ -677,10 +654,8 @@ static int spacemit_snd_pcm_open(struct snd_soc_component *component, struct snd
|
||||
substream->runtime->private_data = dmadata;
|
||||
|
||||
if (dmadata->dma_id == DMA_HDMI) {
|
||||
- hdmi_ptr.ch_sn = L_CH;
|
||||
hdmi_ptr.iec_offset = 0;
|
||||
hdmi_ptr.srate = 48000;
|
||||
- hdmi_create_cs(&hdmi_ptr);
|
||||
}
|
||||
unlock:
|
||||
spin_unlock_irqrestore(&dev->lock, flags);
|
||||
@@ -704,7 +679,6 @@ static int spacemit_snd_pcm_close(struct snd_soc_component *component, struct sn
|
||||
}
|
||||
dmaengine_terminate_all(chan);
|
||||
if (dmadata->dma_id == DMA_HDMI) {
|
||||
- hdmi_ptr.ch_sn = L_CH;
|
||||
hdmi_ptr.iec_offset = 0;
|
||||
}
|
||||
unlock:
|
||||
@@ -830,72 +804,66 @@ static void spacemit_snd_pcm_remove(struct snd_soc_component *component)
|
||||
dev->dmadata[i].dma_chan = NULL;
|
||||
}
|
||||
}
|
||||
-static void hdmi_set_cs_channel_sn(struct hdmi_codec_priv *hdmi_priv)
|
||||
-{
|
||||
- hdmi_priv->cs[2] &= 0x0f;
|
||||
- if (hdmi_priv->ch_sn == L_CH) {
|
||||
- hdmi_priv->cs[2] |= (0x1 << 4);
|
||||
- hdmi_priv->ch_sn = R_CH;
|
||||
- } else if (hdmi_priv->ch_sn == R_CH) {
|
||||
- hdmi_priv->cs[2] |= (0x2 << 4);
|
||||
- hdmi_priv->ch_sn = L_CH;
|
||||
- }
|
||||
-}
|
||||
|
||||
-static uint32_t get_cs_bit(struct hdmi_codec_priv *hdmi_priv)
|
||||
+static uint32_t parity_even(uint32_t sample)
|
||||
{
|
||||
- unsigned long tmp = 0;
|
||||
- int cs_idx;
|
||||
- int bit_idx;
|
||||
- cs_idx = hdmi_priv->iec_offset >> 3;
|
||||
- bit_idx = hdmi_priv->iec_offset - (cs_idx << 3);
|
||||
-
|
||||
- tmp = hdmi_priv->cs[cs_idx] >> bit_idx;
|
||||
-
|
||||
- return (uint32_t)tmp&0x1;
|
||||
+ bool parity = 0;
|
||||
+ sample ^= sample >> 16;
|
||||
+ sample ^= sample >> 8;
|
||||
+ parity = ParityTable256[sample & 0xff];
|
||||
+ if (parity)
|
||||
+ return 1;
|
||||
+ else
|
||||
+ return 0;
|
||||
}
|
||||
|
||||
-static uint32_t parity_even(uint32_t sample)
|
||||
+static int32_t cal_cs_status_48kHz(int32_t offset)
|
||||
{
|
||||
- bool parity = 0;
|
||||
- sample ^= sample >> 16;
|
||||
- sample ^= sample >> 8;
|
||||
- parity = ParityTable256[sample & 0xff];
|
||||
- if (parity)
|
||||
- return 1;
|
||||
- else
|
||||
- return 0;
|
||||
+ if ((offset == CS_SAMPLING_FREQUENCY) || (offset == CS_MAX_SAMPLE_WORD))
|
||||
+ {
|
||||
+ return 1;
|
||||
+ } else {
|
||||
+ return 0;
|
||||
+ }
|
||||
}
|
||||
|
||||
static void hdmi_reformat(void *dst, void *src, int len)
|
||||
{
|
||||
- uint32_t *dst32 = (uint32_t *)dst;
|
||||
- uint16_t *src16 = (uint16_t *)src;
|
||||
- struct hdmi_codec_priv *dw = &hdmi_ptr;
|
||||
- uint16_t frm_cnt = len;
|
||||
- uint32_t ctrl;
|
||||
- uint32_t sample,parity;
|
||||
- dw->channels = 2;
|
||||
- while (frm_cnt--) {
|
||||
- for (int i = 0; i < dw->channels; i++) {
|
||||
- hdmi_set_cs_channel_sn(dw);
|
||||
- if (dw->iec_offset == 0) {
|
||||
- ctrl = CS_CTRL1 | (get_cs_bit(dw) << CHANNEL_STATUS_OFFSET);
|
||||
- } else {
|
||||
- ctrl = CS_CTRL2 | (get_cs_bit(dw) << CHANNEL_STATUS_OFFSET);
|
||||
- }
|
||||
-
|
||||
- sample = ((uint32_t)(*src16++) << 8)| ctrl;
|
||||
- parity = parity_even(sample);
|
||||
- sample = sample | (parity << PARITY_BIT_OFFSET);
|
||||
- *dst32++ = sample;
|
||||
- }
|
||||
-
|
||||
- dw->iec_offset++;
|
||||
- if (dw->iec_offset >= 192){
|
||||
- dw->iec_offset = 0;
|
||||
+ uint32_t *dst32 = (uint32_t *)dst;
|
||||
+ uint16_t *src16 = (uint16_t *)src;
|
||||
+ struct hdmi_codec_priv *dw = &hdmi_ptr;
|
||||
+ uint16_t frm_cnt = len;
|
||||
+ uint32_t ctrl;
|
||||
+ uint32_t sample,parity;
|
||||
+ dw->channels = 2;
|
||||
+ while (frm_cnt--) {
|
||||
+ for (int i = 0; i < dw->channels; i++) {
|
||||
+ //bit 0-23
|
||||
+ sample = ((uint32_t)(*src16++) << 8);
|
||||
+ //bit 24
|
||||
+ sample = sample | (1 << VALID_OFFSET);
|
||||
+ //bit 26
|
||||
+ sample = sample | (cal_cs_status_48kHz(dw->iec_offset) << CHANNEL_STATUS_OFFSET);
|
||||
+ //bit 27
|
||||
+ parity = parity_even(sample);
|
||||
+ sample = sample | (parity << PARITY_BIT_OFFSET);
|
||||
+
|
||||
+ //bit 30 31
|
||||
+ if (dw->iec_offset == 0) {
|
||||
+ ctrl = CS_CTRL1;
|
||||
+ } else {
|
||||
+ ctrl = CS_CTRL2;
|
||||
+ }
|
||||
+ sample = sample | ctrl;
|
||||
+
|
||||
+ *dst32++ = sample;
|
||||
}
|
||||
- };
|
||||
+
|
||||
+ dw->iec_offset++;
|
||||
+ if (dw->iec_offset >= 192){
|
||||
+ dw->iec_offset = 0;
|
||||
+ }
|
||||
+ }
|
||||
}
|
||||
|
||||
static int spacemit_snd_pcm_copy(struct snd_soc_component *component, struct snd_pcm_substream *substream, int channel,
|
||||
--
|
||||
2.39.2
|
||||
|
||||
|
|
@ -1,248 +0,0 @@
|
|||
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
|
||||
From: Patrick Yavitz <pyavitz@armbian.com>
|
||||
Date: Sat, 22 Jun 2024 15:32:30 -0400
|
||||
Subject: REVERT: Fixes for dtb mapping
|
||||
|
||||
This breaks PCIe on the BPI-F3 so lets revert it until a solution is found.
|
||||
|
||||
https://lore.kernel.org/lkml/mhng-4113481b-4c71-4b5c-ab7e-6896058f074b@palmer-ri-x1c9a/T/
|
||||
https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/diff/?id=v6.1.27&id2=v6.1.26&dt=2
|
||||
|
||||
[ 2.854097] spacemit-pmic-pinctrl spacemit-pinctrl@spm8821: DMA mask not set
|
||||
[ 2.861747] shpchp: Standard Hot Plug PCI Controller Driver version: 0.4
|
||||
[ 2.862556] k1x-dwc-pcie ca400000.pcie: has no power on gpio.
|
||||
[ 2.862764] k1x-dwc-pcie ca400000.pcie: host bridge /soc/pcie@ca400000 ranges:
|
||||
[ 2.862801] k1x-dwc-pcie ca400000.pcie: IO 0x009f002000..0x009f101fff -> 0x009f002000
|
||||
[ 2.862823] k1x-dwc-pcie ca400000.pcie: MEM 0x0090000000..0x009effffff -> 0x0090000000
|
||||
[ 2.862865] k1x-dwc-pcie ca400000.pcie: resource collision: [mem 0x90000000-0x9effffff] conflicts with Reserved [mem 0x80000000-0xc07fffff]
|
||||
[ 2.872584] k1x-dwc-pcie ca400000.pcie: failed to initialize host
|
||||
[ 2.878747] k1x-dwc-pcie: probe of ca400000.pcie failed with error -12
|
||||
[ 2.885725] k1x-dwc-pcie ca800000.pcie: has no power on gpio.
|
||||
[ 2.885912] k1x-dwc-pcie ca800000.pcie: host bridge /soc/pcie@ca800000 ranges:
|
||||
[ 2.885948] k1x-dwc-pcie ca800000.pcie: IO 0x00b7002000..0x00b7101fff -> 0x00b7002000
|
||||
[ 2.885969] k1x-dwc-pcie ca800000.pcie: MEM 0x00a0000000..0x00b6ffffff -> 0x00a0000000
|
||||
[ 2.885987] k1x-dwc-pcie ca800000.pcie: resource collision: [mem 0xa0000000-0xb6ffffff] conflicts with Reserved [mem 0x80000000-0xc07fffff]
|
||||
[ 2.897922] k1x-dwc-pcie ca800000.pcie: failed to initialize host
|
||||
[ 2.904083] k1x-dwc-pcie: probe of ca800000.pcie failed with error -12
|
||||
|
||||
Signed-off-by: Patrick Yavitz <pyavitz@armbian.com>
|
||||
---
|
||||
arch/riscv/include/asm/fixmap.h | 8 -
|
||||
arch/riscv/include/asm/pgtable.h | 8 +-
|
||||
arch/riscv/kernel/setup.c | 6 +-
|
||||
arch/riscv/mm/init.c | 78 ++++++----
|
||||
4 files changed, 52 insertions(+), 48 deletions(-)
|
||||
|
||||
diff --git a/arch/riscv/include/asm/fixmap.h b/arch/riscv/include/asm/fixmap.h
|
||||
index 111111111111..222222222222 100644
|
||||
--- a/arch/riscv/include/asm/fixmap.h
|
||||
+++ b/arch/riscv/include/asm/fixmap.h
|
||||
@@ -22,14 +22,6 @@
|
||||
*/
|
||||
enum fixed_addresses {
|
||||
FIX_HOLE,
|
||||
- /*
|
||||
- * The fdt fixmap mapping must be PMD aligned and will be mapped
|
||||
- * using PMD entries in fixmap_pmd in 64-bit and a PGD entry in 32-bit.
|
||||
- */
|
||||
- FIX_FDT_END,
|
||||
- FIX_FDT = FIX_FDT_END + FIX_FDT_SIZE / PAGE_SIZE - 1,
|
||||
-
|
||||
- /* Below fixmaps will be mapped using fixmap_pte */
|
||||
FIX_PTE,
|
||||
FIX_PMD,
|
||||
FIX_PUD,
|
||||
diff --git a/arch/riscv/include/asm/pgtable.h b/arch/riscv/include/asm/pgtable.h
|
||||
index 111111111111..222222222222 100644
|
||||
--- a/arch/riscv/include/asm/pgtable.h
|
||||
+++ b/arch/riscv/include/asm/pgtable.h
|
||||
@@ -87,13 +87,9 @@
|
||||
|
||||
#define FIXADDR_TOP PCI_IO_START
|
||||
#ifdef CONFIG_64BIT
|
||||
-#define MAX_FDT_SIZE PMD_SIZE
|
||||
-#define FIX_FDT_SIZE (MAX_FDT_SIZE + SZ_2M)
|
||||
-#define FIXADDR_SIZE (PMD_SIZE + FIX_FDT_SIZE)
|
||||
+#define FIXADDR_SIZE PMD_SIZE
|
||||
#else
|
||||
-#define MAX_FDT_SIZE PGDIR_SIZE
|
||||
-#define FIX_FDT_SIZE MAX_FDT_SIZE
|
||||
-#define FIXADDR_SIZE (PGDIR_SIZE + FIX_FDT_SIZE)
|
||||
+#define FIXADDR_SIZE PGDIR_SIZE
|
||||
#endif
|
||||
#define FIXADDR_START (FIXADDR_TOP - FIXADDR_SIZE)
|
||||
|
||||
diff --git a/arch/riscv/kernel/setup.c b/arch/riscv/kernel/setup.c
|
||||
index 111111111111..222222222222 100644
|
||||
--- a/arch/riscv/kernel/setup.c
|
||||
+++ b/arch/riscv/kernel/setup.c
|
||||
@@ -280,8 +280,12 @@ void __init setup_arch(char **cmdline_p)
|
||||
#if IS_ENABLED(CONFIG_BUILTIN_DTB)
|
||||
unflatten_and_copy_device_tree();
|
||||
#else
|
||||
- unflatten_device_tree();
|
||||
+ if (early_init_dt_verify(__va(XIP_FIXUP(dtb_early_pa))))
|
||||
+ unflatten_device_tree();
|
||||
+ else
|
||||
+ pr_err("No DTB found in kernel mappings\n");
|
||||
#endif
|
||||
+ early_init_fdt_scan_reserved_mem();
|
||||
misc_mem_init();
|
||||
|
||||
init_resources();
|
||||
diff --git a/arch/riscv/mm/init.c b/arch/riscv/mm/init.c
|
||||
index 111111111111..222222222222 100644
|
||||
--- a/arch/riscv/mm/init.c
|
||||
+++ b/arch/riscv/mm/init.c
|
||||
@@ -57,6 +57,7 @@ unsigned long empty_zero_page[PAGE_SIZE / sizeof(unsigned long)]
|
||||
EXPORT_SYMBOL(empty_zero_page);
|
||||
|
||||
extern char _start[];
|
||||
+#define DTB_EARLY_BASE_VA PGDIR_SIZE
|
||||
void *_dtb_early_va __initdata;
|
||||
uintptr_t _dtb_early_pa __initdata;
|
||||
|
||||
@@ -241,22 +242,31 @@ static void __init setup_bootmem(void)
|
||||
set_max_mapnr(max_low_pfn - ARCH_PFN_OFFSET);
|
||||
|
||||
reserve_initrd_mem();
|
||||
-
|
||||
- /*
|
||||
- * No allocation should be done before reserving the memory as defined
|
||||
- * in the device tree, otherwise the allocation could end up in a
|
||||
- * reserved region.
|
||||
- */
|
||||
- early_init_fdt_scan_reserved_mem();
|
||||
-
|
||||
/*
|
||||
* If DTB is built in, no need to reserve its memblock.
|
||||
* Otherwise, do reserve it but avoid using
|
||||
* early_init_fdt_reserve_self() since __pa() does
|
||||
* not work for DTB pointers that are fixmap addresses
|
||||
*/
|
||||
- if (!IS_ENABLED(CONFIG_BUILTIN_DTB))
|
||||
- memblock_reserve(dtb_early_pa, fdt_totalsize(dtb_early_va));
|
||||
+ if (!IS_ENABLED(CONFIG_BUILTIN_DTB)) {
|
||||
+ /*
|
||||
+ * In case the DTB is not located in a memory region we won't
|
||||
+ * be able to locate it later on via the linear mapping and
|
||||
+ * get a segfault when accessing it via __va(dtb_early_pa).
|
||||
+ * To avoid this situation copy DTB to a memory region.
|
||||
+ * Note that memblock_phys_alloc will also reserve DTB region.
|
||||
+ */
|
||||
+ if (!memblock_is_memory(dtb_early_pa)) {
|
||||
+ size_t fdt_size = fdt_totalsize(dtb_early_va);
|
||||
+ phys_addr_t new_dtb_early_pa = memblock_phys_alloc(fdt_size, PAGE_SIZE);
|
||||
+ void *new_dtb_early_va = early_memremap(new_dtb_early_pa, fdt_size);
|
||||
+
|
||||
+ memcpy(new_dtb_early_va, dtb_early_va, fdt_size);
|
||||
+ early_memunmap(new_dtb_early_va, fdt_size);
|
||||
+ _dtb_early_pa = new_dtb_early_pa;
|
||||
+ } else
|
||||
+ memblock_reserve(dtb_early_pa, fdt_totalsize(dtb_early_va));
|
||||
+ }
|
||||
|
||||
#ifdef CONFIG_ZONE_DMA32
|
||||
dma_contiguous_reserve(dma32_phys_limit);
|
||||
@@ -279,6 +289,9 @@ pgd_t trampoline_pg_dir[PTRS_PER_PGD] __page_aligned_bss;
|
||||
static pte_t fixmap_pte[PTRS_PER_PTE] __page_aligned_bss;
|
||||
|
||||
pgd_t early_pg_dir[PTRS_PER_PGD] __initdata __aligned(PAGE_SIZE);
|
||||
+static p4d_t __maybe_unused early_dtb_p4d[PTRS_PER_P4D] __initdata __aligned(PAGE_SIZE);
|
||||
+static pud_t __maybe_unused early_dtb_pud[PTRS_PER_PUD] __initdata __aligned(PAGE_SIZE);
|
||||
+static pmd_t __maybe_unused early_dtb_pmd[PTRS_PER_PMD] __initdata __aligned(PAGE_SIZE);
|
||||
|
||||
#ifdef CONFIG_XIP_KERNEL
|
||||
#define pt_ops (*(struct pt_alloc_ops *)XIP_FIXUP(&pt_ops))
|
||||
@@ -623,6 +636,9 @@ static void __init create_p4d_mapping(p4d_t *p4dp,
|
||||
#define trampoline_pgd_next (pgtable_l5_enabled ? \
|
||||
(uintptr_t)trampoline_p4d : (pgtable_l4_enabled ? \
|
||||
(uintptr_t)trampoline_pud : (uintptr_t)trampoline_pmd))
|
||||
+#define early_dtb_pgd_next (pgtable_l5_enabled ? \
|
||||
+ (uintptr_t)early_dtb_p4d : (pgtable_l4_enabled ? \
|
||||
+ (uintptr_t)early_dtb_pud : (uintptr_t)early_dtb_pmd))
|
||||
#else
|
||||
#define pgd_next_t pte_t
|
||||
#define alloc_pgd_next(__va) pt_ops.alloc_pte(__va)
|
||||
@@ -630,6 +646,7 @@ static void __init create_p4d_mapping(p4d_t *p4dp,
|
||||
#define create_pgd_next_mapping(__nextp, __va, __pa, __sz, __prot) \
|
||||
create_pte_mapping(__nextp, __va, __pa, __sz, __prot)
|
||||
#define fixmap_pgd_next ((uintptr_t)fixmap_pte)
|
||||
+#define early_dtb_pgd_next ((uintptr_t)early_dtb_pmd)
|
||||
#define create_p4d_mapping(__pmdp, __va, __pa, __sz, __prot) do {} while(0)
|
||||
#define create_pud_mapping(__pmdp, __va, __pa, __sz, __prot) do {} while(0)
|
||||
#define create_pmd_mapping(__pmdp, __va, __pa, __sz, __prot) do {} while(0)
|
||||
@@ -852,27 +869,32 @@ static void __init create_kernel_page_table(pgd_t *pgdir, bool early)
|
||||
* this means 2 PMD entries whereas for 32-bit kernel, this is only 1 PGDIR
|
||||
* entry.
|
||||
*/
|
||||
-static void __init create_fdt_early_page_table(uintptr_t fix_fdt_va,
|
||||
- uintptr_t dtb_pa)
|
||||
+static void __init create_fdt_early_page_table(pgd_t *pgdir, uintptr_t dtb_pa)
|
||||
{
|
||||
#ifndef CONFIG_BUILTIN_DTB
|
||||
uintptr_t pa = dtb_pa & ~(PMD_SIZE - 1);
|
||||
|
||||
- /* Make sure the fdt fixmap address is always aligned on PMD size */
|
||||
- BUILD_BUG_ON(FIX_FDT % (PMD_SIZE / PAGE_SIZE));
|
||||
+ create_pgd_mapping(early_pg_dir, DTB_EARLY_BASE_VA,
|
||||
+ IS_ENABLED(CONFIG_64BIT) ? early_dtb_pgd_next : pa,
|
||||
+ PGDIR_SIZE,
|
||||
+ IS_ENABLED(CONFIG_64BIT) ? PAGE_TABLE : PAGE_KERNEL);
|
||||
|
||||
- /* In 32-bit only, the fdt lies in its own PGD */
|
||||
- if (!IS_ENABLED(CONFIG_64BIT)) {
|
||||
- create_pgd_mapping(early_pg_dir, fix_fdt_va,
|
||||
- pa, MAX_FDT_SIZE, PAGE_KERNEL);
|
||||
- } else {
|
||||
- create_pmd_mapping(fixmap_pmd, fix_fdt_va,
|
||||
+ if (pgtable_l5_enabled)
|
||||
+ create_p4d_mapping(early_dtb_p4d, DTB_EARLY_BASE_VA,
|
||||
+ (uintptr_t)early_dtb_pud, P4D_SIZE, PAGE_TABLE);
|
||||
+
|
||||
+ if (pgtable_l4_enabled)
|
||||
+ create_pud_mapping(early_dtb_pud, DTB_EARLY_BASE_VA,
|
||||
+ (uintptr_t)early_dtb_pmd, PUD_SIZE, PAGE_TABLE);
|
||||
+
|
||||
+ if (IS_ENABLED(CONFIG_64BIT)) {
|
||||
+ create_pmd_mapping(early_dtb_pmd, DTB_EARLY_BASE_VA,
|
||||
pa, PMD_SIZE, PAGE_KERNEL);
|
||||
- create_pmd_mapping(fixmap_pmd, fix_fdt_va + PMD_SIZE,
|
||||
+ create_pmd_mapping(early_dtb_pmd, DTB_EARLY_BASE_VA + PMD_SIZE,
|
||||
pa + PMD_SIZE, PMD_SIZE, PAGE_KERNEL);
|
||||
}
|
||||
|
||||
- dtb_early_va = (void *)fix_fdt_va + (dtb_pa & (PMD_SIZE - 1));
|
||||
+ dtb_early_va = (void *)DTB_EARLY_BASE_VA + (dtb_pa & (PMD_SIZE - 1));
|
||||
#else
|
||||
/*
|
||||
* For 64-bit kernel, __va can't be used since it would return a linear
|
||||
@@ -1042,7 +1064,7 @@ asmlinkage void __init setup_vm(uintptr_t dtb_pa)
|
||||
create_kernel_page_table(early_pg_dir, true);
|
||||
|
||||
/* Setup early mapping for FDT early scan */
|
||||
- create_fdt_early_page_table(__fix_to_virt(FIX_FDT), dtb_pa);
|
||||
+ create_fdt_early_page_table(early_pg_dir, dtb_pa);
|
||||
|
||||
/*
|
||||
* Bootime fixmap only can handle PMD_SIZE mapping. Thus, boot-ioremap
|
||||
@@ -1084,16 +1106,6 @@ static void __init setup_vm_final(void)
|
||||
u64 i;
|
||||
|
||||
/* Setup swapper PGD for fixmap */
|
||||
-#if !defined(CONFIG_64BIT)
|
||||
- /*
|
||||
- * In 32-bit, the device tree lies in a pgd entry, so it must be copied
|
||||
- * directly in swapper_pg_dir in addition to the pgd entry that points
|
||||
- * to fixmap_pte.
|
||||
- */
|
||||
- unsigned long idx = pgd_index(__fix_to_virt(FIX_FDT));
|
||||
-
|
||||
- set_pgd(&swapper_pg_dir[idx], early_pg_dir[idx]);
|
||||
-#endif
|
||||
create_pgd_mapping(swapper_pg_dir, FIXADDR_START,
|
||||
__pa_symbol(fixmap_pgd_next),
|
||||
PGDIR_SIZE, PAGE_TABLE);
|
||||
--
|
||||
Armbian
|
||||
|
||||
|
|
@ -9,18 +9,13 @@
|
|||
model = "BananaPi BPI-F3";
|
||||
};
|
||||
|
||||
&pcie2_rc {
|
||||
num-lanes = <1>;
|
||||
};
|
||||
|
||||
&uart2 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart2>;
|
||||
status = "okay";
|
||||
status = "disabled";
|
||||
|
||||
bluetooth {
|
||||
compatible = "realtek,rtl8852bs-bt";
|
||||
device-wake-gpios = <&gpio 64 GPIO_ACTIVE_HIGH>;
|
||||
host-wake-gpios = <&gpio 65 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -0,0 +1,17 @@
|
|||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Copyright (C) 2023 SPACEMIT Micro Limited
|
||||
*/
|
||||
|
||||
/ {
|
||||
reserved-memory {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
|
||||
spacemitzreserved: spacemit-mmz-@50000000 {
|
||||
no-map;
|
||||
reg = <0x0 0x50000000 0x0 0x28000000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -11,7 +11,7 @@
|
|||
compatible = "spacemit,plat-cam", "simple-bus";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
interconnects = <&dram_range1>;
|
||||
interconnects = <&dram_range3>;
|
||||
interconnect-names = "dma-mem";
|
||||
status = "okay";
|
||||
};
|
||||
|
|
@ -25,7 +25,7 @@
|
|||
clock-names = "csi_dphy";
|
||||
resets = <&reset RESET_CCIC1_PHY>;
|
||||
reset-names = "cphy_reset";
|
||||
interconnects = <&dram_range1>;
|
||||
interconnects = <&dram_range3>;
|
||||
interconnect-names = "dma-mem";
|
||||
status = "okay";
|
||||
};
|
||||
|
|
@ -39,7 +39,7 @@
|
|||
clock-names = "csi_dphy";
|
||||
resets = <&reset RESET_CCIC2_PHY>;
|
||||
reset-names = "cphy_reset";
|
||||
interconnects = <&dram_range1>;
|
||||
interconnects = <&dram_range3>;
|
||||
interconnect-names = "dma-mem";
|
||||
status = "okay";
|
||||
};
|
||||
|
|
@ -54,7 +54,7 @@
|
|||
clock-names = "csi_dphy";
|
||||
resets = <&reset RESET_CCIC3_PHY>;
|
||||
reset-names = "cphy_reset";
|
||||
interconnects = <&dram_range1>;
|
||||
interconnects = <&dram_range3>;
|
||||
interconnect-names = "dma-mem";
|
||||
status = "okay";
|
||||
};
|
||||
|
|
@ -76,7 +76,7 @@
|
|||
<&reset RESET_CCIC_4X>, <&reset RESET_ISP_CI>;
|
||||
reset-names = "isp_ahb_reset", "csi_reset",
|
||||
"ccic_4x_reset", "isp_ci_reset";
|
||||
interconnects = <&dram_range1>;
|
||||
interconnects = <&dram_range3>;
|
||||
interconnect-names = "dma-mem";
|
||||
status = "okay";
|
||||
};
|
||||
|
|
@ -98,7 +98,7 @@
|
|||
<&reset RESET_CCIC_4X>, <&reset RESET_ISP_CI>;
|
||||
reset-names = "isp_ahb_reset", "csi_reset",
|
||||
"ccic_4x_reset", "isp_ci_reset";
|
||||
interconnects = <&dram_range1>;
|
||||
interconnects = <&dram_range3>;
|
||||
interconnect-names = "dma-mem";
|
||||
status = "okay";
|
||||
};
|
||||
|
|
@ -120,7 +120,7 @@
|
|||
<&reset RESET_CCIC_4X>, <&reset RESET_ISP_CI>;
|
||||
reset-names = "isp_ahb_reset", "csi_reset",
|
||||
"ccic_4x_reset", "isp_ci_reset";
|
||||
interconnects = <&dram_range1>;
|
||||
interconnects = <&dram_range3>;
|
||||
interconnect-names = "dma-mem";
|
||||
status = "okay";
|
||||
};
|
||||
|
|
@ -140,7 +140,7 @@
|
|||
<&reset RESET_ISP_CI>, <&reset RESET_LCD_MCLK>;
|
||||
reset-names = "isp_ahb_reset", "isp_reset",
|
||||
"isp_ci_reset", "lcd_mclk_reset";
|
||||
interconnects = <&dram_range1>;
|
||||
interconnects = <&dram_range3>;
|
||||
interconnect-names = "dma-mem";
|
||||
status = "okay";
|
||||
};
|
||||
|
|
@ -160,7 +160,7 @@
|
|||
<&reset RESET_ISP_CI>, <&reset RESET_LCD_MCLK>;
|
||||
reset-names = "isp_ahb_reset", "isp_reset",
|
||||
"isp_ci_reset", "lcd_mclk_reset";
|
||||
interconnects = <&dram_range1>;
|
||||
interconnects = <&dram_range3>;
|
||||
interconnect-names = "dma-mem";
|
||||
status = "okay";
|
||||
};
|
||||
|
|
@ -180,7 +180,7 @@
|
|||
<&reset RESET_ISP_CI>, <&reset RESET_LCD_MCLK>;
|
||||
reset-names = "isp_ahb_reset", "isp_cpp_reset",
|
||||
"isp_ci_reset", "lcd_mclk_reset";
|
||||
interconnects = <&dram_range1>;
|
||||
interconnects = <&dram_range3>;
|
||||
interconnect-names = "dma-mem";
|
||||
status = "okay";
|
||||
};
|
||||
|
|
|
|||
|
|
@ -0,0 +1,52 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
|
||||
/* Copyright (c) 2024 Spacemit, Inc */
|
||||
|
||||
&efuse {
|
||||
status = "okay";
|
||||
|
||||
efuse_bank7: efuse_bank@7 {
|
||||
compatible = "spacemit,k1-efuse";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
reg = <0x190 0x20>;
|
||||
resets = <&reset RESET_AES>;
|
||||
reset-names = "aes_reset";
|
||||
clocks = <&ccu CLK_AES>;
|
||||
clock-names = "aes_core";
|
||||
status = "okay";
|
||||
|
||||
soc_die_id: bank7@11,3 {
|
||||
reg = <0x11 3>;
|
||||
bits = <3 16>;
|
||||
};
|
||||
|
||||
soc_ver_id: bank7@1f,6 {
|
||||
reg = <0x1F 1>;
|
||||
bits = <6 2>;
|
||||
};
|
||||
|
||||
soc_pack_id: bank7@16,6 {
|
||||
reg = <0x16 2>;
|
||||
bits = <6 9>;
|
||||
};
|
||||
|
||||
soc_svt_dro: bank7@15,5 {
|
||||
reg = <0x15 2>;
|
||||
bits = <5 9>;
|
||||
};
|
||||
|
||||
soc_chip_id: bank7@17,7 {
|
||||
reg = <0x17 8>;
|
||||
bits = <7 55>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&socinfo {
|
||||
nvmem-cells = <&soc_die_id>, <&soc_ver_id>, <&soc_pack_id>,
|
||||
<&soc_svt_dro>, <&soc_chip_id>;
|
||||
nvmem-cell-names = "soc_die_id", "soc_ver_id", "soc_pack_id",
|
||||
"soc_svt_dro", "soc_chip_id";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
|
|
@ -49,15 +49,13 @@
|
|||
riscv,cbom-block-size = <64>;
|
||||
i-cache-block-size = <64>;
|
||||
i-cache-size = <32768>;
|
||||
i-cache-sets = <512>;
|
||||
i-cache-sets = <128>;
|
||||
d-cache-block-size = <64>;
|
||||
d-cache-size = <32768>;
|
||||
d-cache-sets = <512>;
|
||||
d-cache-sets = <128>;
|
||||
next-level-cache = <&clst0_l2_cache>;
|
||||
mmu-type = "riscv,sv39";
|
||||
clocks = <&ccu CLK_CPU_C0_CORE>;
|
||||
cpu-idle-states = <&CPU_NONRET> /*, <&CLUSTER_NONRET>, <&TOP_NONRET> */;
|
||||
operating-points-v2 = <&clst0_core_opp_table>;
|
||||
#cooling-cells = <2>;
|
||||
|
||||
cpu0_intc: interrupt-controller {
|
||||
|
|
@ -77,15 +75,13 @@
|
|||
riscv,cbom-block-size = <64>;
|
||||
i-cache-block-size = <64>;
|
||||
i-cache-size = <32768>;
|
||||
i-cache-sets = <512>;
|
||||
i-cache-sets = <128>;
|
||||
d-cache-block-size = <64>;
|
||||
d-cache-size = <32768>;
|
||||
d-cache-sets = <512>;
|
||||
d-cache-sets = <128>;
|
||||
next-level-cache = <&clst0_l2_cache>;
|
||||
mmu-type = "riscv,sv39";
|
||||
clocks = <&ccu CLK_CPU_C0_CORE>;
|
||||
cpu-idle-states = <&CPU_NONRET> /*, <&CLUSTER_NONRET>, <&TOP_NONRET> */;
|
||||
operating-points-v2 = <&clst0_core_opp_table>;
|
||||
#cooling-cells = <2>;
|
||||
|
||||
cpu1_intc: interrupt-controller {
|
||||
|
|
@ -105,15 +101,13 @@
|
|||
riscv,cbom-block-size = <64>;
|
||||
i-cache-block-size = <64>;
|
||||
i-cache-size = <32768>;
|
||||
i-cache-sets = <512>;
|
||||
i-cache-sets = <128>;
|
||||
d-cache-block-size = <64>;
|
||||
d-cache-size = <32768>;
|
||||
d-cache-sets = <512>;
|
||||
d-cache-sets = <128>;
|
||||
next-level-cache = <&clst0_l2_cache>;
|
||||
mmu-type = "riscv,sv39";
|
||||
clocks = <&ccu CLK_CPU_C0_CORE>;
|
||||
cpu-idle-states = <&CPU_NONRET> /*, <&CLUSTER_NONRET>, <&TOP_NONRET> */;
|
||||
operating-points-v2 = <&clst0_core_opp_table>;
|
||||
#cooling-cells = <2>;
|
||||
|
||||
cpu2_intc: interrupt-controller {
|
||||
|
|
@ -133,15 +127,13 @@
|
|||
riscv,cbom-block-size = <64>;
|
||||
i-cache-block-size = <64>;
|
||||
i-cache-size = <32768>;
|
||||
i-cache-sets = <512>;
|
||||
i-cache-sets = <128>;
|
||||
d-cache-block-size = <64>;
|
||||
d-cache-size = <32768>;
|
||||
d-cache-sets = <512>;
|
||||
d-cache-sets = <128>;
|
||||
next-level-cache = <&clst0_l2_cache>;
|
||||
mmu-type = "riscv,sv39";
|
||||
clocks = <&ccu CLK_CPU_C0_CORE>;
|
||||
cpu-idle-states = <&CPU_NONRET> /*, <&CLUSTER_NONRET>, <&TOP_NONRET> */;
|
||||
operating-points-v2 = <&clst0_core_opp_table>;
|
||||
#cooling-cells = <2>;
|
||||
|
||||
cpu3_intc: interrupt-controller {
|
||||
|
|
@ -161,15 +153,13 @@
|
|||
riscv,cbom-block-size = <64>;
|
||||
i-cache-block-size = <64>;
|
||||
i-cache-size = <32768>;
|
||||
i-cache-sets = <512>;
|
||||
i-cache-sets = <128>;
|
||||
d-cache-block-size = <64>;
|
||||
d-cache-size = <32768>;
|
||||
d-cache-sets = <512>;
|
||||
d-cache-sets = <128>;
|
||||
next-level-cache = <&clst1_l2_cache>;
|
||||
mmu-type = "riscv,sv39";
|
||||
clocks = <&ccu CLK_CPU_C1_CORE>;
|
||||
cpu-idle-states = <&CPU_NONRET> /*, <&CLUSTER_NONRET>, <&TOP_NONRET> */;
|
||||
operating-points-v2 = <&clst1_core_opp_table>;
|
||||
#cooling-cells = <2>;
|
||||
|
||||
cpu4_intc: interrupt-controller {
|
||||
|
|
@ -189,15 +179,13 @@
|
|||
riscv,cbom-block-size = <64>;
|
||||
i-cache-block-size = <64>;
|
||||
i-cache-size = <32768>;
|
||||
i-cache-sets = <512>;
|
||||
i-cache-sets = <128>;
|
||||
d-cache-block-size = <64>;
|
||||
d-cache-size = <32768>;
|
||||
d-cache-sets = <512>;
|
||||
d-cache-sets = <128>;
|
||||
next-level-cache = <&clst1_l2_cache>;
|
||||
mmu-type = "riscv,sv39";
|
||||
clocks = <&ccu CLK_CPU_C1_CORE>;
|
||||
cpu-idle-states = <&CPU_NONRET> /*, <&CLUSTER_NONRET>, <&TOP_NONRET> */;
|
||||
operating-points-v2 = <&clst1_core_opp_table>;
|
||||
#cooling-cells = <2>;
|
||||
|
||||
cpu5_intc: interrupt-controller {
|
||||
|
|
@ -217,15 +205,13 @@
|
|||
riscv,cbom-block-size = <64>;
|
||||
i-cache-block-size = <64>;
|
||||
i-cache-size = <32768>;
|
||||
i-cache-sets = <512>;
|
||||
i-cache-sets = <128>;
|
||||
d-cache-block-size = <64>;
|
||||
d-cache-size = <32768>;
|
||||
d-cache-sets = <512>;
|
||||
d-cache-sets = <128>;
|
||||
next-level-cache = <&clst1_l2_cache>;
|
||||
mmu-type = "riscv,sv39";
|
||||
clocks = <&ccu CLK_CPU_C1_CORE>;
|
||||
cpu-idle-states = <&CPU_NONRET> /*, <&CLUSTER_NONRET>, <&TOP_NONRET> */;
|
||||
operating-points-v2 = <&clst1_core_opp_table>;
|
||||
#cooling-cells = <2>;
|
||||
|
||||
cpu6_intc: interrupt-controller {
|
||||
|
|
@ -245,15 +231,13 @@
|
|||
riscv,cbom-block-size = <64>;
|
||||
i-cache-block-size = <64>;
|
||||
i-cache-size = <32768>;
|
||||
i-cache-sets = <512>;
|
||||
i-cache-sets = <128>;
|
||||
d-cache-block-size = <64>;
|
||||
d-cache-size = <32768>;
|
||||
d-cache-sets = <512>;
|
||||
d-cache-sets = <128>;
|
||||
next-level-cache = <&clst1_l2_cache>;
|
||||
mmu-type = "riscv,sv39";
|
||||
clocks = <&ccu CLK_CPU_C1_CORE>;
|
||||
cpu-idle-states = <&CPU_NONRET> /*, <&CLUSTER_NONRET>, <&TOP_NONRET> */;
|
||||
operating-points-v2 = <&clst1_core_opp_table>;
|
||||
#cooling-cells = <2>;
|
||||
|
||||
cpu7_intc: interrupt-controller {
|
||||
|
|
@ -268,7 +252,7 @@
|
|||
cache-block-size = <64>;
|
||||
cache-level = <2>;
|
||||
cache-size = <524288>;
|
||||
cache-sets = <1024>;
|
||||
cache-sets = <512>;
|
||||
cache-unified;
|
||||
};
|
||||
|
||||
|
|
@ -277,7 +261,7 @@
|
|||
cache-block-size = <64>;
|
||||
cache-level = <2>;
|
||||
cache-size = <524288>;
|
||||
cache-sets = <1024>;
|
||||
cache-sets = <512>;
|
||||
cache-unified;
|
||||
};
|
||||
|
||||
|
|
@ -314,99 +298,6 @@
|
|||
wakeup-latency-us = <1600>;
|
||||
};
|
||||
};
|
||||
|
||||
clst0_core_opp_table: opp_table0 {
|
||||
compatible = "operating-points-v2";
|
||||
opp-shared;
|
||||
|
||||
clocks = <&ccu CLK_CPU_C0_ACE>, <&ccu CLK_CPU_C0_TCM>, <&ccu CLK_CCI550>;
|
||||
clock-names = "ace","tcm", "cci";
|
||||
cci-hz = /bits/ 64 <614000000>;
|
||||
|
||||
opp1600000000 {
|
||||
opp-hz = /bits/ 64 <1600000000>;
|
||||
tcm-hz = /bits/ 64 <800000000>;
|
||||
ace-hz = /bits/ 64 <800000000>;
|
||||
opp-microvolt = <950000>;
|
||||
clock-latency-ns = <200000>;
|
||||
};
|
||||
|
||||
opp1228800000 {
|
||||
opp-hz = /bits/ 64 <1228800000>;
|
||||
tcm-hz = /bits/ 64 <614400000>;
|
||||
ace-hz = /bits/ 64 <614400000>;
|
||||
opp-microvolt = <950000>;
|
||||
clock-latency-ns = <200000>;
|
||||
};
|
||||
|
||||
opp1000000000 {
|
||||
opp-hz = /bits/ 64 <1000000000>;
|
||||
tcm-hz = /bits/ 64 <500000000>;
|
||||
ace-hz = /bits/ 64 <500000000>;
|
||||
opp-microvolt = <950000>;
|
||||
clock-latency-ns = <200000>;
|
||||
};
|
||||
|
||||
opp819000000 {
|
||||
opp-hz = /bits/ 64 <819000000>;
|
||||
opp-microvolt = <950000>;
|
||||
tcm-hz = /bits/ 64 <409500000>;
|
||||
ace-hz = /bits/ 64 <409500000>;
|
||||
clock-latency-ns = <200000>;
|
||||
};
|
||||
|
||||
opp614400000 {
|
||||
opp-hz = /bits/ 64 <614400000>;
|
||||
tcm-hz = /bits/ 64 <307200000>;
|
||||
ace-hz = /bits/ 64 <307200000>;
|
||||
opp-microvolt = <950000>;
|
||||
clock-latency-ns = <200000>;
|
||||
};
|
||||
};
|
||||
|
||||
clst1_core_opp_table: opp_table1 {
|
||||
compatible = "operating-points-v2";
|
||||
opp-shared;
|
||||
|
||||
clocks = <&ccu CLK_CPU_C1_ACE>, <&ccu CLK_CCI550>;
|
||||
clock-names = "ace", "cci";
|
||||
cci-hz = /bits/ 64 <614000000>;
|
||||
|
||||
opp1600000000 {
|
||||
opp-hz = /bits/ 64 <1600000000>;
|
||||
ace-hz = /bits/ 64 <800000000>;
|
||||
opp-microvolt = <950000>;
|
||||
clock-latency-ns = <200000>;
|
||||
};
|
||||
|
||||
opp1228800000 {
|
||||
opp-hz = /bits/ 64 <1228800000>;
|
||||
ace-hz = /bits/ 64 <614400000>;
|
||||
opp-microvolt = <950000>;
|
||||
clock-latency-ns = <200000>;
|
||||
};
|
||||
|
||||
opp1000000000 {
|
||||
opp-hz = /bits/ 64 <1000000000>;
|
||||
ace-hz = /bits/ 64 <500000000>;
|
||||
opp-microvolt = <950000>;
|
||||
clock-latency-ns = <200000>;
|
||||
};
|
||||
|
||||
opp819000000 {
|
||||
opp-hz = /bits/ 64 <819000000>;
|
||||
ace-hz = /bits/ 64 <409500000>;
|
||||
opp-microvolt = <950000>;
|
||||
clock-latency-ns = <200000>;
|
||||
};
|
||||
|
||||
opp614400000 {
|
||||
opp-hz = /bits/ 64 <614400000>;
|
||||
ace-hz = /bits/ 64 <307200000>;
|
||||
opp-microvolt = <950000>;
|
||||
clock-latency-ns = <200000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
clocks {
|
||||
|
|
@ -468,6 +359,7 @@
|
|||
area_reserved@80000000 {
|
||||
/* dram area is 0~2GB, and 4GB~, the 2GB~4GB is io area */
|
||||
reg = <0x0 0x80000000 0x0 0x40800000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
/* sram area, used for rcpu code & data & heap space */
|
||||
|
|
@ -527,7 +419,7 @@
|
|||
#size-cells = <2>;
|
||||
ranges;
|
||||
|
||||
/* dram mapping for dma/usb/sdh/audio/crypto for ex. */
|
||||
/* dram mapping for usb/sdh for ex. */
|
||||
dram_range0: dram_range@0 {
|
||||
compatible = "spacemit-dram-bus";
|
||||
#address-cells = <2>;
|
||||
|
|
@ -537,7 +429,7 @@
|
|||
status = "okay";
|
||||
};
|
||||
|
||||
/* dram mapping for vpu/gpu/v2d/jpu for ex. */
|
||||
/* dram mapping for vpu/gpu/dpu for ex. */
|
||||
dram_range1: dram_range@1 {
|
||||
compatible = "spacemit-dram-bus";
|
||||
#address-cells = <2>;
|
||||
|
|
@ -548,6 +440,7 @@
|
|||
status = "okay";
|
||||
};
|
||||
|
||||
/* dram mapping for pcie for ex. */
|
||||
dram_range2: dram_range@2 {
|
||||
compatible = "spacemit-dram-bus";
|
||||
#address-cells = <2>;
|
||||
|
|
@ -558,6 +451,39 @@
|
|||
status = "okay";
|
||||
};
|
||||
|
||||
/* dram mapping for v2d/isp/csi/vi/cpp for ex. */
|
||||
dram_range3: dram_range@3 {
|
||||
compatible = "spacemit-dram-bus";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
dma-ranges = <0x0 0x00000000 0x0 0x00000000 0x0 0x80000000>,
|
||||
<0x0 0x80000000 0x1 0x00000000 0x1 0x80000000>;
|
||||
#interconnect-cells = <0>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* dram mapping for dma&users for ex. */
|
||||
dram_range4: dram_range@4 {
|
||||
compatible = "spacemit-dram-bus";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
dma-ranges = <0x0 0x00000000 0x0 0x00000000 0x0 0x80000000>,
|
||||
<0x1 0x00000000 0x1 0x80000000 0x3 0x00000000>;
|
||||
#interconnect-cells = <0>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* dram mapping for eth/crypto/jpu for ex. */
|
||||
dram_range5: dram_range@5 {
|
||||
compatible = "spacemit-dram-bus";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
dma-ranges = <0x0 0x00000000 0x0 0x00000000 0x0 0x80000000>,
|
||||
<0x0 0x80000000 0x1 0x00000000 0x0 0x80000000>;
|
||||
#interconnect-cells = <0>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
clint0: clint@e4000000 {
|
||||
compatible = "riscv,clint0";
|
||||
interrupts-extended = <
|
||||
|
|
@ -632,8 +558,9 @@
|
|||
};
|
||||
|
||||
pinctrl: pinctrl@d401e000 {
|
||||
compatible = "pinconf-single";
|
||||
reg = <0x0 0xd401e000 0x0 0x400>;
|
||||
compatible = "pinconf-single-aib";
|
||||
reg = <0x0 0xd401e000 0x0 0x400>,
|
||||
<0x0 0xd4019800 0x0 0x10>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
#pinctrl-cells = <2>;
|
||||
|
|
@ -642,6 +569,16 @@
|
|||
pinctrl-single,register-width = <32>;
|
||||
pinctrl-single,function-mask = <0xff77>;
|
||||
|
||||
clocks = <&ccu CLK_AIB>;
|
||||
clock-names = "clk_aib";
|
||||
resets = <&reset RESET_AIB>;
|
||||
reset-names = "aib_rst";
|
||||
|
||||
interrupt-parent = <&intc>;
|
||||
interrupts = <60>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
|
||||
range: gpio-range {
|
||||
#pinctrl-single,gpio-range-cells = <3>;
|
||||
};
|
||||
|
|
@ -796,7 +733,7 @@
|
|||
dmas = <&pdma0 DMA_UART0_RX 1
|
||||
&pdma0 DMA_UART0_TX 1>;
|
||||
dma-names = "rx", "tx";
|
||||
interconnects = <&dram_range0>;
|
||||
interconnects = <&dram_range4>;
|
||||
interconnect-names = "dma-mem";
|
||||
status = "ok";
|
||||
};
|
||||
|
|
@ -813,7 +750,7 @@
|
|||
power-domains = <&power K1X_PMU_BUS_PWR_DOMAIN>;
|
||||
clk,pm-runtime,no-sleep;
|
||||
cpuidle,pm-runtime,sleep;
|
||||
interconnects = <&dram_range0>;
|
||||
interconnects = <&dram_range4>;
|
||||
interconnect-names = "dma-mem";
|
||||
status = "disabled";
|
||||
};
|
||||
|
|
@ -830,7 +767,7 @@
|
|||
power-domains = <&power K1X_PMU_BUS_PWR_DOMAIN>;
|
||||
clk,pm-runtime,no-sleep;
|
||||
cpuidle,pm-runtime,sleep;
|
||||
interconnects = <&dram_range0>;
|
||||
interconnects = <&dram_range4>;
|
||||
interconnect-names = "dma-mem";
|
||||
status = "disabled";
|
||||
};
|
||||
|
|
@ -847,7 +784,7 @@
|
|||
power-domains = <&power K1X_PMU_BUS_PWR_DOMAIN>;
|
||||
clk,pm-runtime,no-sleep;
|
||||
cpuidle,pm-runtime,sleep;
|
||||
interconnects = <&dram_range0>;
|
||||
interconnects = <&dram_range4>;
|
||||
interconnect-names = "dma-mem";
|
||||
status = "disabled";
|
||||
};
|
||||
|
|
@ -864,7 +801,7 @@
|
|||
power-domains = <&power K1X_PMU_BUS_PWR_DOMAIN>;
|
||||
clk,pm-runtime,no-sleep;
|
||||
cpuidle,pm-runtime,sleep;
|
||||
interconnects = <&dram_range0>;
|
||||
interconnects = <&dram_range4>;
|
||||
interconnect-names = "dma-mem";
|
||||
status = "disabled";
|
||||
};
|
||||
|
|
@ -881,7 +818,7 @@
|
|||
power-domains = <&power K1X_PMU_BUS_PWR_DOMAIN>;
|
||||
clk,pm-runtime,no-sleep;
|
||||
cpuidle,pm-runtime,sleep;
|
||||
interconnects = <&dram_range0>;
|
||||
interconnects = <&dram_range4>;
|
||||
interconnect-names = "dma-mem";
|
||||
status = "disabled";
|
||||
};
|
||||
|
|
@ -898,7 +835,7 @@
|
|||
power-domains = <&power K1X_PMU_BUS_PWR_DOMAIN>;
|
||||
clk,pm-runtime,no-sleep;
|
||||
cpuidle,pm-runtime,sleep;
|
||||
interconnects = <&dram_range0>;
|
||||
interconnects = <&dram_range4>;
|
||||
interconnect-names = "dma-mem";
|
||||
status = "disabled";
|
||||
};
|
||||
|
|
@ -915,7 +852,7 @@
|
|||
power-domains = <&power K1X_PMU_BUS_PWR_DOMAIN>;
|
||||
clk,pm-runtime,no-sleep;
|
||||
cpuidle,pm-runtime,sleep;
|
||||
interconnects = <&dram_range0>;
|
||||
interconnects = <&dram_range4>;
|
||||
interconnect-names = "dma-mem";
|
||||
status = "disabled";
|
||||
};
|
||||
|
|
@ -932,7 +869,7 @@
|
|||
power-domains = <&power K1X_PMU_BUS_PWR_DOMAIN>;
|
||||
clk,pm-runtime,no-sleep;
|
||||
cpuidle,pm-runtime,sleep;
|
||||
interconnects = <&dram_range0>;
|
||||
interconnects = <&dram_range4>;
|
||||
interconnect-names = "dma-mem";
|
||||
status = "disabled";
|
||||
};
|
||||
|
|
@ -980,7 +917,7 @@
|
|||
power-domains = <&power K1X_PMU_BUS_PWR_DOMAIN>;
|
||||
clk,pm-runtime,no-sleep;
|
||||
cpuidle,pm-runtime,sleep;
|
||||
interconnects = <&dram_range0>;
|
||||
interconnects = <&dram_range4>;
|
||||
interconnect-names = "dma-mem";
|
||||
status = "ok";
|
||||
};
|
||||
|
|
@ -1012,7 +949,7 @@
|
|||
resets = <&reset RESET_SSPA0>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interconnects = <&dram_range0>;
|
||||
interconnects = <&dram_range4>;
|
||||
interconnect-names = "dma-mem";
|
||||
status = "disabled";
|
||||
};
|
||||
|
|
@ -1033,7 +970,7 @@
|
|||
resets = <&reset RESET_SSPA1>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interconnects = <&dram_range0>;
|
||||
interconnects = <&dram_range4>;
|
||||
interconnect-names = "dma-mem";
|
||||
status = "disabled";
|
||||
};
|
||||
|
|
@ -1052,7 +989,7 @@
|
|||
resets = <&reset RESET_SEC_SSP2>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interconnects = <&dram_range0>;
|
||||
interconnects = <&dram_range4>;
|
||||
interconnect-names = "dma-mem";
|
||||
status = "disabled";
|
||||
};
|
||||
|
|
@ -1073,7 +1010,7 @@
|
|||
resets = <&reset RESET_SSP3>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interconnects = <&dram_range0>;
|
||||
interconnects = <&dram_range4>;
|
||||
interconnect-names = "dma-mem";
|
||||
status = "disabled";
|
||||
};
|
||||
|
|
@ -1105,7 +1042,7 @@
|
|||
spacemit,apb_clock = <52000000>;
|
||||
power-domains = <&power K1X_PMU_BUS_PWR_DOMAIN>;
|
||||
cpuidle,pm-runtime,sleep;
|
||||
interconnects = <&dram_range0>;
|
||||
interconnects = <&dram_range4>;
|
||||
interconnect-names = "dma-mem";
|
||||
status = "disabled";
|
||||
};
|
||||
|
|
@ -1137,7 +1074,7 @@
|
|||
spacemit,apb_clock = <52000000>;
|
||||
power-domains = <&power K1X_PMU_BUS_PWR_DOMAIN>;
|
||||
cpuidle,pm-runtime,sleep;
|
||||
interconnects = <&dram_range0>;
|
||||
interconnects = <&dram_range4>;
|
||||
interconnect-names = "dma-mem";
|
||||
status = "disabled";
|
||||
};
|
||||
|
|
@ -1169,7 +1106,7 @@
|
|||
spacemit,apb_clock = <52000000>;
|
||||
power-domains = <&power K1X_PMU_BUS_PWR_DOMAIN>;
|
||||
cpuidle,pm-runtime,sleep;
|
||||
interconnects = <&dram_range0>;
|
||||
interconnects = <&dram_range4>;
|
||||
interconnect-names = "dma-mem";
|
||||
status = "disabled";
|
||||
};
|
||||
|
|
@ -1194,7 +1131,7 @@
|
|||
spacemit,apb_clock = <52000000>;
|
||||
power-domains = <&power K1X_PMU_BUS_PWR_DOMAIN>;
|
||||
cpuidle,pm-runtime,sleep;
|
||||
interconnects = <&dram_range0>;
|
||||
interconnects = <&dram_range4>;
|
||||
interconnect-names = "dma-mem";
|
||||
status = "disabled";
|
||||
};
|
||||
|
|
@ -1226,7 +1163,7 @@
|
|||
spacemit,apb_clock = <52000000>;
|
||||
power-domains = <&power K1X_PMU_BUS_PWR_DOMAIN>;
|
||||
cpuidle,pm-runtime,sleep;
|
||||
interconnects = <&dram_range0>;
|
||||
interconnects = <&dram_range4>;
|
||||
interconnect-names = "dma-mem";
|
||||
status = "disabled";
|
||||
};
|
||||
|
|
@ -1258,7 +1195,7 @@
|
|||
spacemit,apb_clock = <52000000>;
|
||||
power-domains = <&power K1X_PMU_BUS_PWR_DOMAIN>;
|
||||
cpuidle,pm-runtime,sleep;
|
||||
interconnects = <&dram_range0>;
|
||||
interconnects = <&dram_range4>;
|
||||
interconnect-names = "dma-mem";
|
||||
status = "disabled";
|
||||
};
|
||||
|
|
@ -1290,7 +1227,7 @@
|
|||
spacemit,apb_clock = <52000000>;
|
||||
power-domains = <&power K1X_PMU_BUS_PWR_DOMAIN>;
|
||||
cpuidle,pm-runtime,sleep;
|
||||
interconnects = <&dram_range0>;
|
||||
interconnects = <&dram_range4>;
|
||||
interconnect-names = "dma-mem";
|
||||
status = "disabled";
|
||||
};
|
||||
|
|
@ -1322,7 +1259,7 @@
|
|||
spacemit,apb_clock = <52000000>;
|
||||
power-domains = <&power K1X_PMU_BUS_PWR_DOMAIN>;
|
||||
cpuidle,pm-runtime,sleep;
|
||||
interconnects = <&dram_range0>;
|
||||
interconnects = <&dram_range4>;
|
||||
interconnect-names = "dma-mem";
|
||||
status = "disabled";
|
||||
};
|
||||
|
|
@ -1354,7 +1291,7 @@
|
|||
spacemit,apb_clock = <52000000>;
|
||||
power-domains = <&power K1X_PMU_BUS_PWR_DOMAIN>;
|
||||
cpuidle,pm-runtime,sleep;
|
||||
interconnects = <&dram_range0>;
|
||||
interconnects = <&dram_range4>;
|
||||
interconnect-names = "dma-mem";
|
||||
status = "disabled";
|
||||
};
|
||||
|
|
@ -1649,8 +1586,6 @@
|
|||
clock-names = "per","ipg";
|
||||
resets = <&reset RESET_CAN0>;
|
||||
fsl,clk-source = <0>;
|
||||
interconnects = <&dram_range0>;
|
||||
interconnect-names = "dma-mem";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -1663,8 +1598,6 @@
|
|||
clocks = <&ccu CLK_RCPU_CAN>,<&ccu CLK_RCPU_CAN_BUS>;
|
||||
clock-names = "per","ipg";
|
||||
resets = <&reset RESET_RCPU_CAN>;
|
||||
interconnects = <&dram_range0>;
|
||||
interconnect-names = "dma-mem";
|
||||
rcpu-can;
|
||||
status = "disabled";
|
||||
};
|
||||
|
|
@ -1717,7 +1650,7 @@
|
|||
power-domains = <&power K1X_PMU_BUS_PWR_DOMAIN>;
|
||||
clk,pm-runtime,no-sleep;
|
||||
cpuidle,pm-runtime,sleep;
|
||||
interconnects = <&dram_range1>;
|
||||
interconnects = <&dram_range5>;
|
||||
interconnect-names = "dma-mem";
|
||||
status = "disabled";
|
||||
};
|
||||
|
|
@ -1741,7 +1674,7 @@
|
|||
power-domains = <&power K1X_PMU_BUS_PWR_DOMAIN>;
|
||||
clk,pm-runtime,no-sleep;
|
||||
cpuidle,pm-runtime,sleep;
|
||||
interconnects = <&dram_range1>;
|
||||
interconnects = <&dram_range5>;
|
||||
interconnect-names = "dma-mem";
|
||||
status = "disabled";
|
||||
};
|
||||
|
|
@ -1796,8 +1729,9 @@
|
|||
|
||||
ehci: ehci@c0900100 {
|
||||
compatible = "spacemit,mv-ehci";
|
||||
reg = <0x0 0xc0900100 0x0 0x4000>;
|
||||
interrupts = <105>;
|
||||
reg = <0x0 0xc0900100 0x0 0x4000>,
|
||||
<0x0 0xd428287c 0x0 0x4>;
|
||||
interrupts = <105>,<106>;
|
||||
interrupt-parent = <&intc>;
|
||||
spacemit,ehci-name = "mv-ehci";
|
||||
spacemit,otg-force-a-bus-req;
|
||||
|
|
@ -1823,8 +1757,9 @@
|
|||
|
||||
ehci1: ehci1@c0980100 {
|
||||
compatible = "spacemit,mv-ehci";
|
||||
reg = <0x0 0xc0980100 0x0 0x4000>;
|
||||
interrupts = <118>;
|
||||
reg = <0x0 0xc0980100 0x0 0x4000>,
|
||||
<0x0 0xd4282bc4 0x0 0x4>;
|
||||
interrupts = <118>,<148>;
|
||||
interrupt-parent = <&intc>;
|
||||
spacemit,ehci-name = "mv-ehci";
|
||||
spacemit,otg-force-a-bus-req;
|
||||
|
|
@ -1868,6 +1803,7 @@
|
|||
compatible = "spacemit,k1-x-dwc3";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
reg = <0x0 0xd4282bc8 0x0 0x4>;
|
||||
resets = <&reset RESET_USB3_0>;
|
||||
reset-names = "ctl_rst";
|
||||
clocks = <&ccu CLK_USB30>;
|
||||
|
|
@ -2127,7 +2063,7 @@
|
|||
k1x,qspi-rx-dma = <1>;
|
||||
dmas = <&pdma0 45 1>;
|
||||
dma-names = "tx-dma";
|
||||
interconnects = <&dram_range0>;
|
||||
interconnects = <&dram_range4>;
|
||||
interconnect-names = "dma-mem";
|
||||
status = "disabled";
|
||||
};
|
||||
|
|
@ -2306,7 +2242,7 @@
|
|||
reset-names= "v2d_reset";
|
||||
interrupt-parent = <&intc>;
|
||||
interrupts = <86>;
|
||||
interconnects = <&dram_range1>;
|
||||
interconnects = <&dram_range3>;
|
||||
interconnect-names = "dma-mem";
|
||||
status = "ok";
|
||||
};
|
||||
|
|
@ -2332,7 +2268,7 @@
|
|||
jpu,cclk-min-frequency = <409000000>;
|
||||
jpu,cclk-default-frequency = <614000000>;
|
||||
page-size = <4>;
|
||||
interconnects = <&dram_range1>;
|
||||
interconnects = <&dram_range5>;
|
||||
interconnect-names = "dma-mem";
|
||||
clk,pm-runtime,no-sleep;
|
||||
status = "okay";
|
||||
|
|
@ -2367,9 +2303,24 @@
|
|||
num-engines = <1>;
|
||||
clocks = <&ccu CLK_AES>;
|
||||
resets = <&reset RESET_AES>;
|
||||
interconnects = <&dram_range5>;
|
||||
interconnect-names = "dma-mem";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
efuse: fuse@f0702800 {
|
||||
compatible = "simple-mfd";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 0x0 0xf0702800 0x400>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
socinfo: socinfo@0 {
|
||||
compatible = "spacemit,socinfo-k1x";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ciu: ciu@d4282c00 {
|
||||
compatible = "spacemit,aquila-ciu", "spacemit,ciu", "syscon";
|
||||
reg = <0x0 0xd4282c00 0x0 0x2d0>;
|
||||
|
|
@ -2510,6 +2461,8 @@
|
|||
compatible = "spacemit,simple-audio-card";
|
||||
simple-audio-card,name = "snd-hdmi";
|
||||
status = "disabled";
|
||||
interconnects = <&dram_range4>;
|
||||
interconnect-names = "dma-mem";
|
||||
simple-audio-card,cpu {
|
||||
sound-dai = <&hdmi_sspa>;
|
||||
};
|
||||
|
|
@ -2525,6 +2478,8 @@
|
|||
compatible = "spacemit,simple-audio-card";
|
||||
simple-audio-card,format = "i2s";
|
||||
status = "disabled";
|
||||
interconnects = <&dram_range4>;
|
||||
interconnect-names = "dma-mem";
|
||||
spacemit,init-jack;
|
||||
simple-audio-card,cpu {
|
||||
sound-dai = <&i2s0>;
|
||||
|
|
|
|||
|
|
@ -4,11 +4,13 @@
|
|||
/dts-v1/;
|
||||
|
||||
#include "k1-x.dtsi"
|
||||
#include "k1-x-efuse.dtsi"
|
||||
#include "k1-x_pinctrl.dtsi"
|
||||
#include "lcd_gx09inx101_mipi.dtsi"
|
||||
#include "k1-x-hdmi.dtsi"
|
||||
#include "k1-x-lcd.dtsi"
|
||||
#include "k1-x-camera-sdk.dtsi"
|
||||
#include "k1-x_opp_table.dtsi"
|
||||
|
||||
/ {
|
||||
model = "spacemit k1-x deb1 board";
|
||||
|
|
@ -147,8 +149,11 @@
|
|||
|
||||
wlan_pwrseq: wlan-pwrseq {
|
||||
compatible = "spacemit,wlan-pwrseq";
|
||||
regon-gpios = <&gpio 116 0>;
|
||||
hostwake-gpios = <&gpio 66 0>;
|
||||
regon-gpios = <&gpio 116 0>;
|
||||
interrupt-parent = <&pinctrl>;
|
||||
interrupts = <268>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_wlan_wakeup>;
|
||||
};
|
||||
|
||||
bt_pwrseq: bt-pwrseq {
|
||||
|
|
@ -243,13 +248,6 @@
|
|||
status = "okay";
|
||||
};
|
||||
|
||||
&i2c1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_i2c1>;
|
||||
spacemit,i2c-fast-mode;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2c2 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_i2c2_0>;
|
||||
|
|
@ -551,7 +549,7 @@
|
|||
&range GPIO_58 1 (MUX_MODE0 | EDGE_NONE | PULL_UP | PAD_1V8_DS2)
|
||||
&range GPIO_63 2 (MUX_MODE0 | EDGE_NONE | PULL_UP | PAD_1V8_DS2)
|
||||
&range GPIO_65 1 (MUX_MODE0 | EDGE_NONE | PULL_UP | PAD_1V8_DS2)
|
||||
&range GPIO_66 2 (MUX_MODE0 | EDGE_NONE | PULL_UP | PAD_3V_DS4)
|
||||
&range GPIO_67 1 (MUX_MODE0 | EDGE_NONE | PULL_UP | PAD_3V_DS4)
|
||||
&range PRI_TDI 2 (MUX_MODE1 | EDGE_NONE | PULL_UP | PAD_1V8_DS2)
|
||||
&range PRI_TCK 1 (MUX_MODE1 | EDGE_NONE | PULL_DOWN | PAD_1V8_DS2)
|
||||
&range PRI_TDO 1 (MUX_MODE1 | EDGE_NONE | PULL_UP | PAD_1V8_DS2)
|
||||
|
|
@ -622,13 +620,20 @@
|
|||
K1X_PADCONF(GPIO_46, MUX_MODE1, (EDGE_NONE | PULL_DIS | PAD_1V8_DS2)) /* gmac1_clk_ref */
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_wlan_wakeup: wlan_wakeup_grp {
|
||||
pinctrl-single,pins =<
|
||||
K1X_PADCONF(GPIO_66, MUX_MODE0, (EDGE_FALL | PULL_DOWN | PAD_3V_DS2)) /* wifi edge detect */
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
&gpio{
|
||||
gpio-ranges = <
|
||||
&pinctrl 49 GPIO_49 2
|
||||
&pinctrl 58 GPIO_58 1
|
||||
&pinctrl 63 GPIO_63 5
|
||||
&pinctrl 63 GPIO_63 3
|
||||
&pinctrl 67 GPIO_67 1
|
||||
&pinctrl 70 PRI_TDI 4
|
||||
&pinctrl 74 GPIO_74 1
|
||||
&pinctrl 80 GPIO_80 4
|
||||
|
|
@ -994,23 +999,6 @@
|
|||
power-domains = <&power K1X_PMU_ISP_PWR_DOMAIN>;
|
||||
};
|
||||
|
||||
&cpu_0 {
|
||||
clst0-supply = <&dcdc_1>;
|
||||
vin-supply-names = "clst0";
|
||||
};
|
||||
|
||||
&clst0_core_opp_table {
|
||||
opp1600000000 {
|
||||
opp-microvolt = <1050000>;
|
||||
};
|
||||
};
|
||||
|
||||
&clst1_core_opp_table {
|
||||
opp1600000000 {
|
||||
opp-microvolt = <1050000>;
|
||||
};
|
||||
};
|
||||
|
||||
&rcpu {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_rcpu>;
|
||||
|
|
|
|||
|
|
@ -0,0 +1,110 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
|
||||
/* Copyright (c) 2024 Spacemit, Inc */
|
||||
|
||||
&cpus {
|
||||
clst_core_opp_table0: opp_table0 {
|
||||
compatible = "operating-points-v2";
|
||||
opp-shared;
|
||||
|
||||
clocks = <&ccu CLK_CPU_C0_ACE>, <&ccu CLK_CPU_C1_ACE>, <&ccu CLK_CPU_C0_TCM>,
|
||||
<&ccu CLK_CCI550>, <&ccu CLK_PLL3>;
|
||||
clock-names = "ace0","ace1","tcm","cci","pll3";
|
||||
cci-hz = /bits/ 64 <614000000>;
|
||||
|
||||
opp1600000000 {
|
||||
opp-hz = /bits/ 64 <1600000000>, /bits/ 64 <1600000000>;
|
||||
tcm-hz = /bits/ 64 <800000000>;
|
||||
ace-hz = /bits/ 64 <800000000>;
|
||||
opp-microvolt = <1050000>;
|
||||
clock-latency-ns = <200000>;
|
||||
};
|
||||
|
||||
opp1228800000 {
|
||||
opp-hz = /bits/ 64 <1228800000>, /bits/ 64 <1228800000>;
|
||||
tcm-hz = /bits/ 64 <614400000>;
|
||||
ace-hz = /bits/ 64 <614400000>;
|
||||
opp-microvolt = <950000>;
|
||||
clock-latency-ns = <200000>;
|
||||
};
|
||||
|
||||
opp1000000000 {
|
||||
opp-hz = /bits/ 64 <1000000000>, /bits/ 64 <1000000000>;
|
||||
tcm-hz = /bits/ 64 <500000000>;
|
||||
ace-hz = /bits/ 64 <500000000>;
|
||||
opp-microvolt = <950000>;
|
||||
clock-latency-ns = <200000>;
|
||||
};
|
||||
|
||||
opp819000000 {
|
||||
opp-hz = /bits/ 64 <819000000>, /bits/ 64 <819000000>;
|
||||
opp-microvolt = <950000>;
|
||||
tcm-hz = /bits/ 64 <409500000>;
|
||||
ace-hz = /bits/ 64 <409500000>;
|
||||
clock-latency-ns = <200000>;
|
||||
};
|
||||
|
||||
opp614400000 {
|
||||
opp-hz = /bits/ 64 <614400000>, /bits/ 64 <614400000>;
|
||||
tcm-hz = /bits/ 64 <307200000>;
|
||||
ace-hz = /bits/ 64 <307200000>;
|
||||
opp-microvolt = <950000>;
|
||||
clock-latency-ns = <200000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&cpu_0 {
|
||||
clst-supply = <&dcdc_1>;
|
||||
clocks = <&ccu CLK_CPU_C0_CORE>, <&ccu CLK_CPU_C1_CORE>;
|
||||
clock-names = "cls0", "cls1";
|
||||
operating-points-v2 = <&clst_core_opp_table0>;
|
||||
};
|
||||
|
||||
&cpu_1 {
|
||||
clst-supply = <&dcdc_1>;
|
||||
clocks = <&ccu CLK_CPU_C0_CORE>, <&ccu CLK_CPU_C1_CORE>;
|
||||
clock-names = "cls0", "cls1";
|
||||
operating-points-v2 = <&clst_core_opp_table0>;
|
||||
};
|
||||
|
||||
&cpu_2 {
|
||||
clst-supply = <&dcdc_1>;
|
||||
clocks = <&ccu CLK_CPU_C0_CORE>, <&ccu CLK_CPU_C1_CORE>;
|
||||
clock-names = "cls0", "cls1";
|
||||
operating-points-v2 = <&clst_core_opp_table0>;
|
||||
};
|
||||
|
||||
&cpu_3 {
|
||||
clst-supply = <&dcdc_1>;
|
||||
clocks = <&ccu CLK_CPU_C0_CORE>, <&ccu CLK_CPU_C1_CORE>;
|
||||
clock-names = "cls0", "cls1";
|
||||
operating-points-v2 = <&clst_core_opp_table0>;
|
||||
};
|
||||
|
||||
&cpu_4 {
|
||||
clst-supply = <&dcdc_1>;
|
||||
clocks = <&ccu CLK_CPU_C0_CORE>, <&ccu CLK_CPU_C1_CORE>;
|
||||
clock-names = "cls0", "cls1";
|
||||
operating-points-v2 = <&clst_core_opp_table0>;
|
||||
};
|
||||
|
||||
&cpu_5 {
|
||||
clst-supply = <&dcdc_1>;
|
||||
clocks = <&ccu CLK_CPU_C0_CORE>, <&ccu CLK_CPU_C1_CORE>;
|
||||
clock-names = "cls0", "cls1";
|
||||
operating-points-v2 = <&clst_core_opp_table0>;
|
||||
};
|
||||
|
||||
&cpu_6 {
|
||||
clst-supply = <&dcdc_1>;
|
||||
clocks = <&ccu CLK_CPU_C0_CORE>, <&ccu CLK_CPU_C1_CORE>;
|
||||
clock-names = "cls0", "cls1";
|
||||
operating-points-v2 = <&clst_core_opp_table0>;
|
||||
};
|
||||
|
||||
&cpu_7 {
|
||||
clst-supply = <&dcdc_1>;
|
||||
clocks = <&ccu CLK_CPU_C0_CORE>, <&ccu CLK_CPU_C1_CORE>;
|
||||
clock-names = "cls0", "cls1";
|
||||
operating-points-v2 = <&clst_core_opp_table0>;
|
||||
};
|
||||
|
|
@ -0,0 +1,234 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
|
||||
/* Copyright (c) 2023 Spacemit, Inc */
|
||||
|
||||
&cpus {
|
||||
clst_core_opp_table0: opp_table0 {
|
||||
compatible = "operating-points-v2";
|
||||
opp-shared;
|
||||
|
||||
clocks = <&ccu CLK_CPU_C0_ACE>, <&ccu CLK_CPU_C1_ACE>, <&ccu CLK_CPU_C0_TCM>,
|
||||
<&ccu CLK_CCI550>, <&ccu CLK_PLL3>;
|
||||
clock-names = "ace0","ace1","tcm","cci","pll3";
|
||||
cci-hz = /bits/ 64 <614000000>;
|
||||
|
||||
opp1800000000 {
|
||||
opp-hz = /bits/ 64 <1800000000>, /bits/ 64 <1800000000>;
|
||||
tcm-hz = /bits/ 64 <900000000>;
|
||||
ace-hz = /bits/ 64 <900000000>;
|
||||
opp-microvolt = <1160000>;
|
||||
clock-latency-ns = <200000>;
|
||||
};
|
||||
|
||||
opp1600000000 {
|
||||
opp-hz = /bits/ 64 <1600000000>, /bits/ 64 <1600000000>;
|
||||
tcm-hz = /bits/ 64 <800000000>;
|
||||
ace-hz = /bits/ 64 <800000000>;
|
||||
opp-microvolt = <1050000>;
|
||||
clock-latency-ns = <200000>;
|
||||
};
|
||||
|
||||
opp1228800000 {
|
||||
opp-hz = /bits/ 64 <1228800000>, /bits/ 64 <1228800000>;
|
||||
tcm-hz = /bits/ 64 <614400000>;
|
||||
ace-hz = /bits/ 64 <614400000>;
|
||||
opp-microvolt = <950000>;
|
||||
clock-latency-ns = <200000>;
|
||||
};
|
||||
|
||||
opp1000000000 {
|
||||
opp-hz = /bits/ 64 <1000000000>, /bits/ 64 <1000000000>;
|
||||
tcm-hz = /bits/ 64 <500000000>;
|
||||
ace-hz = /bits/ 64 <500000000>;
|
||||
opp-microvolt = <950000>;
|
||||
clock-latency-ns = <200000>;
|
||||
};
|
||||
|
||||
opp819000000 {
|
||||
opp-hz = /bits/ 64 <819000000>, /bits/ 64 <819000000>;
|
||||
opp-microvolt = <950000>;
|
||||
tcm-hz = /bits/ 64 <409500000>;
|
||||
ace-hz = /bits/ 64 <409500000>;
|
||||
clock-latency-ns = <200000>;
|
||||
};
|
||||
|
||||
opp614400000 {
|
||||
opp-hz = /bits/ 64 <614400000>, /bits/ 64 <614400000>;
|
||||
tcm-hz = /bits/ 64 <307200000>;
|
||||
ace-hz = /bits/ 64 <307200000>;
|
||||
opp-microvolt = <950000>;
|
||||
clock-latency-ns = <200000>;
|
||||
};
|
||||
};
|
||||
|
||||
clst_core_opp_table1: opp_table1 {
|
||||
compatible = "operating-points-v2";
|
||||
opp-shared;
|
||||
|
||||
clocks = <&ccu CLK_CPU_C0_ACE>, <&ccu CLK_CPU_C1_ACE>, <&ccu CLK_CPU_C0_TCM>,
|
||||
<&ccu CLK_CCI550>, <&ccu CLK_PLL3>;
|
||||
clock-names = "ace0","ace1","tcm","cci","pll3";
|
||||
cci-hz = /bits/ 64 <614000000>;
|
||||
|
||||
opp1800000000 {
|
||||
opp-hz = /bits/ 64 <1800000000>, /bits/ 64 <1800000000>;
|
||||
tcm-hz = /bits/ 64 <900000000>;
|
||||
ace-hz = /bits/ 64 <900000000>;
|
||||
opp-microvolt = <1100000>;
|
||||
clock-latency-ns = <200000>;
|
||||
};
|
||||
|
||||
opp1600000000 {
|
||||
opp-hz = /bits/ 64 <1600000000>, /bits/ 64 <1600000000>;
|
||||
tcm-hz = /bits/ 64 <800000000>;
|
||||
ace-hz = /bits/ 64 <800000000>;
|
||||
opp-microvolt = <1050000>;
|
||||
clock-latency-ns = <200000>;
|
||||
};
|
||||
|
||||
opp1228800000 {
|
||||
opp-hz = /bits/ 64 <1228800000>, /bits/ 64 <1228800000>;
|
||||
tcm-hz = /bits/ 64 <614400000>;
|
||||
ace-hz = /bits/ 64 <614400000>;
|
||||
opp-microvolt = <950000>;
|
||||
clock-latency-ns = <200000>;
|
||||
};
|
||||
|
||||
opp1000000000 {
|
||||
opp-hz = /bits/ 64 <1000000000>, /bits/ 64 <1000000000>;
|
||||
tcm-hz = /bits/ 64 <500000000>;
|
||||
ace-hz = /bits/ 64 <500000000>;
|
||||
opp-microvolt = <950000>;
|
||||
clock-latency-ns = <200000>;
|
||||
};
|
||||
|
||||
opp819000000 {
|
||||
opp-hz = /bits/ 64 <819000000>, /bits/ 64 <819000000>;
|
||||
opp-microvolt = <950000>;
|
||||
tcm-hz = /bits/ 64 <409500000>;
|
||||
ace-hz = /bits/ 64 <409500000>;
|
||||
clock-latency-ns = <200000>;
|
||||
};
|
||||
|
||||
opp614400000 {
|
||||
opp-hz = /bits/ 64 <614400000>, /bits/ 64 <614400000>;
|
||||
tcm-hz = /bits/ 64 <307200000>;
|
||||
ace-hz = /bits/ 64 <307200000>;
|
||||
opp-microvolt = <950000>;
|
||||
clock-latency-ns = <200000>;
|
||||
};
|
||||
};
|
||||
|
||||
clst_core_opp_table2: opp_table2 {
|
||||
compatible = "operating-points-v2";
|
||||
opp-shared;
|
||||
|
||||
clocks = <&ccu CLK_CPU_C0_ACE>, <&ccu CLK_CPU_C1_ACE>, <&ccu CLK_CPU_C0_TCM>,
|
||||
<&ccu CLK_CCI550>, <&ccu CLK_PLL3>;
|
||||
clock-names = "ace0","ace1","tcm","cci","pll3";
|
||||
cci-hz = /bits/ 64 <614000000>;
|
||||
|
||||
opp1800000000 {
|
||||
opp-hz = /bits/ 64 <1800000000>, /bits/ 64 <1800000000>;
|
||||
tcm-hz = /bits/ 64 <900000000>;
|
||||
ace-hz = /bits/ 64 <900000000>;
|
||||
opp-microvolt = <1050000>;
|
||||
clock-latency-ns = <200000>;
|
||||
};
|
||||
|
||||
opp1600000000 {
|
||||
opp-hz = /bits/ 64 <1600000000>, /bits/ 64 <1600000000>;
|
||||
tcm-hz = /bits/ 64 <800000000>;
|
||||
ace-hz = /bits/ 64 <800000000>;
|
||||
opp-microvolt = <1050000>;
|
||||
clock-latency-ns = <200000>;
|
||||
};
|
||||
|
||||
opp1228800000 {
|
||||
opp-hz = /bits/ 64 <1228800000>, /bits/ 64 <1228800000>;
|
||||
tcm-hz = /bits/ 64 <614400000>;
|
||||
ace-hz = /bits/ 64 <614400000>;
|
||||
opp-microvolt = <950000>;
|
||||
clock-latency-ns = <200000>;
|
||||
};
|
||||
|
||||
opp1000000000 {
|
||||
opp-hz = /bits/ 64 <1000000000>, /bits/ 64 <1000000000>;
|
||||
tcm-hz = /bits/ 64 <500000000>;
|
||||
ace-hz = /bits/ 64 <500000000>;
|
||||
opp-microvolt = <950000>;
|
||||
clock-latency-ns = <200000>;
|
||||
};
|
||||
|
||||
opp819000000 {
|
||||
opp-hz = /bits/ 64 <819000000>, /bits/ 64 <819000000>;
|
||||
opp-microvolt = <950000>;
|
||||
tcm-hz = /bits/ 64 <409500000>;
|
||||
ace-hz = /bits/ 64 <409500000>;
|
||||
clock-latency-ns = <200000>;
|
||||
};
|
||||
|
||||
opp614400000 {
|
||||
opp-hz = /bits/ 64 <614400000>, /bits/ 64 <614400000>;
|
||||
tcm-hz = /bits/ 64 <307200000>;
|
||||
ace-hz = /bits/ 64 <307200000>;
|
||||
opp-microvolt = <950000>;
|
||||
clock-latency-ns = <200000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&cpu_0 {
|
||||
clst-supply = <&dcdc_1>;
|
||||
clocks = <&ccu CLK_CPU_C0_CORE>, <&ccu CLK_CPU_C1_CORE>;
|
||||
clock-names = "cls0", "cls1";
|
||||
operating-points-v2 = <&clst_core_opp_table0>, <&clst_core_opp_table1>, <&clst_core_opp_table2>;
|
||||
};
|
||||
|
||||
&cpu_1 {
|
||||
clst-supply = <&dcdc_1>;
|
||||
clocks = <&ccu CLK_CPU_C0_CORE>, <&ccu CLK_CPU_C1_CORE>;
|
||||
clock-names = "cls0", "cls1";
|
||||
operating-points-v2 = <&clst_core_opp_table0>, <&clst_core_opp_table1>, <&clst_core_opp_table2>;
|
||||
};
|
||||
|
||||
&cpu_2 {
|
||||
clst-supply = <&dcdc_1>;
|
||||
clocks = <&ccu CLK_CPU_C0_CORE>, <&ccu CLK_CPU_C1_CORE>;
|
||||
clock-names = "cls0", "cls1";
|
||||
operating-points-v2 = <&clst_core_opp_table0>, <&clst_core_opp_table1>, <&clst_core_opp_table2>;
|
||||
};
|
||||
|
||||
&cpu_3 {
|
||||
clst-supply = <&dcdc_1>;
|
||||
clocks = <&ccu CLK_CPU_C0_CORE>, <&ccu CLK_CPU_C1_CORE>;
|
||||
clock-names = "cls0", "cls1";
|
||||
operating-points-v2 = <&clst_core_opp_table0>, <&clst_core_opp_table1>, <&clst_core_opp_table2>;
|
||||
};
|
||||
|
||||
&cpu_4 {
|
||||
clst-supply = <&dcdc_1>;
|
||||
clocks = <&ccu CLK_CPU_C0_CORE>, <&ccu CLK_CPU_C1_CORE>;
|
||||
clock-names = "cls0", "cls1";
|
||||
operating-points-v2 = <&clst_core_opp_table0>, <&clst_core_opp_table1>, <&clst_core_opp_table2>;
|
||||
};
|
||||
|
||||
&cpu_5 {
|
||||
clst-supply = <&dcdc_1>;
|
||||
clocks = <&ccu CLK_CPU_C0_CORE>, <&ccu CLK_CPU_C1_CORE>;
|
||||
clock-names = "cls0", "cls1";
|
||||
operating-points-v2 = <&clst_core_opp_table0>, <&clst_core_opp_table1>, <&clst_core_opp_table2>;
|
||||
};
|
||||
|
||||
&cpu_6 {
|
||||
clst-supply = <&dcdc_1>;
|
||||
clocks = <&ccu CLK_CPU_C0_CORE>, <&ccu CLK_CPU_C1_CORE>;
|
||||
clock-names = "cls0", "cls1";
|
||||
operating-points-v2 = <&clst_core_opp_table0>, <&clst_core_opp_table1>, <&clst_core_opp_table2>;
|
||||
};
|
||||
|
||||
&cpu_7 {
|
||||
clst-supply = <&dcdc_1>;
|
||||
clocks = <&ccu CLK_CPU_C0_CORE>, <&ccu CLK_CPU_C1_CORE>;
|
||||
clock-names = "cls0", "cls1";
|
||||
operating-points-v2 = <&clst_core_opp_table0>, <&clst_core_opp_table1>, <&clst_core_opp_table2>;
|
||||
};
|
||||
|
|
@ -0,0 +1,76 @@
|
|||
/ {
|
||||
sram {
|
||||
compatible = "mmio-sram";
|
||||
/* 256k */
|
||||
reg = <0x0 0x2f902000 0x0 0x3e000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x0 0x0 0x2f902000 0x3e000>;
|
||||
|
||||
/* channel 0*/
|
||||
cpu_scp_lpri0: scp-sram@2f900000 {
|
||||
compatible = "arm,scmi-shmem";
|
||||
reg = <0x0 0x80>;
|
||||
};
|
||||
|
||||
/* channel 1*/
|
||||
cpu_scp_lpri1: scp-sram@2f900080 {
|
||||
compatible = "arm,scmi-shmem";
|
||||
reg = <0x80 0x80>;
|
||||
};
|
||||
|
||||
/* channel 2*/
|
||||
cpu_scp_lpri2: scp-sram@2f900100 {
|
||||
compatible = "arm,scmi-shmem";
|
||||
reg = <0x100 0x80>;
|
||||
};
|
||||
|
||||
/* channel 3*/
|
||||
cpu_scp_lpri3: scp-sram@2f900180 {
|
||||
compatible = "arm,scmi-shmem";
|
||||
reg = <0x180 0x80>;
|
||||
};
|
||||
};
|
||||
|
||||
firmware {
|
||||
scmi {
|
||||
compatible = "arm,scmi";
|
||||
mbox-names = "tx", "rx";
|
||||
mboxes = <&mailbox 0 &mailbox 2>;
|
||||
shmem = <&cpu_scp_lpri0 &cpu_scp_lpri0>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
scmi_vold: protocol@23 {
|
||||
reg = <0x17>;
|
||||
regulators {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
regulator_devlittle: regulator@0 {
|
||||
reg = <0x0>;
|
||||
regulator-min-microvolt = <820000>;
|
||||
regulator-max-microvolt = <1000000>;
|
||||
};
|
||||
|
||||
regulator_devgpu: regulator@1 {
|
||||
reg = <0x1>;
|
||||
regulator-min-microvolt = <820000>;
|
||||
regulator-max-microvolt = <900000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
scmi_devpd: protocol@11 {
|
||||
reg = <0x11>;
|
||||
#power-domain-cells = <1>;
|
||||
};
|
||||
|
||||
scmi_dvfs: protocol@13 {
|
||||
reg = <0x13>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
|
|
@ -9,18 +9,13 @@
|
|||
model = "BananaPi BPI-F3";
|
||||
};
|
||||
|
||||
&pcie2_rc {
|
||||
num-lanes = <1>;
|
||||
};
|
||||
|
||||
&uart2 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart2>;
|
||||
status = "okay";
|
||||
status = "disabled";
|
||||
|
||||
bluetooth {
|
||||
compatible = "realtek,rtl8852bs-bt";
|
||||
device-wake-gpios = <&gpio 64 GPIO_ACTIVE_HIGH>;
|
||||
host-wake-gpios = <&gpio 65 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
};
|
||||
|
|
|
|||
Loading…
Reference in New Issue