Update rk3588-edge to 6.7-rc.1 and add support for VOP2, Crypto, HW RNG (#5928)

* Update rk3588-edge to 6.7-rc1 kernel * Update patches for rk3588-edge and add support for crypto, trng, hdmi tx, vop2
2023-11-20 00:30:26 +03:00 · 2023-11-20 00:30:26 +03:00 · af3b4fafec
parent 8a4dbdfad5
commit af3b4fafec
15 changed files with 18168 additions and 2855 deletions
--- a/config/kernel/linux-rockchip-rk3588-edge.config
+++ b/config/kernel/linux-rockchip-rk3588-edge.config
@ -1,6 +1,6 @@
 #
 # Automatically generated file; DO NOT EDIT.
-# Linux/arm64 6.6.1 Kernel Configuration
+# Linux/arm64 6.7.0-rc1 Kernel Configuration
 #
 CONFIG_CC_VERSION_TEXT="aarch64-linux-gnu-gcc (Ubuntu 11.4.0-1ubuntu1~22.04) 11.4.0"
 CONFIG_CC_IS_GCC=y
@ -334,6 +334,7 @@ CONFIG_BUILTIN_RETURN_ADDRESS_STRIPS_PAC=y
 # CONFIG_ARCH_NXP is not set
 # CONFIG_ARCH_MA35 is not set
 # CONFIG_ARCH_NPCM is not set
+# CONFIG_ARCH_PENSANDO is not set
 # CONFIG_ARCH_QCOM is not set
 # CONFIG_ARCH_REALTEK is not set
 # CONFIG_ARCH_RENESAS is not set
@ -445,6 +446,7 @@ CONFIG_ARCH_SUPPORTS_KEXEC_SIG=y
 CONFIG_ARCH_SUPPORTS_KEXEC_IMAGE_VERIFY_SIG=y
 CONFIG_ARCH_DEFAULT_KEXEC_IMAGE_VERIFY_SIG=y
 CONFIG_ARCH_SUPPORTS_CRASH_DUMP=y
+CONFIG_ARCH_HAS_GENERIC_CRASHKERNEL_RESERVATION=y
 CONFIG_TRANS_TABLE=y
 CONFIG_XEN_DOM0=y
 CONFIG_XEN=y
@ -1003,6 +1005,7 @@ CONFIG_MIGRATION=y
 CONFIG_ARCH_ENABLE_HUGEPAGE_MIGRATION=y
 CONFIG_ARCH_ENABLE_THP_MIGRATION=y
 CONFIG_CONTIG_ALLOC=y
+CONFIG_PCP_BATCH_SCALE_MAX=5
 CONFIG_PHYS_ADDR_T_64BIT=y
 CONFIG_MMU_NOTIFIER=y
 CONFIG_KSM=y
@ -1159,6 +1162,8 @@ CONFIG_TCP_CONG_BBR=m
 # CONFIG_DEFAULT_CUBIC is not set
 CONFIG_DEFAULT_RENO=y
 CONFIG_DEFAULT_TCP_CONG="reno"
+CONFIG_TCP_SIGPOOL=y
+# CONFIG_TCP_AO is not set
 CONFIG_TCP_MD5SIG=y
 CONFIG_IPV6=y
 CONFIG_IPV6_ROUTER_PREF=y
@ -1636,9 +1641,6 @@ CONFIG_VLAN_8021Q_MVRP=y
 CONFIG_LLC=y
 CONFIG_LLC2=m
 CONFIG_ATALK=m
-CONFIG_DEV_APPLETALK=m
-CONFIG_IPDDP=m
-CONFIG_IPDDP_ENCAP=y
 CONFIG_X25=m
 CONFIG_LAPB=m
 CONFIG_PHONET=m
@ -1932,6 +1934,7 @@ CONFIG_CFG80211_DEFAULT_PS=y
 CONFIG_CFG80211_CRDA_SUPPORT=y
 CONFIG_CFG80211_WEXT=y
 CONFIG_CFG80211_WEXT_EXPORT=y
+# CONFIG_CFG80211_KUNIT_TEST is not set
 CONFIG_LIB80211=m
 CONFIG_LIB80211_CRYPT_WEP=m
 CONFIG_LIB80211_CRYPT_CCMP=m
@ -1942,6 +1945,7 @@ CONFIG_MAC80211_HAS_RC=y
 CONFIG_MAC80211_RC_MINSTREL=y
 CONFIG_MAC80211_RC_DEFAULT_MINSTREL=y
 CONFIG_MAC80211_RC_DEFAULT="minstrel_ht"
+# CONFIG_MAC80211_KUNIT_TEST is not set
 CONFIG_MAC80211_MESH=y
 CONFIG_MAC80211_LEDS=y
 # CONFIG_MAC80211_DEBUGFS is not set
@ -2022,6 +2026,7 @@ CONFIG_PAGE_POOL_STATS=y
 CONFIG_FAILOVER=y
 CONFIG_ETHTOOL_NETLINK=y
 # CONFIG_NETDEV_ADDR_LIST_TEST is not set
+# CONFIG_NET_TEST is not set

 #
 # Device Drivers
@ -2036,6 +2041,7 @@ CONFIG_PCIEPORTBUS=y
 CONFIG_HOTPLUG_PCI_PCIE=y
 CONFIG_PCIEAER=y
 CONFIG_PCIEAER_INJECT=m
+CONFIG_PCIEAER_CXL=y
 CONFIG_PCIE_ECRC=y
 CONFIG_PCIEASPM=y
 CONFIG_PCIEASPM_DEFAULT=y
@ -2068,6 +2074,7 @@ CONFIG_VGA_ARB=y
 CONFIG_VGA_ARB_MAX_GPUS=16
 CONFIG_HOTPLUG_PCI=y
 CONFIG_HOTPLUG_PCI_ACPI=y
+# CONFIG_HOTPLUG_PCI_ACPI_AMPERE_ALTRA is not set
 # CONFIG_HOTPLUG_PCI_ACPI_IBM is not set
 # CONFIG_HOTPLUG_PCI_CPCI is not set
 # CONFIG_HOTPLUG_PCI_SHPC is not set
@ -2185,6 +2192,7 @@ CONFIG_DEV_COREDUMP=y
 CONFIG_HMEM_REPORTING=y
 # CONFIG_TEST_ASYNC_DRIVER_PROBE is not set
 # CONFIG_DM_KUNIT_TEST is not set
+# CONFIG_DRIVER_PE_KUNIT_TEST is not set
 CONFIG_SYS_HYPERVISOR=y
 CONFIG_GENERIC_CPU_AUTOPROBE=y
 CONFIG_GENERIC_CPU_VULNERABILITIES=y
@ -2214,7 +2222,6 @@ CONFIG_GENERIC_ARCH_NUMA=y
 #
 CONFIG_ARM_CCI=y
 CONFIG_ARM_CCI400_COMMON=y
-CONFIG_BRCMSTB_GISB_ARB=y
 # CONFIG_MOXTET is not set
 CONFIG_VEXPRESS_CONFIG=y
 CONFIG_MHI_BUS=m
@ -2250,6 +2257,7 @@ CONFIG_ARM_SCMI_TRANSPORT_VIRTIO=y
 CONFIG_ARM_SCMI_TRANSPORT_VIRTIO_VERSION1_COMPLIANCE=y
 # CONFIG_ARM_SCMI_TRANSPORT_VIRTIO_ATOMIC_ENABLE is not set
 CONFIG_ARM_SCMI_POWER_DOMAIN=y
+CONFIG_ARM_SCMI_PERF_DOMAIN=y
 CONFIG_ARM_SCMI_POWER_CONTROL=m
 # end of ARM System Control and Management Interface Protocol

@ -2295,6 +2303,12 @@ CONFIG_UEFI_CPER=y
 CONFIG_UEFI_CPER_ARM=y
 CONFIG_ARM_PSCI_FW=y
 CONFIG_ARM_PSCI_CHECKER=y
+
+#
+# Qualcomm firmware drivers
+#
+# end of Qualcomm firmware drivers
+
 CONFIG_HAVE_ARM_SMCCC=y
 CONFIG_HAVE_ARM_SMCCC_DISCOVERY=y
 CONFIG_ARM_SMCCC_SOC_ID=y
@ -2317,7 +2331,6 @@ CONFIG_MTD=y
 #
 # Partition parsers
 #
-# CONFIG_MTD_AR7_PARTS is not set
 CONFIG_MTD_CMDLINE_PARTS=m
 CONFIG_MTD_OF_PARTS=y
 CONFIG_MTD_AFS_PARTS=m
@ -2527,7 +2540,7 @@ CONFIG_BLKDEV_UBLK_LEGACY_OPCODES=y
 #
 # NVME Support
 #
-CONFIG_NVME_COMMON=y
+CONFIG_NVME_AUTH=m
 CONFIG_NVME_CORE=y
 CONFIG_BLK_DEV_NVME=y
 CONFIG_NVME_MULTIPATH=y
@ -2536,13 +2549,15 @@ CONFIG_NVME_HWMON=y
 CONFIG_NVME_FABRICS=m
 CONFIG_NVME_FC=m
 CONFIG_NVME_TCP=m
-CONFIG_NVME_AUTH=y
+# CONFIG_NVME_TCP_TLS is not set
+# CONFIG_NVME_HOST_AUTH is not set
 CONFIG_NVME_TARGET=m
 CONFIG_NVME_TARGET_PASSTHRU=y
 CONFIG_NVME_TARGET_LOOP=m
 CONFIG_NVME_TARGET_FC=m
 CONFIG_NVME_TARGET_FCLOOP=m
 CONFIG_NVME_TARGET_TCP=m
+# CONFIG_NVME_TARGET_TCP_TLS is not set
 CONFIG_NVME_TARGET_AUTH=y
 # end of NVME Support

@ -2584,7 +2599,6 @@ CONFIG_VCPU_STALL_DETECTOR=m
 #
 CONFIG_EEPROM_AT24=m
 CONFIG_EEPROM_AT25=m
-CONFIG_EEPROM_LEGACY=m
 CONFIG_EEPROM_MAX6875=m
 CONFIG_EEPROM_93CX6=m
 # CONFIG_EEPROM_93XX46 is not set
@ -2854,7 +2868,6 @@ CONFIG_MD_FAULTY=m
 CONFIG_MD_CLUSTER=m
 CONFIG_BCACHE=m
 # CONFIG_BCACHE_DEBUG is not set
-# CONFIG_BCACHE_CLOSURES_DEBUG is not set
 # CONFIG_BCACHE_ASYNC_REGISTRATION is not set
 CONFIG_BLK_DEV_DM_BUILTIN=y
 CONFIG_BLK_DEV_DM=m
@ -2957,6 +2970,7 @@ CONFIG_TUN_VNET_CROSS_LE=y
 CONFIG_VETH=m
 CONFIG_VIRTIO_NET=m
 CONFIG_NLMON=m
+# CONFIG_NETKIT is not set
 CONFIG_NET_VRF=m
 CONFIG_MHI_NET=m
 # CONFIG_ARCNET is not set
@ -3163,6 +3177,7 @@ CONFIG_I40EVF=m
 # CONFIG_ICE is not set
 CONFIG_FM10K=m
 # CONFIG_IGC is not set
+# CONFIG_IDPF is not set
 CONFIG_JME=m
 CONFIG_NET_VENDOR_ADI=y
 CONFIG_ADIN1110=m
@ -3202,6 +3217,7 @@ CONFIG_MLX5_CORE_EN_DCB=y
 # CONFIG_MLX5_EN_TLS is not set
 CONFIG_MLX5_SW_STEERING=y
 # CONFIG_MLX5_SF is not set
+# CONFIG_MLX5_DPLL is not set
 # CONFIG_MLXSW_CORE is not set
 # CONFIG_MLXFW is not set
 CONFIG_MLXBF_GIGE=m
@ -3771,6 +3787,8 @@ CONFIG_MT7921E=m
 CONFIG_MT7921S=m
 CONFIG_MT7921U=m
 # CONFIG_MT7996E is not set
+# CONFIG_MT7925E is not set
+# CONFIG_MT7925U is not set
 CONFIG_WLAN_VENDOR_MICROCHIP=y
 CONFIG_WILC1000=m
 CONFIG_WILC1000_SDIO=m
@ -3883,14 +3901,14 @@ CONFIG_WL18XX=m
 CONFIG_WLCORE=m
 CONFIG_WLCORE_SPI=m
 CONFIG_WLCORE_SDIO=m
-CONFIG_RTL8723DU=m
+# CONFIG_RTL8723DU is not set
 CONFIG_RTL8723DS=m
 # CONFIG_RTL8822BU is not set
 # CONFIG_RTL8821CU is not set
-CONFIG_88XXAU=m
-CONFIG_RTL8192EU=m
-CONFIG_RTL8189FS=m
-CONFIG_RTL8189ES=m
+# CONFIG_88XXAU is not set
+# CONFIG_RTL8192EU is not set
+# CONFIG_RTL8189FS is not set
+# CONFIG_RTL8189ES is not set
 CONFIG_WLAN_VENDOR_ZYDAS=y
 CONFIG_USB_ZD1201=m
 CONFIG_ZD1211RW=m
@ -4369,6 +4387,7 @@ CONFIG_HW_RANDOM_VIRTIO=m
 CONFIG_HW_RANDOM_OPTEE=m
 # CONFIG_HW_RANDOM_CCTRNG is not set
 # CONFIG_HW_RANDOM_XIPHERA is not set
+CONFIG_HW_RANDOM_ROCKCHIP=m
 CONFIG_HW_RANDOM_ARM_SMCCC_TRNG=m
 CONFIG_HW_RANDOM_CN10K=y
 # CONFIG_APPLICOM is not set
@ -4753,7 +4772,6 @@ CONFIG_W1_SLAVE_DS28E17=m
 # end of 1-wire Slaves

 CONFIG_POWER_RESET=y
-CONFIG_POWER_RESET_BRCMSTB=y
 CONFIG_POWER_RESET_GPIO=y
 CONFIG_POWER_RESET_GPIO_RESTART=y
 # CONFIG_POWER_RESET_LTC2952 is not set
@ -4820,6 +4838,7 @@ CONFIG_CHARGER_CROS_PCHG=m
 CONFIG_CHARGER_UCS1002=m
 # CONFIG_CHARGER_BD99954 is not set
 # CONFIG_BATTERY_UG3105 is not set
+# CONFIG_FUEL_GAUGE_MM8013 is not set
 CONFIG_HWMON=y
 CONFIG_HWMON_VID=m
 # CONFIG_HWMON_DEBUG_CHIP is not set
@ -4873,6 +4892,7 @@ CONFIG_SENSORS_IBMPEX=m
 CONFIG_SENSORS_IIO_HWMON=m
 CONFIG_SENSORS_IT87=m
 CONFIG_SENSORS_JC42=m
+# CONFIG_SENSORS_POWERZ is not set
 CONFIG_SENSORS_POWR1220=m
 CONFIG_SENSORS_LINEAGE=m
 CONFIG_SENSORS_LTC2945=m
@ -4880,6 +4900,7 @@ CONFIG_SENSORS_LTC2947=m
 CONFIG_SENSORS_LTC2947_I2C=m
 CONFIG_SENSORS_LTC2947_SPI=m
 CONFIG_SENSORS_LTC2990=m
+# CONFIG_SENSORS_LTC2991 is not set
 CONFIG_SENSORS_LTC2992=m
 CONFIG_SENSORS_LTC4151=m
 CONFIG_SENSORS_LTC4215=m
@ -5304,6 +5325,7 @@ CONFIG_REGULATOR_GPIO=y
 # CONFIG_REGULATOR_LTC3589 is not set
 # CONFIG_REGULATOR_LTC3676 is not set
 # CONFIG_REGULATOR_MAX1586 is not set
+# CONFIG_REGULATOR_MAX77503 is not set
 # CONFIG_REGULATOR_MAX77857 is not set
 # CONFIG_REGULATOR_MAX8649 is not set
 # CONFIG_REGULATOR_MAX8660 is not set
@ -5643,6 +5665,7 @@ CONFIG_MEDIA_PCI_SUPPORT=y
 #
 # Media capture support
 #
+# CONFIG_VIDEO_MGB4 is not set
 CONFIG_VIDEO_SOLO6X10=m
 # CONFIG_VIDEO_TW5864 is not set
 CONFIG_VIDEO_TW68=m
@ -5785,6 +5808,10 @@ CONFIG_VIDEO_CAFE_CCIC=m
 # Microchip Technology, Inc. media platform drivers
 #

+#
+# Nuvoton media platform drivers
+#
+
 #
 # NVidia media platform drivers
 #
@ -5913,6 +5940,7 @@ CONFIG_VIDEO_IMX412=m
 CONFIG_VIDEO_MAX9271_LIB=m
 CONFIG_VIDEO_MT9M001=m
 CONFIG_VIDEO_MT9M111=m
+# CONFIG_VIDEO_MT9M114 is not set
 CONFIG_VIDEO_MT9P031=m
 CONFIG_VIDEO_MT9T112=m
 CONFIG_VIDEO_MT9V011=m
@ -6418,10 +6446,12 @@ CONFIG_DRM_PANEL_FEIYANG_FY07024DI26A30D=m
 CONFIG_DRM_PANEL_ILITEK_IL9322=m
 CONFIG_DRM_PANEL_ILITEK_ILI9341=m
 CONFIG_DRM_PANEL_ILITEK_ILI9881C=m
+# CONFIG_DRM_PANEL_ILITEK_ILI9882T is not set
 CONFIG_DRM_PANEL_INNOLUX_EJ030NA=m
 CONFIG_DRM_PANEL_INNOLUX_P079ZCA=m
 # CONFIG_DRM_PANEL_JADARD_JD9365DA_H3 is not set
 CONFIG_DRM_PANEL_JDI_LT070ME05000=m
+# CONFIG_DRM_PANEL_JDI_LPM102A188A is not set
 # CONFIG_DRM_PANEL_JDI_R63452 is not set
 CONFIG_DRM_PANEL_KHADAS_TS050=m
 CONFIG_DRM_PANEL_KINGDISPLAY_KD097D04=m
@ -6449,6 +6479,7 @@ CONFIG_DRM_PANEL_PANASONIC_VVX10F034N00=m
 CONFIG_DRM_PANEL_RASPBERRYPI_TOUCHSCREEN=m
 CONFIG_DRM_PANEL_RAYDIUM_RM67191=m
 CONFIG_DRM_PANEL_RAYDIUM_RM68200=m
+# CONFIG_DRM_PANEL_RAYDIUM_RM692E5 is not set
 CONFIG_DRM_PANEL_RONBO_RB070D30=m
 CONFIG_DRM_PANEL_SAMSUNG_ATNA33XC20=m
 CONFIG_DRM_PANEL_SAMSUNG_DB7430=m
@ -6634,6 +6665,7 @@ CONFIG_FB_SYS_IMAGEBLIT=y
 CONFIG_FB_SYS_FOPS=y
 CONFIG_FB_DEFERRED_IO=y
 CONFIG_FB_DMAMEM_HELPERS=y
+CONFIG_FB_IOMEM_FOPS=y
 CONFIG_FB_IOMEM_HELPERS=y
 CONFIG_FB_SYSMEM_HELPERS=y
 CONFIG_FB_SYSMEM_HELPERS_DEFERRED=y
@ -6832,6 +6864,7 @@ CONFIG_SND_HDA_RECONFIG=y
 CONFIG_SND_HDA_INPUT_BEEP=y
 CONFIG_SND_HDA_INPUT_BEEP_MODE=1
 CONFIG_SND_HDA_PATCH_LOADER=y
+# CONFIG_SND_HDA_CIRRUS_SCODEC_KUNIT_TEST is not set
 CONFIG_SND_HDA_SCODEC_CS35L41=m
 CONFIG_SND_HDA_CS_DSP_CONTROLS=m
 CONFIG_SND_HDA_SCODEC_CS35L41_I2C=m
@ -6993,6 +7026,8 @@ CONFIG_SND_SOC_ALC5623=m
 CONFIG_SND_SOC_AW8738=m
 # CONFIG_SND_SOC_AW88395 is not set
 # CONFIG_SND_SOC_AW88261 is not set
+# CONFIG_SND_SOC_AW87390 is not set
+# CONFIG_SND_SOC_AW88399 is not set
 CONFIG_SND_SOC_BD28623=m
 CONFIG_SND_SOC_BT_SCO=m
 # CONFIG_SND_SOC_CHV3_CODEC is not set
@ -7116,6 +7151,7 @@ CONFIG_SND_SOC_RT715=m
 CONFIG_SND_SOC_RT715_SDW=m
 CONFIG_SND_SOC_RT715_SDCA_SDW=m
 # CONFIG_SND_SOC_RT9120 is not set
+# CONFIG_SND_SOC_RTQ9128 is not set
 CONFIG_SND_SOC_SDW_MOCKUP=m
 CONFIG_SND_SOC_SGTL5000=m
 CONFIG_SND_SOC_SIGMADSP=m
@ -7401,6 +7437,7 @@ CONFIG_USB_CONN_GPIO=y
 CONFIG_USB_ARCH_HAS_HCD=y
 CONFIG_USB=y
 CONFIG_USB_PCI=y
+# CONFIG_USB_PCI_AMD is not set
 CONFIG_USB_ANNOUNCE_NEW_DEVICES=y

 #
@ -7546,6 +7583,7 @@ CONFIG_USB_CHIPIDEA_UDC=y
 CONFIG_USB_CHIPIDEA_HOST=y
 CONFIG_USB_CHIPIDEA_PCI=y
 CONFIG_USB_CHIPIDEA_MSM=y
+CONFIG_USB_CHIPIDEA_NPCM=y
 CONFIG_USB_CHIPIDEA_IMX=y
 CONFIG_USB_CHIPIDEA_GENERIC=y
 CONFIG_USB_CHIPIDEA_TEGRA=y
@ -7629,6 +7667,7 @@ CONFIG_USB_CYTHERM=m
 CONFIG_USB_IDMOUSE=m
 CONFIG_USB_APPLEDISPLAY=m
 CONFIG_APPLE_MFI_FASTCHARGE=m
+# CONFIG_USB_LJCA is not set
 CONFIG_USB_SISUSBVGA=m
 CONFIG_USB_LD=m
 CONFIG_USB_TRANCEVIBRATOR=m
@ -7798,6 +7837,7 @@ CONFIG_TYPEC_MUX_FSA4480=m
 # CONFIG_TYPEC_MUX_GPIO_SBU is not set
 CONFIG_TYPEC_MUX_PI3USB30532=m
 # CONFIG_TYPEC_MUX_NB7VPQ904M is not set
+# CONFIG_TYPEC_MUX_PTN36502 is not set
 # end of USB Type-C Multiplexer/DeMultiplexer Switch support

 #
@ -7951,6 +7991,7 @@ CONFIG_LEDS_TRIGGER_HEARTBEAT=y
 CONFIG_LEDS_TRIGGER_BACKLIGHT=m
 CONFIG_LEDS_TRIGGER_CPU=y
 CONFIG_LEDS_TRIGGER_ACTIVITY=y
+# CONFIG_LEDS_TRIGGER_GPIO is not set
 CONFIG_LEDS_TRIGGER_DEFAULT_ON=y

 #
@ -8260,7 +8301,6 @@ CONFIG_XEN_FRONT_PGDIR_SHBUF=m
 # CONFIG_COMEDI is not set
 CONFIG_STAGING=y
 # CONFIG_PRISM2_USB is not set
-CONFIG_RTL8192U=m
 CONFIG_RTLLIB=m
 CONFIG_RTLLIB_CRYPTO_CCMP=m
 CONFIG_RTLLIB_CRYPTO_TKIP=m
@ -8307,12 +8347,6 @@ CONFIG_AD9834=m
 #
 # CONFIG_AD5933 is not set
 # end of Network Analyzer, Impedance Converters
-
-#
-# Resolver to digital converters
-#
-# CONFIG_AD2S1210 is not set
-# end of Resolver to digital converters
 # end of IIO staging drivers

 CONFIG_FB_SM750=m
@ -8371,7 +8405,6 @@ CONFIG_FIELDBUS_DEV=m
 CONFIG_HMS_ANYBUSS_BUS=m
 # CONFIG_ARCX_ANYBUS_CONTROLLER is not set
 # CONFIG_HMS_PROFINET is not set
-# CONFIG_QLGE is not set
 # CONFIG_VME_BUS is not set
 # CONFIG_RTL8723CS is not set
 # CONFIG_GOLDFISH is not set
@ -8396,7 +8429,7 @@ CONFIG_CROS_EC_TYPEC=m
 CONFIG_CROS_USBPD_NOTIFY=y
 # CONFIG_CHROMEOS_PRIVACY_SCREEN is not set
 CONFIG_CROS_TYPEC_SWITCH=m
-# CONFIG_CROS_KUNIT is not set
+# CONFIG_CROS_KUNIT_EC_PROTO_TEST is not set
 # CONFIG_MELLANOX_PLATFORM is not set
 CONFIG_SURFACE_PLATFORMS=y
 # CONFIG_SURFACE_3_POWER_OPREGION is not set
@ -8450,6 +8483,7 @@ CONFIG_CLK_RK3588=y
 # CONFIG_COMMON_CLK_XLNX_CLKWZRD is not set
 # CONFIG_CLK_KUNIT_TEST is not set
 # CONFIG_CLK_GATE_KUNIT_TEST is not set
+# CONFIG_CLK_FD_KUNIT_TEST is not set
 # CONFIG_HWSPINLOCK is not set

 #
@ -8479,6 +8513,7 @@ CONFIG_PCC=y
 # CONFIG_MAILBOX_TEST is not set
 CONFIG_IOMMU_IOVA=y
 CONFIG_IOMMU_API=y
+CONFIG_IOMMUFD_DRIVER=y
 CONFIG_IOMMU_SUPPORT=y

 #
@ -8548,7 +8583,6 @@ CONFIG_SOUNDWIRE_QCOM=m
 #
 # Broadcom SoC drivers
 #
-CONFIG_SOC_BRCMSTB=y
 # end of Broadcom SoC drivers

 #
@ -8587,7 +8621,6 @@ CONFIG_QCOM_QMI_HELPERS=m

 CONFIG_ROCKCHIP_GRF=y
 CONFIG_ROCKCHIP_IODOMAIN=y
-CONFIG_ROCKCHIP_PM_DOMAINS=y
 CONFIG_SOC_TI=y

 #
@ -8596,6 +8629,33 @@ CONFIG_SOC_TI=y
 # end of Xilinx SoC drivers
 # end of SOC (System On Chip) specific Drivers

+#
+# PM Domains
+#
+
+#
+# Amlogic PM Domains
+#
+# end of Amlogic PM Domains
+
+#
+# Broadcom PM Domains
+#
+# end of Broadcom PM Domains
+
+#
+# i.MX PM Domains
+#
+# end of i.MX PM Domains
+
+#
+# Qualcomm PM Domains
+#
+# end of Qualcomm PM Domains
+
+CONFIG_ROCKCHIP_PM_DOMAINS=y
+# end of PM Domains
+
 CONFIG_PM_DEVFREQ=y

 #
@ -8744,6 +8804,7 @@ CONFIG_AD799X=m
 # CONFIG_HI8435 is not set
 # CONFIG_HX711 is not set
 # CONFIG_INA2XX_ADC is not set
+# CONFIG_LTC2309 is not set
 # CONFIG_LTC2471 is not set
 # CONFIG_LTC2485 is not set
 CONFIG_LTC2496=m
@ -8758,6 +8819,7 @@ CONFIG_MAX1363=m
 CONFIG_MAX9611=m
 CONFIG_MCP320X=m
 CONFIG_MCP3422=m
+# CONFIG_MCP3564 is not set
 CONFIG_MCP3911=m
 # CONFIG_MEDIATEK_MT6370_ADC is not set
 # CONFIG_NAU7802 is not set
@ -9176,6 +9238,7 @@ CONFIG_MCP41010=m
 # Pressure sensors
 #
 # CONFIG_ABP060MG is not set
+# CONFIG_ROHM_BM1390 is not set
 CONFIG_BMP280=m
 CONFIG_BMP280_I2C=m
 CONFIG_BMP280_SPI=m
@ -9228,6 +9291,7 @@ CONFIG_VL53L0X_I2C=m
 #
 # CONFIG_AD2S90 is not set
 # CONFIG_AD2S1200 is not set
+# CONFIG_AD2S1210 is not set
 # end of Resolver to digital converters

 #
@ -9255,6 +9319,7 @@ CONFIG_PWM_SYSFS=y
 CONFIG_PWM_ATMEL_TCB=m
 CONFIG_PWM_CLK=m
 CONFIG_PWM_CROS_EC=m
+CONFIG_PWM_DWC_CORE=m
 CONFIG_PWM_DWC=m
 # CONFIG_PWM_FSL_FTM is not set
 CONFIG_PWM_NTXEC=m
@ -9320,6 +9385,7 @@ CONFIG_PHY_ROCKCHIP_INNO_CSIDPHY=m
 CONFIG_PHY_ROCKCHIP_INNO_DSIDPHY=y
 CONFIG_PHY_ROCKCHIP_NANENG_COMBO_PHY=y
 CONFIG_PHY_ROCKCHIP_PCIE=y
+CONFIG_PHY_ROCKCHIP_SAMSUNG_HDPTX_HDMI=m
 CONFIG_PHY_ROCKCHIP_SNPS_PCIE3=m
 CONFIG_PHY_ROCKCHIP_TYPEC=y
 CONFIG_PHY_ROCKCHIP_USB=y
@ -9436,6 +9502,7 @@ CONFIG_MOST_SND=m
 # CONFIG_PECI is not set
 # CONFIG_HTE is not set
 # CONFIG_CDX_BUS is not set
+CONFIG_DPLL=y
 # end of Device Drivers

 #
@ -9491,7 +9558,6 @@ CONFIG_OCFS2_DEBUG_MASKLOG=y
 # CONFIG_OCFS2_DEBUG_FS is not set
 CONFIG_BTRFS_FS=y
 CONFIG_BTRFS_FS_POSIX_ACL=y
-# CONFIG_BTRFS_FS_CHECK_INTEGRITY is not set
 # CONFIG_BTRFS_FS_RUN_SANITY_TESTS is not set
 # CONFIG_BTRFS_DEBUG is not set
 # CONFIG_BTRFS_ASSERT is not set
@ -9512,6 +9578,7 @@ CONFIG_F2FS_FS_LZ4HC=y
 CONFIG_F2FS_FS_ZSTD=y
 CONFIG_F2FS_IOSTAT=y
 # CONFIG_F2FS_UNFAIR_RWSEM is not set
+# CONFIG_BCACHEFS_FS is not set
 CONFIG_ZONEFS_FS=m
 CONFIG_FS_POSIX_ACL=y
 CONFIG_EXPORTFS=y
@ -10132,7 +10199,9 @@ CONFIG_CRYPTO_DRBG_HMAC=y
 # CONFIG_CRYPTO_DRBG_CTR is not set
 CONFIG_CRYPTO_DRBG=y
 CONFIG_CRYPTO_JITTERENTROPY=y
-# CONFIG_CRYPTO_JITTERENTROPY_TESTINTERFACE is not set
+CONFIG_CRYPTO_JITTERENTROPY_MEMORY_BLOCKS=64
+CONFIG_CRYPTO_JITTERENTROPY_MEMORY_BLOCKSIZE=32
+CONFIG_CRYPTO_JITTERENTROPY_OSR=1
 CONFIG_CRYPTO_KDF800108_CTR=y
 # end of Random number generation

@ -10198,6 +10267,8 @@ CONFIG_CRYPTO_DEV_NITROX_CNN55XX=m
 CONFIG_CRYPTO_DEV_CAVIUM_ZIP=m
 CONFIG_CRYPTO_DEV_ROCKCHIP=m
 # CONFIG_CRYPTO_DEV_ROCKCHIP_DEBUG is not set
+CONFIG_CRYPTO_DEV_ROCKCHIP2=m
+# CONFIG_CRYPTO_DEV_ROCKCHIP2_DEBUG is not set
 CONFIG_CRYPTO_DEV_VIRTIO=m
 CONFIG_CRYPTO_DEV_SAFEXCEL=m
 CONFIG_CRYPTO_DEV_CCREE=m
@ -10225,6 +10296,7 @@ CONFIG_SYSTEM_TRUSTED_KEYS=""
 CONFIG_SYSTEM_EXTRA_CERTIFICATE=y
 CONFIG_SYSTEM_EXTRA_CERTIFICATE_SIZE=4096
 CONFIG_SECONDARY_TRUSTED_KEYRING=y
+# CONFIG_SECONDARY_TRUSTED_KEYRING_SIGNED_BY_BUILTIN is not set
 CONFIG_SYSTEM_BLACKLIST_KEYRING=y
 CONFIG_SYSTEM_BLACKLIST_HASH_LIST=""
 # CONFIG_SYSTEM_REVOCATION_LIST is not set
@ -10314,7 +10386,6 @@ CONFIG_ZSTD_DECOMPRESS=y
 CONFIG_XZ_DEC=y
 CONFIG_XZ_DEC_X86=y
 CONFIG_XZ_DEC_POWERPC=y
-CONFIG_XZ_DEC_IA64=y
 CONFIG_XZ_DEC_ARM=y
 CONFIG_XZ_DEC_ARMTHUMB=y
 CONFIG_XZ_DEC_SPARC=y
@ -10342,6 +10413,7 @@ CONFIG_BTREE=y
 CONFIG_INTERVAL_TREE=y
 CONFIG_XARRAY_MULTI=y
 CONFIG_ASSOCIATIVE_ARRAY=y
+CONFIG_CLOSURES=y
 CONFIG_HAS_IOMEM=y
 CONFIG_HAS_IOPORT=y
 CONFIG_HAS_IOPORT_MAP=y
@ -10419,12 +10491,14 @@ CONFIG_MEMREGION=y
 CONFIG_ARCH_STACKWALK=y
 CONFIG_STACKDEPOT=y
 CONFIG_SBITMAP=y
+# CONFIG_LWQ_TEST is not set
 # end of Library routines

 CONFIG_GENERIC_IOREMAP=y
 CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y
 CONFIG_ASN1_ENCODER=y
 CONFIG_POLYNOMIAL=m
+CONFIG_FIRMWARE_TABLE=y

 #
 # Kernel hacking
@ -10600,6 +10674,7 @@ CONFIG_STACKTRACE=y
 # CONFIG_DEBUG_PLIST is not set
 # CONFIG_DEBUG_SG is not set
 # CONFIG_DEBUG_NOTIFIERS is not set
+# CONFIG_DEBUG_CLOSURES is not set
 # CONFIG_DEBUG_MAPLE_TREE is not set
 # end of Debug kernel data structures

@ -10767,6 +10842,7 @@ CONFIG_MEMCPY_SLOW_KUNIT_TEST=y
 CONFIG_TEST_MEMCAT_P=m
 # CONFIG_TEST_MEMINIT is not set
 # CONFIG_TEST_FREE_PAGES is not set
+# CONFIG_TEST_OBJPOOL is not set
 CONFIG_ARCH_USE_MEMTEST=y
 CONFIG_MEMTEST=y
 # end of Kernel Testing and Coverage
--- a/config/sources/families/rockchip-rk3588.conf
+++ b/config/sources/families/rockchip-rk3588.conf
@ -34,8 +34,8 @@ case $BRANCH in
 		SKIP_BOOTSPLASH="yes"
 		LINUXFAMILY=rockchip-rk3588
 		LINUXCONFIG='linux-rockchip-rk3588-'$BRANCH
-		KERNEL_MAJOR_MINOR="6.6" # Major and minor versions of this kernel.
-		KERNELBRANCH='branch:linux-6.6.y'
+		KERNEL_MAJOR_MINOR="6.7" # Major and minor versions of this kernel.
+		KERNELBRANCH='tag:v6.7-rc1'
 		KERNELPATCHDIR='rockchip-rk3588-edge'
 		;;

--- a/patch/kernel/rockchip-rk3588-edge/0010-fix-clk-divisions.patch
+++ b/patch/kernel/rockchip-rk3588-edge/0010-fix-clk-divisions.patch
@ -1,28 +1,74 @@
-From 0c7ec3f97f2dd703029b8a3250d04338623aea1a Mon Sep 17 00:00:00 2001
+From fab08a275f328e2e0a6fef73226e45eb1d4bb108 Mon Sep 17 00:00:00 2001
 From: Sebastian Reichel <sebastian.reichel@collabora.com>
-Date: Thu, 18 May 2023 05:19:48 +0200
-Subject: [PATCH] clk: divider: Fix divisions
+Date: Tue, 24 Oct 2023 16:09:35 +0200
+Subject: [PATCH 1/3] math.h: add DIV_ROUND_UP_NO_OVERFLOW
+
+Add a new DIV_ROUND_UP helper, which cannot overflow when
+big numbers are being used.
+
+Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
+---
+ include/linux/math.h | 11 +++++++++++
+ 1 file changed, 11 insertions(+)
+
+diff --git a/include/linux/math.h b/include/linux/math.h
+index dd4152711de7..f80bfb375ab9 100644
+--- a/include/linux/math.h
+++ b/include/linux/math.h
+@@ -36,6 +36,17 @@
+ 
+ #define DIV_ROUND_UP __KERNEL_DIV_ROUND_UP
+ 
+/**
+ * DIV_ROUND_UP_NO_OVERFLOW - divide two numbers and always round up
+ * @n: numerator / dividend
+ * @d: denominator / divisor
+ *
+ * This functions does the same as DIV_ROUND_UP, but internally uses a
+ * division and a modulo operation instead of math tricks. This way it
+ * avoids overflowing when handling big numbers.
+ */
+#define DIV_ROUND_UP_NO_OVERFLOW(n, d) (((n) / (d)) + !!((n) % (d)))
+
+ #define DIV_ROUND_DOWN_ULL(ll, d) \
+ 	({ unsigned long long _tmp = (ll); do_div(_tmp, d); _tmp; })
+ 
+-- 
+2.42.1
+
+
+From 967c218122840e468981031fd8888846727f5282 Mon Sep 17 00:00:00 2001
+From: Sebastian Reichel <sebastian.reichel@collabora.com>
+Date: Tue, 24 Oct 2023 16:13:50 +0200
+Subject: [PATCH 2/3] clk: divider: Fix divisor masking on 64 bit platforms

 The clock framework handles clock rates as "unsigned long", so u32 on
 32-bit architectures and u64 on 64-bit architectures.

-The current code pointlessly casts the dividend to u64 on 32-bit
-architectures and thus pointlessly reducing the performance.
+The current code casts the dividend to u64 on 32-bit to avoid a
+potential overflow. For example DIV_ROUND_UP(3000000000, 1500000000)
+= (3.0G + 1.5G - 1) / 1.5G = = OVERFLOW / 1.5G, which has been
+introduced in commit 9556f9dad8f5 ("clk: divider: handle integer overflow
+when dividing large clock rates").

-On the other hand on 64-bit architectures the divisor is masked and only
-the lower 32-bit are used. Thus requesting a frequency >= 4.3GHz results
+On 64 bit platforms this masks the divisor, so that only the lower
+32 bit are used. Thus requesting a frequency >= 4.3GHz results
 in incorrect values. For example requesting 4300000000 (4.3 GHz) will
 effectively request ca. 5 MHz. Requesting clk_round_rate(clk, ULONG_MAX)
 is a bit of a special case, since that still returns correct values as
 long as the parent clock is below 8.5 GHz.

+Fix this by switching to DIV_ROUND_UP_NO_OVERFLOW, which cannot
+overflow. This avoids any requirements on the arguments (except
+that divisor should not be 0 obviously).
+
 Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
 ---
 drivers/clk/clk-divider.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

 diff --git a/drivers/clk/clk-divider.c b/drivers/clk/clk-divider.c
-index a2c2b5203b0a9..c38e8aa60e547 100644
+index a2c2b5203b0a..94b4fb66a60f 100644
 --- a/drivers/clk/clk-divider.c
 +++ b/drivers/clk/clk-divider.c
@@ -220,7 +220,7 @@ static int _div_round_up(const struct clk_div_table *table,
@ -30,7 +76,7 @@ index a2c2b5203b0a9..c38e8aa60e547 100644
 			 unsigned long flags)
 {
 -	int div = DIV_ROUND_UP_ULL((u64)parent_rate, rate);
-+	int div = DIV_ROUND_UP(parent_rate, rate);
+	int div = DIV_ROUND_UP_NO_OVERFLOW(parent_rate, rate);
 
 	if (flags & CLK_DIVIDER_POWER_OF_TWO)
 		div = __roundup_pow_of_two(div);
@ -39,7 +85,7 @@ index a2c2b5203b0a9..c38e8aa60e547 100644
 	unsigned long up_rate, down_rate;
 
 -	up = DIV_ROUND_UP_ULL((u64)parent_rate, rate);
-+	up = DIV_ROUND_UP(parent_rate, rate);
+	up = DIV_ROUND_UP_NO_OVERFLOW(parent_rate, rate);
 	down = parent_rate / rate;
 
 	if (flags & CLK_DIVIDER_POWER_OF_TWO) {
@ -48,10 +94,51 @@ index a2c2b5203b0a9..c38e8aa60e547 100644
 	unsigned int div, value;
 
 -	div = DIV_ROUND_UP_ULL((u64)parent_rate, rate);
-+	div = DIV_ROUND_UP(parent_rate, rate);
+	div = DIV_ROUND_UP_NO_OVERFLOW(parent_rate, rate);
 
 	if (!_is_valid_div(table, div, flags))
 		return -EINVAL;
 -- 
-GitLab
+2.42.1
+
+
+From 5747896098cee178de4bed1eb0052893690eb40e Mon Sep 17 00:00:00 2001
+From: Sebastian Reichel <sebastian.reichel@collabora.com>
+Date: Tue, 24 Oct 2023 18:09:57 +0200
+Subject: [PATCH 3/3] clk: composite: replace open-coded abs_diff()
+
+Replace the open coded abs_diff() with the existing helper function.
+
+Suggested-by: Andy Shevchenko <andriy.shevchenko@intel.com>
+Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
+---
+ drivers/clk/clk-composite.c | 6 ++----
+ 1 file changed, 2 insertions(+), 4 deletions(-)
+
+diff --git a/drivers/clk/clk-composite.c b/drivers/clk/clk-composite.c
+index 66759fe28fad..478a4e594336 100644
+--- a/drivers/clk/clk-composite.c
+++ b/drivers/clk/clk-composite.c
+@@ -6,6 +6,7 @@
+ #include <linux/clk-provider.h>
+ #include <linux/device.h>
+ #include <linux/err.h>
+#include <linux/math.h>
+ #include <linux/slab.h>
+ 
+ static u8 clk_composite_get_parent(struct clk_hw *hw)
+@@ -119,10 +120,7 @@ static int clk_composite_determine_rate(struct clk_hw *hw,
+ 			if (ret)
+ 				continue;
+ 
+-			if (req->rate >= tmp_req.rate)
+-				rate_diff = req->rate - tmp_req.rate;
+-			else
+-				rate_diff = tmp_req.rate - req->rate;
+			rate_diff = abs_diff(req->rate, tmp_req.rate);
+ 
+ 			if (!rate_diff || !req->best_parent_hw
+ 				       || best_rate_diff > rate_diff) {
+-- 
+2.42.1

--- a/patch/kernel/rockchip-rk3588-edge/0020-USB3-Host-Support-For-Rock5.patch
+++ b/patch/kernel/rockchip-rk3588-edge/0020-USB3-Host-Support-For-Rock5.patch
@ -0,0 +1,85 @@
+From a2439d839c103c029294042b5b3d4a065e5073d0 Mon Sep 17 00:00:00 2001
+From: Sebastian Reichel <sebastian.reichel@collabora.com>
+Date: Wed, 19 Jul 2023 15:56:42 +0200
+Subject: [PATCH 1/2] arm64: dts: rockchip: add USB3 host to rock-5b
+
+Enable USB3 host controller for the Radxa ROCK 5 Model B. This adds
+USB3 for the upper USB3 port (the one further away from the PCB).
+
+The lower USB3 and the USB-C ports use the RK3588 USB TypeC host
+controller, which use a different PHY without upstream support.
+
+Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
+---
+ arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts | 8 ++++++++
+ 1 file changed, 8 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts
+index 741f631db345..61b937beca7f 100644
+--- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts
+@@ -138,6 +138,10 @@ &combphy1_ps {
+ 	status = "okay";
+ };
+ 
+&combphy2_psu {
+	status = "okay";
+};
+
+ &cpu_b0 {
+ 	cpu-supply = <&vdd_cpu_big0_s0>;
+ };
+@@ -765,3 +769,7 @@ &usb_host1_ehci {
+ &usb_host1_ohci {
+ 	status = "okay";
+ };
+
+&usb_host2_xhci {
+	status = "okay";
+};
+-- 
+2.42.1
+
+
+From 292226fcc7af3e6d5e3b1587459146042fb8a2cf Mon Sep 17 00:00:00 2001
+From: Sebastian Reichel <sebastian.reichel@collabora.com>
+Date: Fri, 21 Jul 2023 15:19:37 +0200
+Subject: [PATCH 2/2] arm64: dts: rockchip: add USB3 host to rock-5a
+
+Enable USB3 host controller for the Radxa ROCK 5 Model A. This adds
+USB3 for the lower USB3 port (the one closer to the PCB).
+
+The upper USB3 port uses the RK3588 USB TypeC host controller, which
+use a different PHY without upstream support.
+
+Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
+---
+ arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts | 8 ++++++++
+ 1 file changed, 8 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts b/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts
+index 8347adcbd003..6fb03294576c 100644
+--- a/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts
+@@ -114,6 +114,10 @@ vcc_1v1_nldo_s3: vcc-1v1-nldo-s3-regulator {
+ 	};
+ };
+ 
+&combphy2_psu {
+	status = "okay";
+};
+
+ &cpu_b0 {
+ 	cpu-supply = <&vdd_cpu_big0_s0>;
+ };
+@@ -734,3 +738,7 @@ &usb_host1_ehci {
+ &usb_host1_ohci {
+ 	status = "okay";
+ };
+
+&usb_host2_xhci {
+	status = "okay";
+};
+-- 
+2.42.1
+
--- a/patch/kernel/rockchip-rk3588-edge/0021-RK3588-Add-USB3-DRD-Support.patch
+++ b/patch/kernel/rockchip-rk3588-edge/0021-RK3588-Add-USB3-DRD-Support.patch
--- a/patch/kernel/rockchip-rk3588-edge/0022-RK3588-Add-Cpufreq-Support.patch
+++ b/patch/kernel/rockchip-rk3588-edge/0022-RK3588-Add-Cpufreq-Support.patch
@ -1,7 +1,7 @@
-From f9c3292a2a99acf817f97a2b312a98e42a5eaa2e Mon Sep 17 00:00:00 2001
+From 8baebef8be9691a28f8efa284dfce9a5b9395130 Mon Sep 17 00:00:00 2001
 From: Sebastian Reichel <sebastian.reichel@collabora.com>
 Date: Thu, 18 Aug 2022 14:21:30 +0200
-Subject: [PATCH 1/2] cpufreq: rockchip: Introduce driver for rk3588
+Subject: [PATCH 1/5] cpufreq: rockchip: Introduce driver for rk3588

 This is a heavily modified port from the downstream driver.
 Downstream used it for multiple rockchip generations, while
@ -23,7 +23,7 @@ Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
 create mode 100644 drivers/cpufreq/rockchip-cpufreq.c

 diff --git a/drivers/cpufreq/Kconfig.arm b/drivers/cpufreq/Kconfig.arm
-index 123b4bbfcfee..6fdc2f0430bb 100644
+index f911606897b8..1e255210851e 100644
 --- a/drivers/cpufreq/Kconfig.arm
 +++ b/drivers/cpufreq/Kconfig.arm
@@ -189,6 +189,16 @@ config ARM_RASPBERRYPI_CPUFREQ
@ -44,7 +44,7 @@ index 123b4bbfcfee..6fdc2f0430bb 100644
 	bool "Samsung S3C64XX"
 	depends on CPU_S3C6410
 diff --git a/drivers/cpufreq/Makefile b/drivers/cpufreq/Makefile
-index ef8510774913..c3f8c9cd563f 100644
+index 8d141c71b016..14fb48863f0b 100644
 --- a/drivers/cpufreq/Makefile
 +++ b/drivers/cpufreq/Makefile
@@ -71,6 +71,7 @@ obj-$(CONFIG_PXA3xx)			+= pxa3xx-cpufreq.o
@ -56,12 +56,12 @@ index ef8510774913..c3f8c9cd563f 100644
 obj-$(CONFIG_ARM_S5PV210_CPUFREQ)	+= s5pv210-cpufreq.o
 obj-$(CONFIG_ARM_SA1110_CPUFREQ)	+= sa1110-cpufreq.o
 diff --git a/drivers/cpufreq/cpufreq-dt-platdev.c b/drivers/cpufreq/cpufreq-dt-platdev.c
-index e2b20080de3a..7bc19a59be26 100644
+index bd1e1357cef8..cfd35aa52043 100644
 --- a/drivers/cpufreq/cpufreq-dt-platdev.c
 +++ b/drivers/cpufreq/cpufreq-dt-platdev.c
-@@ -159,6 +159,8 @@ static const struct of_device_id blocklist[] __initconst = {
- 	{ .compatible = "qcom,sm8250", },
- 	{ .compatible = "qcom,sm8350", },
+@@ -168,6 +168,8 @@ static const struct of_device_id blocklist[] __initconst = {
+ 	{ .compatible = "qcom,sm8450", },
+ 	{ .compatible = "qcom,sm8550", },
 
 +	{ .compatible = "rockchip,rk3588", },
 +
@ -720,13 +720,13 @@ index 000000000000..0bf57ac85e60
 +MODULE_DESCRIPTION("Rockchip cpufreq driver");
 +MODULE_LICENSE("GPL v2");
 -- 
-2.41.0
+2.42.1


-From 1a4f292fcdb4b4a625dda97e8236911b896c8abe Mon Sep 17 00:00:00 2001
+From f542d93ac2d5c4b6458599494f90bd4021d34b2c Mon Sep 17 00:00:00 2001
 From: Sebastian Reichel <sebastian.reichel@collabora.com>
 Date: Tue, 4 Apr 2023 17:30:46 +0200
-Subject: [PATCH 2/2] arm64: dts: rockchip: rk3588: add cpu frequency scaling
+Subject: [PATCH 2/5] arm64: dts: rockchip: rk3588: add cpu frequency scaling
 support

 Add required bits for CPU frequency scaling to the Rockchip 3588
@ -741,7 +741,7 @@ Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
 1 file changed, 452 insertions(+)

 diff --git a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
-index a90ec13f50b4..aa78f535b27d 100644
+index be694aaef7d0..e7ebeda1c799 100644
 --- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
 +++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
@@ -10,6 +10,7 @@
@ -1263,7 +1263,7 @@ index a90ec13f50b4..aa78f535b27d 100644
 	timer {
 		compatible = "arm,armv8-timer";
 		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH 0>,
-@@ -491,6 +933,16 @@ sys_grf: syscon@fd58c000 {
+@@ -496,6 +938,16 @@ sys_grf: syscon@fd58c000 {
 		reg = <0x0 0xfd58c000 0x0 0x1000>;
 	};
 
@ -1281,5 +1281,198 @@ index a90ec13f50b4..aa78f535b27d 100644
 		compatible = "rockchip,rk3588-php-grf", "syscon";
 		reg = <0x0 0xfd5b0000 0x0 0x1000>;
 -- 
-2.41.0
+2.42.1
+
+
+From e84f55d8a9d849eac51f73c47cdb90eb7dbac90f Mon Sep 17 00:00:00 2001
+From: Sebastian Reichel <sebastian.reichel@collabora.com>
+Date: Thu, 25 May 2023 19:48:49 +0200
+Subject: [PATCH 3/5] arm64: dts: rockchip: rk3588-evb1: add cpu mem regulator
+ info
+
+Add the second supply regulator for the CPU cores, which is used
+for supplying the memory interface.
+
+Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
+---
+ arch/arm64/boot/dts/rockchip/rk3588-evb1-v10.dts | 8 ++++++++
+ 1 file changed, 8 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/rockchip/rk3588-evb1-v10.dts b/arch/arm64/boot/dts/rockchip/rk3588-evb1-v10.dts
+index ee45b8a801ad..cbee9e4b86da 100644
+--- a/arch/arm64/boot/dts/rockchip/rk3588-evb1-v10.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3588-evb1-v10.dts
+@@ -249,34 +249,42 @@ &combphy2_psu {
+ 
+ &cpu_b0 {
+ 	cpu-supply = <&vdd_cpu_big0_s0>;
+	mem-supply = <&vdd_cpu_big0_mem_s0>;
+ };
+ 
+ &cpu_b1 {
+ 	cpu-supply = <&vdd_cpu_big0_s0>;
+	mem-supply = <&vdd_cpu_big0_mem_s0>;
+ };
+ 
+ &cpu_b2 {
+ 	cpu-supply = <&vdd_cpu_big1_s0>;
+	mem-supply = <&vdd_cpu_big1_mem_s0>;
+ };
+ 
+ &cpu_b3 {
+ 	cpu-supply = <&vdd_cpu_big1_s0>;
+	mem-supply = <&vdd_cpu_big1_mem_s0>;
+ };
+ 
+ &cpu_l0 {
+ 	cpu-supply = <&vdd_cpu_lit_s0>;
+	mem-supply = <&vdd_cpu_lit_mem_s0>;
+ };
+ 
+ &cpu_l1 {
+ 	cpu-supply = <&vdd_cpu_lit_s0>;
+	mem-supply = <&vdd_cpu_lit_mem_s0>;
+ };
+ 
+ &cpu_l2 {
+ 	cpu-supply = <&vdd_cpu_lit_s0>;
+	mem-supply = <&vdd_cpu_lit_mem_s0>;
+ };
+ 
+ &cpu_l3 {
+ 	cpu-supply = <&vdd_cpu_lit_s0>;
+	mem-supply = <&vdd_cpu_lit_mem_s0>;
+ };
+ 
+ &gmac0 {
+-- 
+2.42.1
+
+
+From 643d555335b4c0dc228111a74cfa5189e17616df Mon Sep 17 00:00:00 2001
+From: Sebastian Reichel <sebastian.reichel@collabora.com>
+Date: Mon, 24 Jul 2023 15:18:39 +0200
+Subject: [PATCH 4/5] arm64: dts: rockchip: rock5a: add cpu mem regulator info
+
+Add the second supply regulator for the CPU cores, which is used
+for supplying the memory interface.
+
+Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
+---
+ arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts | 8 ++++++++
+ 1 file changed, 8 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts b/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts
+index a6ec5e770e71..58c58ec03a7f 100644
+--- a/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts
+@@ -120,34 +120,42 @@ &combphy2_psu {
+ 
+ &cpu_b0 {
+ 	cpu-supply = <&vdd_cpu_big0_s0>;
+	mem-supply = <&vdd_cpu_big0_s0>;
+ };
+ 
+ &cpu_b1 {
+ 	cpu-supply = <&vdd_cpu_big0_s0>;
+	mem-supply = <&vdd_cpu_big0_s0>;
+ };
+ 
+ &cpu_b2 {
+ 	cpu-supply = <&vdd_cpu_big1_s0>;
+	mem-supply = <&vdd_cpu_big1_s0>;
+ };
+ 
+ &cpu_b3 {
+ 	cpu-supply = <&vdd_cpu_big1_s0>;
+	mem-supply = <&vdd_cpu_big1_s0>;
+ };
+ 
+ &cpu_l0 {
+ 	cpu-supply = <&vdd_cpu_lit_s0>;
+	mem-supply = <&vdd_cpu_lit_mem_s0>;
+ };
+ 
+ &cpu_l1 {
+ 	cpu-supply = <&vdd_cpu_lit_s0>;
+	mem-supply = <&vdd_cpu_lit_mem_s0>;
+ };
+ 
+ &cpu_l2 {
+ 	cpu-supply = <&vdd_cpu_lit_s0>;
+	mem-supply = <&vdd_cpu_lit_mem_s0>;
+ };
+ 
+ &cpu_l3 {
+ 	cpu-supply = <&vdd_cpu_lit_s0>;
+	mem-supply = <&vdd_cpu_lit_mem_s0>;
+ };
+ 
+ &i2c0 {
+-- 
+2.42.1
+
+
+From c8bd3a53671c48ccf642bbc6453fdb0274022bad Mon Sep 17 00:00:00 2001
+From: Sebastian Reichel <sebastian.reichel@collabora.com>
+Date: Mon, 24 Jul 2023 15:07:49 +0200
+Subject: [PATCH 5/5] arm64: dts: rockchip: rock5b: add cpu mem regulator info
+
+Add the second supply regulator for the CPU cores, which is used
+for supplying the memory interface.
+
+Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
+---
+ arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts | 8 ++++++++
+ 1 file changed, 8 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts
+index 419d0202f7fc..9ee415e6f498 100644
+--- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts
+@@ -155,34 +155,42 @@ &combphy2_psu {
+ 
+ &cpu_b0 {
+ 	cpu-supply = <&vdd_cpu_big0_s0>;
+	mem-supply = <&vdd_cpu_big0_s0>;
+ };
+ 
+ &cpu_b1 {
+ 	cpu-supply = <&vdd_cpu_big0_s0>;
+	mem-supply = <&vdd_cpu_big0_s0>;
+ };
+ 
+ &cpu_b2 {
+ 	cpu-supply = <&vdd_cpu_big1_s0>;
+	mem-supply = <&vdd_cpu_big1_s0>;
+ };
+ 
+ &cpu_b3 {
+ 	cpu-supply = <&vdd_cpu_big1_s0>;
+	mem-supply = <&vdd_cpu_big1_s0>;
+ };
+ 
+ &cpu_l0 {
+ 	cpu-supply = <&vdd_cpu_lit_s0>;
+	mem-supply = <&vdd_cpu_lit_mem_s0>;
+ };
+ 
+ &cpu_l1 {
+ 	cpu-supply = <&vdd_cpu_lit_s0>;
+	mem-supply = <&vdd_cpu_lit_mem_s0>;
+ };
+ 
+ &cpu_l2 {
+ 	cpu-supply = <&vdd_cpu_lit_s0>;
+	mem-supply = <&vdd_cpu_lit_mem_s0>;
+ };
+ 
+ &cpu_l3 {
+ 	cpu-supply = <&vdd_cpu_lit_s0>;
+	mem-supply = <&vdd_cpu_lit_mem_s0>;
+ };
+ 
+ &i2c0 {
+-- 
+2.42.1

--- a/patch/kernel/rockchip-rk3588-edge/0023-Add-Initial-HDMITX-VOP2-For-RK3588.patch
+++ b/patch/kernel/rockchip-rk3588-edge/0023-Add-Initial-HDMITX-VOP2-For-RK3588.patch
--- a/patch/kernel/rockchip-rk3588-edge/0024-RK3588-Add-Crypto-Support.patch
+++ b/patch/kernel/rockchip-rk3588-edge/0024-RK3588-Add-Crypto-Support.patch
--- a/patch/kernel/rockchip-rk3588-edge/0025-RK3588-Add-HW-RNG-Support.patch
+++ b/patch/kernel/rockchip-rk3588-edge/0025-RK3588-Add-HW-RNG-Support.patch
@ -0,0 +1,665 @@
+From 2162fb12380c68ea4fa5300ef7475d6852196b89 Mon Sep 17 00:00:00 2001
+From: Muhammed Efe Cetin <efectn@protonmail.com>
+Date: Thu, 16 Nov 2023 17:49:42 +0300
+Subject: [PATCH 1/2] hwrng: rockchip: Add support for Rockchip HW RNG
+
+---
+ drivers/char/hw_random/Kconfig        |  13 +
+ drivers/char/hw_random/Makefile       |   1 +
+ drivers/char/hw_random/rockchip-rng.c | 574 ++++++++++++++++++++++++++
+ 3 files changed, 588 insertions(+)
+ create mode 100644 drivers/char/hw_random/rockchip-rng.c
+
+diff --git a/drivers/char/hw_random/Kconfig b/drivers/char/hw_random/Kconfig
+index 442c40efb200..11063cac5b36 100644
+--- a/drivers/char/hw_random/Kconfig
+++ b/drivers/char/hw_random/Kconfig
+@@ -538,6 +538,19 @@ config HW_RANDOM_XIPHERA
+ 	  To compile this driver as a module, choose M here: the
+ 	  module will be called xiphera-trng.
+ 
+config HW_RANDOM_ROCKCHIP
+	tristate "Rockchip Random Number Generator support"
+	depends on ARCH_ROCKCHIP
+	default HW_RANDOM
+	help
+	  This driver provides kernel-side support for the Random Number
+	  Generator hardware found on Rockchip cpus.
+
+	  To compile this driver as a module, choose M here: the
+	  module will be called rockchip-rng.
+
+	  If unsure, say Y.
+
+ config HW_RANDOM_ARM_SMCCC_TRNG
+ 	tristate "Arm SMCCC TRNG firmware interface support"
+ 	depends on HAVE_ARM_SMCCC_DISCOVERY
+diff --git a/drivers/char/hw_random/Makefile b/drivers/char/hw_random/Makefile
+index 32549a1186dc..fd3bbf6e08e1 100644
+--- a/drivers/char/hw_random/Makefile
+++ b/drivers/char/hw_random/Makefile
+@@ -35,6 +35,7 @@ obj-$(CONFIG_HW_RANDOM_IPROC_RNG200) += iproc-rng200.o
+ obj-$(CONFIG_HW_RANDOM_ST) += st-rng.o
+ obj-$(CONFIG_HW_RANDOM_XGENE) += xgene-rng.o
+ obj-$(CONFIG_HW_RANDOM_STM32) += stm32-rng.o
+obj-$(CONFIG_HW_RANDOM_ROCKCHIP) += rockchip-rng.o
+ obj-$(CONFIG_HW_RANDOM_PIC32) += pic32-rng.o
+ obj-$(CONFIG_HW_RANDOM_MESON) += meson-rng.o
+ obj-$(CONFIG_HW_RANDOM_CAVIUM) += cavium-rng.o cavium-rng-vf.o
+diff --git a/drivers/char/hw_random/rockchip-rng.c b/drivers/char/hw_random/rockchip-rng.c
+new file mode 100644
+index 000000000000..f7a3a7f52cca
+--- /dev/null
+++ b/drivers/char/hw_random/rockchip-rng.c
+@@ -0,0 +1,574 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * rockchip-rng.c Random Number Generator driver for the Rockchip
+ *
+ * Copyright (c) 2018, Fuzhou Rockchip Electronics Co., Ltd.
+ * Author: Lin Jinhan <troy.lin@rock-chips.com>
+ *
+ */
+#include <linux/clk.h>
+#include <linux/hw_random.h>
+#include <linux/iopoll.h>
+#include <linux/module.h>
+#include <linux/mod_devicetable.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+#include <linux/pm_runtime.h>
+
+#define _SBF(s, v)	((v) << (s))
+#define HIWORD_UPDATE(val, mask, shift) \
+			((val) << (shift) | (mask) << ((shift) + 16))
+
+#define ROCKCHIP_AUTOSUSPEND_DELAY		100
+#define ROCKCHIP_POLL_PERIOD_US			100
+#define ROCKCHIP_POLL_TIMEOUT_US		50000
+#define RK_MAX_RNG_BYTE				(32)
+
+/* start of CRYPTO V1 register define */
+#define CRYPTO_V1_CTRL				0x0008
+#define CRYPTO_V1_RNG_START			BIT(8)
+#define CRYPTO_V1_RNG_FLUSH			BIT(9)
+
+#define CRYPTO_V1_TRNG_CTRL			0x0200
+#define CRYPTO_V1_OSC_ENABLE			BIT(16)
+#define CRYPTO_V1_TRNG_SAMPLE_PERIOD(x)		(x)
+
+#define CRYPTO_V1_TRNG_DOUT_0			0x0204
+/* end of CRYPTO V1 register define */
+
+/* start of CRYPTO V2 register define */
+#define CRYPTO_V2_RNG_DEFAULT_OFFSET		0x0400
+#define CRYPTO_V2_RNG_CTL			0x0
+#define CRYPTO_V2_RNG_64_BIT_LEN		_SBF(4, 0x00)
+#define CRYPTO_V2_RNG_128_BIT_LEN		_SBF(4, 0x01)
+#define CRYPTO_V2_RNG_192_BIT_LEN		_SBF(4, 0x02)
+#define CRYPTO_V2_RNG_256_BIT_LEN		_SBF(4, 0x03)
+#define CRYPTO_V2_RNG_FATESY_SOC_RING		_SBF(2, 0x00)
+#define CRYPTO_V2_RNG_SLOWER_SOC_RING_0		_SBF(2, 0x01)
+#define CRYPTO_V2_RNG_SLOWER_SOC_RING_1		_SBF(2, 0x02)
+#define CRYPTO_V2_RNG_SLOWEST_SOC_RING		_SBF(2, 0x03)
+#define CRYPTO_V2_RNG_ENABLE			BIT(1)
+#define CRYPTO_V2_RNG_START			BIT(0)
+#define CRYPTO_V2_RNG_SAMPLE_CNT		0x0004
+#define CRYPTO_V2_RNG_DOUT_0			0x0010
+/* end of CRYPTO V2 register define */
+
+/* start of TRNG_V1 register define */
+/* TRNG is no longer subordinate to the Crypto module */
+#define TRNG_V1_CTRL				0x0000
+#define TRNG_V1_CTRL_NOP			_SBF(0, 0x00)
+#define TRNG_V1_CTRL_RAND			_SBF(0, 0x01)
+#define TRNG_V1_CTRL_SEED			_SBF(0, 0x02)
+
+#define TRNG_V1_STAT				0x0004
+#define TRNG_V1_STAT_SEEDED			BIT(9)
+#define TRNG_V1_STAT_GENERATING			BIT(30)
+#define TRNG_V1_STAT_RESEEDING			BIT(31)
+
+#define TRNG_V1_MODE				0x0008
+#define TRNG_V1_MODE_128_BIT			_SBF(3, 0x00)
+#define TRNG_V1_MODE_256_BIT			_SBF(3, 0x01)
+
+#define TRNG_V1_IE				0x0010
+#define TRNG_V1_IE_GLBL_EN			BIT(31)
+#define TRNG_V1_IE_SEED_DONE_EN			BIT(1)
+#define TRNG_V1_IE_RAND_RDY_EN			BIT(0)
+
+#define TRNG_V1_ISTAT				0x0014
+#define TRNG_V1_ISTAT_RAND_RDY			BIT(0)
+
+/* RAND0 ~ RAND7 */
+#define TRNG_V1_RAND0				0x0020
+#define TRNG_V1_RAND7				0x003C
+
+#define TRNG_V1_AUTO_RQSTS			0x0060
+
+#define TRNG_V1_VERSION				0x00F0
+#define TRNG_v1_VERSION_CODE			0x46bc
+/* end of TRNG_V1 register define */
+
+/* start of RKRNG register define */
+#define RKRNG_CTRL				0x0010
+#define RKRNG_CTRL_INST_REQ			BIT(0)
+#define RKRNG_CTRL_RESEED_REQ			BIT(1)
+#define RKRNG_CTRL_TEST_REQ			BIT(2)
+#define RKRNG_CTRL_SW_DRNG_REQ			BIT(3)
+#define RKRNG_CTRL_SW_TRNG_REQ			BIT(4)
+
+#define RKRNG_STATE				0x0014
+#define RKRNG_STATE_INST_ACK			BIT(0)
+#define RKRNG_STATE_RESEED_ACK			BIT(1)
+#define RKRNG_STATE_TEST_ACK			BIT(2)
+#define RKRNG_STATE_SW_DRNG_ACK			BIT(3)
+#define RKRNG_STATE_SW_TRNG_ACK			BIT(4)
+
+/* DRNG_DATA_0 ~ DNG_DATA_7 */
+#define RKRNG_DRNG_DATA_0			0x0070
+#define RKRNG_DRNG_DATA_7			0x008C
+
+/* end of RKRNG register define */
+
+struct rk_rng_soc_data {
+	u32 default_offset;
+
+	int (*rk_rng_init)(struct hwrng *rng);
+	int (*rk_rng_read)(struct hwrng *rng, void *buf, size_t max, bool wait);
+};
+
+struct rk_rng {
+	struct device		*dev;
+	struct hwrng		rng;
+	void __iomem		*mem;
+	struct rk_rng_soc_data	*soc_data;
+	int			clk_num;
+	struct clk_bulk_data	*clk_bulks;
+};
+
+static void rk_rng_writel(struct rk_rng *rng, u32 val, u32 offset)
+{
+	__raw_writel(val, rng->mem + offset);
+}
+
+static u32 rk_rng_readl(struct rk_rng *rng, u32 offset)
+{
+	return __raw_readl(rng->mem + offset);
+}
+
+static int rk_rng_init(struct hwrng *rng)
+{
+	int ret;
+	struct rk_rng *rk_rng = container_of(rng, struct rk_rng, rng);
+
+	dev_dbg(rk_rng->dev, "clk_bulk_prepare_enable.\n");
+
+	ret = clk_bulk_prepare_enable(rk_rng->clk_num, rk_rng->clk_bulks);
+	if (ret < 0) {
+		dev_err(rk_rng->dev, "failed to enable clks %d\n", ret);
+		return ret;
+	}
+
+	return 0;
+}
+
+static void rk_rng_cleanup(struct hwrng *rng)
+{
+	struct rk_rng *rk_rng = container_of(rng, struct rk_rng, rng);
+
+	dev_dbg(rk_rng->dev, "clk_bulk_disable_unprepare.\n");
+	clk_bulk_disable_unprepare(rk_rng->clk_num, rk_rng->clk_bulks);
+}
+
+static int rk_rng_read(struct hwrng *rng, void *buf, size_t max, bool wait)
+{
+	int ret;
+	int read_len = 0;
+	struct rk_rng *rk_rng = container_of(rng, struct rk_rng, rng);
+
+	if (!rk_rng->soc_data->rk_rng_read)
+		return -EFAULT;
+
+	ret = pm_runtime_get_sync(rk_rng->dev);
+	if (ret < 0) {
+		pm_runtime_put_noidle(rk_rng->dev);
+		return ret;
+	}
+
+	ret = 0;
+	while (max > ret) {
+		read_len = rk_rng->soc_data->rk_rng_read(rng, buf + ret,
+							 max - ret, wait);
+		if (read_len < 0) {
+			ret = read_len;
+			break;
+		}
+		ret += read_len;
+	}
+
+	pm_runtime_mark_last_busy(rk_rng->dev);
+	pm_runtime_put_sync_autosuspend(rk_rng->dev);
+
+	return ret;
+}
+
+static void rk_rng_read_regs(struct rk_rng *rng, u32 offset, void *buf,
+			     size_t size)
+{
+	u32 i;
+
+	for (i = 0; i < size; i += 4)
+		*(u32 *)(buf + i) = be32_to_cpu(rk_rng_readl(rng, offset + i));
+}
+
+static int crypto_v1_read(struct hwrng *rng, void *buf, size_t max, bool wait)
+{
+	int ret = 0;
+	u32 reg_ctrl = 0;
+	struct rk_rng *rk_rng = container_of(rng, struct rk_rng, rng);
+
+	/* enable osc_ring to get entropy, sample period is set as 100 */
+	reg_ctrl = CRYPTO_V1_OSC_ENABLE | CRYPTO_V1_TRNG_SAMPLE_PERIOD(100);
+	rk_rng_writel(rk_rng, reg_ctrl, CRYPTO_V1_TRNG_CTRL);
+
+	reg_ctrl = HIWORD_UPDATE(CRYPTO_V1_RNG_START, CRYPTO_V1_RNG_START, 0);
+
+	rk_rng_writel(rk_rng, reg_ctrl, CRYPTO_V1_CTRL);
+
+	ret = read_poll_timeout(rk_rng_readl, reg_ctrl,
+				!(reg_ctrl & CRYPTO_V1_RNG_START),
+				ROCKCHIP_POLL_PERIOD_US,
+				ROCKCHIP_POLL_TIMEOUT_US, false,
+				rk_rng, CRYPTO_V1_CTRL);
+
+	if (ret < 0)
+		goto out;
+
+	ret = min_t(size_t, max, RK_MAX_RNG_BYTE);
+
+	rk_rng_read_regs(rk_rng, CRYPTO_V1_TRNG_DOUT_0, buf, ret);
+
+out:
+	/* close TRNG */
+	rk_rng_writel(rk_rng, HIWORD_UPDATE(0, CRYPTO_V1_RNG_START, 0),
+		      CRYPTO_V1_CTRL);
+
+	return ret;
+}
+
+static int crypto_v2_read(struct hwrng *rng, void *buf, size_t max, bool wait)
+{
+	int ret = 0;
+	u32 reg_ctrl = 0;
+	struct rk_rng *rk_rng = container_of(rng, struct rk_rng, rng);
+
+	/* enable osc_ring to get entropy, sample period is set as 100 */
+	rk_rng_writel(rk_rng, 100, CRYPTO_V2_RNG_SAMPLE_CNT);
+
+	reg_ctrl |= CRYPTO_V2_RNG_256_BIT_LEN;
+	reg_ctrl |= CRYPTO_V2_RNG_SLOWER_SOC_RING_0;
+	reg_ctrl |= CRYPTO_V2_RNG_ENABLE;
+	reg_ctrl |= CRYPTO_V2_RNG_START;
+
+	rk_rng_writel(rk_rng, HIWORD_UPDATE(reg_ctrl, 0xffff, 0),
+		      CRYPTO_V2_RNG_CTL);
+
+	ret = read_poll_timeout(rk_rng_readl, reg_ctrl,
+				!(reg_ctrl & CRYPTO_V2_RNG_START),
+				ROCKCHIP_POLL_PERIOD_US,
+				ROCKCHIP_POLL_TIMEOUT_US, false,
+				rk_rng, CRYPTO_V2_RNG_CTL);
+	if (ret < 0)
+		goto out;
+
+	ret = min_t(size_t, max, RK_MAX_RNG_BYTE);
+
+	rk_rng_read_regs(rk_rng, CRYPTO_V2_RNG_DOUT_0, buf, ret);
+
+out:
+	/* close TRNG */
+	rk_rng_writel(rk_rng, HIWORD_UPDATE(0, 0xffff, 0), CRYPTO_V2_RNG_CTL);
+
+	return ret;
+}
+
+static int trng_v1_init(struct hwrng *rng)
+{
+	int ret;
+	uint32_t auto_reseed_cnt = 1000;
+	uint32_t reg_ctrl, status, version;
+	struct rk_rng *rk_rng = container_of(rng, struct rk_rng, rng);
+
+	version = rk_rng_readl(rk_rng, TRNG_V1_VERSION);
+	if (version != TRNG_v1_VERSION_CODE) {
+		dev_err(rk_rng->dev,
+			"wrong trng version, expected = %08x, actual = %08x\n",
+			TRNG_V1_VERSION, version);
+		ret = -EFAULT;
+		goto exit;
+	}
+
+	status = rk_rng_readl(rk_rng, TRNG_V1_STAT);
+
+	/* TRNG should wait RAND_RDY triggered if it is busy or not seeded */
+	if (!(status & TRNG_V1_STAT_SEEDED) ||
+	    (status & TRNG_V1_STAT_GENERATING) ||
+	    (status & TRNG_V1_STAT_RESEEDING)) {
+		uint32_t mask = TRNG_V1_STAT_SEEDED |
+				TRNG_V1_STAT_GENERATING |
+				TRNG_V1_STAT_RESEEDING;
+
+		udelay(10);
+
+		/* wait for GENERATING and RESEEDING flag to clear */
+		read_poll_timeout(rk_rng_readl, reg_ctrl,
+				  (reg_ctrl & mask) == TRNG_V1_STAT_SEEDED,
+				  ROCKCHIP_POLL_PERIOD_US,
+				  ROCKCHIP_POLL_TIMEOUT_US, false,
+				  rk_rng, TRNG_V1_STAT);
+	}
+
+	/* clear ISTAT flag because trng may auto reseeding when power on */
+	reg_ctrl = rk_rng_readl(rk_rng, TRNG_V1_ISTAT);
+	rk_rng_writel(rk_rng, reg_ctrl, TRNG_V1_ISTAT);
+
+	/* auto reseed after (auto_reseed_cnt * 16) byte rand generate */
+	rk_rng_writel(rk_rng, auto_reseed_cnt, TRNG_V1_AUTO_RQSTS);
+
+	ret = 0;
+exit:
+
+	return ret;
+}
+
+static int trng_v1_read(struct hwrng *rng, void *buf, size_t max, bool wait)
+{
+	int ret = 0;
+	u32 reg_ctrl = 0;
+	struct rk_rng *rk_rng = container_of(rng, struct rk_rng, rng);
+
+	/* clear ISTAT anyway */
+	reg_ctrl = rk_rng_readl(rk_rng, TRNG_V1_ISTAT);
+	rk_rng_writel(rk_rng, reg_ctrl, TRNG_V1_ISTAT);
+
+	/* generate 256bit random */
+	rk_rng_writel(rk_rng, TRNG_V1_MODE_256_BIT, TRNG_V1_MODE);
+	rk_rng_writel(rk_rng, TRNG_V1_CTRL_RAND, TRNG_V1_CTRL);
+
+	/*
+	 * Generate2 56 bit random data will cost 1024 clock cycles.
+	 * Estimated at 150M RNG module frequency, it takes 6.7 microseconds.
+	 */
+	udelay(10);
+	reg_ctrl = rk_rng_readl(rk_rng, TRNG_V1_ISTAT);
+	if (!(reg_ctrl & TRNG_V1_ISTAT_RAND_RDY)) {
+		/* wait RAND_RDY triggered */
+		ret = read_poll_timeout(rk_rng_readl, reg_ctrl,
+					(reg_ctrl & TRNG_V1_ISTAT_RAND_RDY),
+					ROCKCHIP_POLL_PERIOD_US,
+					ROCKCHIP_POLL_TIMEOUT_US, false,
+					rk_rng, TRNG_V1_ISTAT);
+		if (ret < 0)
+			goto out;
+	}
+
+	ret = min_t(size_t, max, RK_MAX_RNG_BYTE);
+
+	rk_rng_read_regs(rk_rng, TRNG_V1_RAND0, buf, ret);
+
+	/* clear all status flag */
+	rk_rng_writel(rk_rng, reg_ctrl, TRNG_V1_ISTAT);
+out:
+	/* close TRNG */
+	rk_rng_writel(rk_rng, TRNG_V1_CTRL_NOP, TRNG_V1_CTRL);
+
+	return ret;
+}
+
+static int rkrng_init(struct hwrng *rng)
+{
+	struct rk_rng *rk_rng = container_of(rng, struct rk_rng, rng);
+	u32 reg = 0;
+
+	rk_rng_writel(rk_rng, HIWORD_UPDATE(0, 0xffff, 0), RKRNG_CTRL);
+
+	reg = rk_rng_readl(rk_rng, RKRNG_STATE);
+	rk_rng_writel(rk_rng, reg, RKRNG_STATE);
+
+	return 0;
+}
+
+static int rkrng_read(struct hwrng *rng, void *buf, size_t max, bool wait)
+{
+	struct rk_rng *rk_rng = container_of(rng, struct rk_rng, rng);
+	u32 reg_ctrl = 0;
+	int ret;
+
+	reg_ctrl = RKRNG_CTRL_SW_DRNG_REQ;
+
+	rk_rng_writel(rk_rng, HIWORD_UPDATE(reg_ctrl, 0xffff, 0), RKRNG_CTRL);
+
+	ret = readl_poll_timeout(rk_rng->mem + RKRNG_STATE, reg_ctrl,
+				 (reg_ctrl & RKRNG_STATE_SW_DRNG_ACK),
+				 ROCKCHIP_POLL_PERIOD_US,
+				 ROCKCHIP_POLL_TIMEOUT_US);
+
+	if (ret)
+		goto exit;
+
+	rk_rng_writel(rk_rng, reg_ctrl, RKRNG_STATE);
+
+	ret = min_t(size_t, max, RK_MAX_RNG_BYTE);
+
+	rk_rng_read_regs(rk_rng, RKRNG_DRNG_DATA_0, buf, ret);
+
+exit:
+	/* close TRNG */
+	rk_rng_writel(rk_rng, HIWORD_UPDATE(0, 0xffff, 0), RKRNG_CTRL);
+
+	return ret;
+}
+
+static const struct rk_rng_soc_data crypto_v1_soc_data = {
+	.default_offset = 0,
+
+	.rk_rng_read = crypto_v1_read,
+};
+
+static const struct rk_rng_soc_data crypto_v2_soc_data = {
+	.default_offset = CRYPTO_V2_RNG_DEFAULT_OFFSET,
+
+	.rk_rng_read = crypto_v2_read,
+};
+
+static const struct rk_rng_soc_data trng_v1_soc_data = {
+	.default_offset = 0,
+
+	.rk_rng_init = trng_v1_init,
+	.rk_rng_read = trng_v1_read,
+};
+
+static const struct rk_rng_soc_data rkrng_soc_data = {
+	.default_offset = 0,
+
+	.rk_rng_init = rkrng_init,
+	.rk_rng_read = rkrng_read,
+};
+
+static const struct of_device_id rk_rng_dt_match[] = {
+	{
+		.compatible = "rockchip,cryptov1-rng",
+		.data = (void *)&crypto_v1_soc_data,
+	},
+	{
+		.compatible = "rockchip,cryptov2-rng",
+		.data = (void *)&crypto_v2_soc_data,
+	},
+	{
+		.compatible = "rockchip,trngv1",
+		.data = (void *)&trng_v1_soc_data,
+	},
+		{
+		.compatible = "rockchip,rkrng",
+		.data = (void *)&rkrng_soc_data,
+	},
+	{ },
+};
+
+MODULE_DEVICE_TABLE(of, rk_rng_dt_match);
+
+static int rk_rng_probe(struct platform_device *pdev)
+{
+	int ret;
+	struct rk_rng *rk_rng;
+	struct device_node *np = pdev->dev.of_node;
+	const struct of_device_id *match;
+	resource_size_t map_size;
+
+	dev_dbg(&pdev->dev, "probing...\n");
+	rk_rng = devm_kzalloc(&pdev->dev, sizeof(struct rk_rng), GFP_KERNEL);
+	if (!rk_rng)
+		return -ENOMEM;
+
+	match = of_match_node(rk_rng_dt_match, np);
+	rk_rng->soc_data = (struct rk_rng_soc_data *)match->data;
+
+	rk_rng->dev = &pdev->dev;
+	rk_rng->rng.name    = "rockchip";
+#ifndef CONFIG_PM
+	rk_rng->rng.init    = rk_rng_init;
+	rk_rng->rng.cleanup = rk_rng_cleanup,
+#endif
+	rk_rng->rng.read    = rk_rng_read;
+	rk_rng->rng.quality = 999;
+
+	rk_rng->mem = devm_of_iomap(&pdev->dev, pdev->dev.of_node, 0, &map_size);
+	if (IS_ERR(rk_rng->mem))
+		return PTR_ERR(rk_rng->mem);
+
+	/* compatible with crypto v2 module */
+	/*
+	 * With old dtsi configurations, the RNG base was equal to the crypto
+	 * base, so both drivers could not be enabled at the same time.
+	 * RNG base = CRYPTO base + RNG offset
+	 * (Since RK356X, RNG module is no longer belongs to CRYPTO module)
+	 *
+	 * With new dtsi configurations, CRYPTO regs is divided into two parts
+	 * |---cipher---|---rng---|---pka---|, and RNG base is real RNG base.
+	 * RNG driver and CRYPTO driver could be enabled at the same time.
+	 */
+	if (map_size > rk_rng->soc_data->default_offset)
+		rk_rng->mem += rk_rng->soc_data->default_offset;
+
+	rk_rng->clk_num = devm_clk_bulk_get_all(&pdev->dev, &rk_rng->clk_bulks);
+	if (rk_rng->clk_num < 0) {
+		dev_err(&pdev->dev, "failed to get clks property\n");
+		return -ENODEV;
+	}
+
+	platform_set_drvdata(pdev, rk_rng);
+
+	pm_runtime_set_autosuspend_delay(&pdev->dev,
+					 ROCKCHIP_AUTOSUSPEND_DELAY);
+	pm_runtime_use_autosuspend(&pdev->dev);
+	pm_runtime_enable(&pdev->dev);
+
+	ret = devm_hwrng_register(&pdev->dev, &rk_rng->rng);
+	if (ret) {
+		pm_runtime_dont_use_autosuspend(&pdev->dev);
+		pm_runtime_disable(&pdev->dev);
+	}
+
+	/* for some platform need hardware operation when probe */
+	if (rk_rng->soc_data->rk_rng_init) {
+		pm_runtime_get_sync(rk_rng->dev);
+
+		ret = rk_rng->soc_data->rk_rng_init(&rk_rng->rng);
+
+		pm_runtime_mark_last_busy(rk_rng->dev);
+		pm_runtime_put_sync_autosuspend(rk_rng->dev);
+	}
+
+	return ret;
+}
+
+#ifdef CONFIG_PM
+static int rk_rng_runtime_suspend(struct device *dev)
+{
+	struct rk_rng *rk_rng = dev_get_drvdata(dev);
+
+	rk_rng_cleanup(&rk_rng->rng);
+
+	return 0;
+}
+
+static int rk_rng_runtime_resume(struct device *dev)
+{
+	struct rk_rng *rk_rng = dev_get_drvdata(dev);
+
+	return rk_rng_init(&rk_rng->rng);
+}
+
+static const struct dev_pm_ops rk_rng_pm_ops = {
+	SET_RUNTIME_PM_OPS(rk_rng_runtime_suspend,
+			   rk_rng_runtime_resume, NULL)
+	SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
+				pm_runtime_force_resume)
+};
+
+#endif
+
+static struct platform_driver rk_rng_driver = {
+	.driver	= {
+		.name	= "rockchip-rng",
+#ifdef CONFIG_PM
+		.pm	= &rk_rng_pm_ops,
+#endif
+		.of_match_table = rk_rng_dt_match,
+	},
+	.probe	= rk_rng_probe,
+};
+
+module_platform_driver(rk_rng_driver);
+
+MODULE_DESCRIPTION("ROCKCHIP H/W Random Number Generator driver");
+MODULE_AUTHOR("Lin Jinhan <troy.lin@rock-chips.com>");
+MODULE_LICENSE("GPL v2");
+-- 
+2.42.1
+
+
+From 80c1c5fd75a0057d19c739c1fae76c63fd27c220 Mon Sep 17 00:00:00 2001
+From: Muhammed Efe Cetin <efectn@protonmail.com>
+Date: Thu, 16 Nov 2023 17:52:35 +0300
+Subject: [PATCH 2/2] arm64: dts: Add HW RNG support to RK3588S
+
+---
+ arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 10 ++++++++++
+ 1 file changed, 10 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
+index a89577fb801e..ed6197dd9267 100644
+--- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
+@@ -2250,6 +2250,16 @@ crypto: crypto@fe370000 {
+ 		status = "okay";
+ 	};
+ 
+	rng: rng@fe378000 {
+		compatible = "rockchip,trngv1";
+		reg = <0x0 0xfe378000 0x0 0x200>;
+		interrupts = <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH 0>;
+		clocks = <&scmi_clk SCMI_HCLK_SECURE_NS>;
+		clock-names = "hclk_trng";
+		resets = <&scmi_reset SRST_H_TRNG_NS>;
+		reset-names = "reset";
+	};
+
+ 	i2s0_8ch: i2s@fe470000 {
+ 		compatible = "rockchip,rk3588-i2s-tdm";
+ 		reg = <0x0 0xfe470000 0x0 0x1000>;
+-- 
+2.42.1
+
--- a/patch/kernel/rockchip-rk3588-edge/0025-arm64-dts-rockchip-rk3588-add-sfc-node.patch
+++ b/patch/kernel/rockchip-rk3588-edge/0025-arm64-dts-rockchip-rk3588-add-sfc-node.patch
@ -1,36 +0,0 @@
-From 951f73458d984d485d73f64a00d8dd041187222a Mon Sep 17 00:00:00 2001
-From: Muhammed Efe Cetin <efectn@protonmail.com>
-Date: Sat, 29 Jul 2023 21:41:14 +0300
-Subject: [PATCH 1/1] arm64: dts: rockchip: rk3588: add sfc node
-
---
- arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 13 +++++++++++++
- 1 file changed, 13 insertions(+)
-
-diff --git a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
-index 5dde719c9cd7..7902c638a5be 100644
--- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
-+++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
-@@ -2251,6 +2251,19 @@ wdt: watchdog@feaf0000 {
- 		interrupts = <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH 0>;
- 	};
- 
-+	sfc: spi@fe2b0000 {
-+		compatible = "rockchip,sfc";
-+		reg = <0x0 0xfe2b0000 0x0 0x4000>;
-+		interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH 0>;
-+		clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>;
-+		clock-names = "clk_sfc", "hclk_sfc";
-+		assigned-clocks = <&cru SCLK_SFC>;
-+		assigned-clock-rates = <100000000>;
-+		#address-cells = <1>;
-+		#size-cells = <0>;
-+		status = "disabled";
-+	};
-+
- 	spi0: spi@feb00000 {
- 		compatible = "rockchip,rk3588-spi", "rockchip,rk3066-spi";
- 		reg = <0x0 0xfeb00000 0x0 0x1000>;
-- 
-2.41.0
-
--- a/patch/kernel/rockchip-rk3588-edge/0026-Add-missing-nodes-to-Orange-Pi-5.patch
+++ b/patch/kernel/rockchip-rk3588-edge/0026-Add-missing-nodes-to-Orange-Pi-5.patch
@ -0,0 +1,322 @@
+From bdf64687d6ecd6fddbceb840da4accf636739633 Mon Sep 17 00:00:00 2001
+From: Muhammed Efe Cetin <efectn@protonmail.com>
+Date: Thu, 16 Nov 2023 18:09:07 +0300
+Subject: [PATCH 1/2] arm64: dts: Add missing nodes to Orange Pi 5
+
+---
+ .../boot/dts/rockchip/rk3588s-orangepi-5.dts  | 214 +++++++++++++++++-
+ 1 file changed, 213 insertions(+), 1 deletion(-)
+
+diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5.dts b/arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5.dts
+index 8f399c4317bd..8c834ced3686 100644
+--- a/arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5.dts
+@@ -6,6 +6,7 @@
+ #include <dt-bindings/leds/common.h>
+ #include <dt-bindings/input/input.h>
+ #include <dt-bindings/pinctrl/rockchip.h>
+#include <dt-bindings/usb/pd.h>
+ #include "rk3588s.dtsi"
+ 
+ / {
+@@ -47,6 +48,46 @@ led-1 {
+ 		};
+ 	};
+ 
+	analog-sound {
+		compatible = "simple-audio-card";
+		pinctrl-names = "default";
+		pinctrl-0 = <&hp_detect>;
+		simple-audio-card,name = "Orange Pi 5 Audio";
+		simple-audio-card,bitclock-master = <&masterdai>;
+		simple-audio-card,format = "i2s";
+		simple-audio-card,frame-master = <&masterdai>;
+		simple-audio-card,hp-det-gpio = <&gpio1 RK_PD5 GPIO_ACTIVE_LOW>;
+		simple-audio-card,mclk-fs = <256>;
+		simple-audio-card,pin-switches = "Headphones", "Speaker";
+		simple-audio-card,routing =
+			"Speaker Amplifier INL", "LOUT2",
+			"Speaker Amplifier INR", "ROUT2",
+			"Speaker", "Speaker Amplifier OUTL",
+			"Speaker", "Speaker Amplifier OUTR",
+			"Headphones Amplifier INL", "LOUT1",
+			"Headphones Amplifier INR", "ROUT1",
+			"Headphones", "Headphones Amplifier OUTL",
+			"Headphones", "Headphones Amplifier OUTR",
+			"LINPUT1", "Onboard Microphone",
+			"RINPUT1", "Onboard Microphone",
+			"LINPUT2", "Microphone Jack",
+			"RINPUT2", "Microphone Jack";
+		simple-audio-card,widgets =
+			"Microphone", "Microphone Jack",
+			"Microphone", "Onboard Microphone",
+			"Headphone", "Headphones",
+			"Speaker", "Speaker";
+
+		simple-audio-card,cpu {
+			sound-dai = <&i2s1_8ch>;
+		};
+
+		masterdai: simple-audio-card,codec {
+			sound-dai = <&es8388>;
+			system-clock-frequency = <12288000>;
+		};
+	};
+
+ 	vbus_typec: vbus-typec-regulator {
+ 		compatible = "regulator-fixed";
+ 		enable-active-high;
+@@ -102,34 +143,47 @@ &combphy2_psu {
+ 
+ &cpu_b0 {
+ 	cpu-supply = <&vdd_cpu_big0_s0>;
+	mem-supply = <&vdd_cpu_big0_s0>;
+ };
+ 
+ &cpu_b1 {
+ 	cpu-supply = <&vdd_cpu_big0_s0>;
+	mem-supply = <&vdd_cpu_big0_s0>;
+ };
+ 
+ &cpu_b2 {
+ 	cpu-supply = <&vdd_cpu_big1_s0>;
+	mem-supply = <&vdd_cpu_big1_s0>;
+ };
+ 
+ &cpu_b3 {
+ 	cpu-supply = <&vdd_cpu_big1_s0>;
+	mem-supply = <&vdd_cpu_big1_s0>;
+ };
+ 
+ &cpu_l0 {
+ 	cpu-supply = <&vdd_cpu_lit_s0>;
+	mem-supply = <&vdd_cpu_lit_mem_s0>;
+ };
+ 
+ &cpu_l1 {
+ 	cpu-supply = <&vdd_cpu_lit_s0>;
+	mem-supply = <&vdd_cpu_lit_mem_s0>;
+ };
+ 
+ &cpu_l2 {
+ 	cpu-supply = <&vdd_cpu_lit_s0>;
+	mem-supply = <&vdd_cpu_lit_mem_s0>;
+ };
+ 
+ &cpu_l3 {
+ 	cpu-supply = <&vdd_cpu_lit_s0>;
+	mem-supply = <&vdd_cpu_lit_mem_s0>;
+};
+
+&display_subsystem {
+	clocks = <&hdptxphy_hdmi_clk0>;
+	clock-names = "hdmi0_phy_pll";
+ };
+ 
+ &gmac1 {
+@@ -223,6 +277,75 @@ hym8563: rtc@51 {
+ 		interrupts = <RK_PB0 IRQ_TYPE_LEVEL_LOW>;
+ 		wakeup-source;
+ 	};
+
+	es8388: audio-codec@10 {
+		compatible = "everest,es8388";
+		reg = <0x10>;
+		clocks = <&cru I2S1_8CH_MCLKOUT>;
+		assigned-clocks = <&cru I2S1_8CH_MCLKOUT>;
+		assigned-clock-rates = <12288000>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&i2s1m0_mclk>;
+		#sound-dai-cells = <0>;
+	};
+
+	usbc0: usb-typec@22 {
+		compatible = "fcs,fusb302";
+		reg = <0x22>;
+		interrupt-parent = <&gpio0>;
+		interrupts = <RK_PD3 IRQ_TYPE_LEVEL_LOW>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&usbc0_int>;
+		vbus-supply = <&vbus_typec>;
+
+		usb_con: connector {
+			compatible = "usb-c-connector";
+			label = "USB-C";
+			data-role = "dual";
+			power-role = "dual";
+			try-power-role = "source";
+			op-sink-microwatt = <1000000>;
+			sink-pdos = <PDO_FIXED(5000, 2000, PDO_FIXED_USB_COMM)>;
+			source-pdos = <PDO_FIXED(5000, 1500, PDO_FIXED_USB_COMM)>;
+
+			ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@0 {
+					reg = <0>;
+					usbc0_hs: endpoint {
+						remote-endpoint = <&usb_host0_xhci_drd_sw>;
+					};
+				};
+
+				port@1 {
+					reg = <1>;
+					usbc0_ss: endpoint {
+						remote-endpoint = <&usbdp_phy0_typec_ss>;
+					};
+				};
+
+				port@2 {
+					reg = <2>;
+					usbc0_sbu: endpoint {
+						remote-endpoint = <&usbdp_phy0_typec_sbu>;
+					};
+				};
+			};
+		};
+	};
+};
+
+&i2s1_8ch {
+	rockchip,i2s-tx-route = <3 2 1 0>;
+	rockchip,i2s-rx-route = <1 3 2 0>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&i2s1m0_sclk
+	             &i2s1m0_lrck
+	             &i2s1m0_sdi1
+	             &i2s1m0_sdo3>;
+	status = "okay";
+ };
+ 
+ &mdio1 {
+@@ -263,6 +386,12 @@ typec5v_pwren: typec5v-pwren {
+ 			rockchip,pins = <3 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>;
+ 		};
+ 	};
+
+	sound {
+		hp_detect: hp-detect {
+			rockchip,pins = <1 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+ };
+ 
+ &saradc {
+@@ -363,7 +492,7 @@ regulator-state-mem {
+ 				};
+ 			};
+ 
+-			vdd_cpu_lit_s0: dcdc-reg2 {
+			vdd_cpu_lit_s0: vdd_cpu_lit_mem_s0: dcdc-reg2 {
+ 				regulator-name = "vdd_cpu_lit_s0";
+ 				regulator-always-on;
+ 				regulator-boot-on;
+@@ -624,6 +753,14 @@ &tsadc {
+ 	status = "okay";
+ };
+ 
+&u2phy0 {
+	status = "okay";
+};
+
+&u2phy0_otg {
+	status = "okay";
+};
+
+ &u2phy2 {
+ 	status = "okay";
+ };
+@@ -649,10 +786,56 @@ &usb_host0_ehci {
+ 	status = "okay";
+ };
+ 
+&usbdp_phy0 {
+	orientation-switch;
+	mode-switch;
+	svid = <0xff01>;
+	sbu1-dc-gpios = <&gpio4 RK_PA5 GPIO_ACTIVE_HIGH>;
+	sbu2-dc-gpios = <&gpio4 RK_PA7 GPIO_ACTIVE_HIGH>;
+
+	port {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		usbdp_phy0_typec_ss: endpoint@0 {
+			reg = <0>;
+			remote-endpoint = <&usbc0_ss>;
+		};
+
+		usbdp_phy0_typec_sbu: endpoint@1 {
+			reg = <1>;
+			remote-endpoint = <&usbc0_sbu>;
+		};
+	};
+};
+
+&usbdp_phy0_dp {
+	status = "okay";
+};
+
+&usbdp_phy0_u3 {
+	status = "okay";
+};
+
+ &usb_host0_ohci {
+ 	status = "okay";
+ };
+ 
+&usb_host0_xhci {
+	usb-role-switch;
+	dr_mode = "otg";
+	status = "okay";
+
+	port {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		usb_host0_xhci_drd_sw: endpoint {
+			remote-endpoint = <&usbc0_hs>;
+		};
+	};
+};
+
+ &usb_host1_ehci {
+ 	status = "okay";
+ };
+@@ -660,3 +843,32 @@ &usb_host1_ehci {
+ &usb_host1_ohci {
+ 	status = "okay";
+ };
+
+&usb_host2_xhci {
+	dr_mode = "host";
+	status = "okay";
+};
+
+&hdmi0 {
+	status = "okay";
+};
+
+&hdmi0_in_vp0 {
+	status = "okay";
+};
+
+&hdptxphy_hdmi0 {
+	status = "okay";
+};
+
+&hdptxphy_hdmi_clk0 {
+	status = "okay";
+};
+
+&vop_mmu {
+	status = "okay";
+};
+
+&vop {
+	status = "okay";
+};
+-- 
+2.42.1
+
--- a/patch/kernel/rockchip-rk3588-edge/0027-arm64-dts-Add-missing-nodes-to-Orange-Pi-5-Plus.patch
+++ b/patch/kernel/rockchip-rk3588-edge/0027-arm64-dts-Add-missing-nodes-to-Orange-Pi-5-Plus.patch
@ -0,0 +1,282 @@
+From 87ce7cdd0d7b56f1826173204add338e25aa8037 Mon Sep 17 00:00:00 2001
+From: Muhammed Efe Cetin <efectn@protonmail.com>
+Date: Thu, 16 Nov 2023 18:15:09 +0300
+Subject: [PATCH 2/2] arm64: dts: Add missing nodes to Orange Pi 5 Plus
+
+---
+ .../dts/rockchip/rk3588-orangepi-5-plus.dts   | 178 +++++++++++++++++-
+ 1 file changed, 177 insertions(+), 1 deletion(-)
+
+diff --git a/arch/arm64/boot/dts/rockchip/rk3588-orangepi-5-plus.dts b/arch/arm64/boot/dts/rockchip/rk3588-orangepi-5-plus.dts
+index 298c183d6f4f..8368b3117351 100644
+--- a/arch/arm64/boot/dts/rockchip/rk3588-orangepi-5-plus.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3588-orangepi-5-plus.dts
+@@ -200,6 +200,18 @@ vcc5v0_sys: vcc5v0-sys-regulator {
+ 		regulator-max-microvolt = <5000000>;
+ 	};
+ 
+	vbus5v0_typec: vbus5v0-typec-regulator {
+		compatible = "regulator-fixed";
+		enable-active-high;
+		gpio = <&gpio4 RK_PB0 GPIO_ACTIVE_HIGH>;
+		regulator-name = "vbus5v0_typec";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&typec5v_pwren>;
+		vin-supply = <&vcc5v0_sys>;
+	};
+
+ 	vcc5v0_usb20: vcc5v0-usb20-regulator {
+ 		compatible = "regulator-fixed";
+ 		enable-active-high;
+@@ -227,34 +239,47 @@ &combphy2_psu {
+ 
+ &cpu_b0 {
+ 	cpu-supply = <&vdd_cpu_big0_s0>;
+	mem-supply = <&vdd_cpu_big0_s0>;
+ };
+ 
+ &cpu_b1 {
+ 	cpu-supply = <&vdd_cpu_big0_s0>;
+	mem-supply = <&vdd_cpu_big0_s0>;
+ };
+ 
+ &cpu_b2 {
+ 	cpu-supply = <&vdd_cpu_big1_s0>;
+	mem-supply = <&vdd_cpu_big1_s0>;
+ };
+ 
+ &cpu_b3 {
+ 	cpu-supply = <&vdd_cpu_big1_s0>;
+	mem-supply = <&vdd_cpu_big1_s0>;
+ };
+ 
+ &cpu_l0 {
+ 	cpu-supply = <&vdd_cpu_lit_s0>;
+	mem-supply = <&vdd_cpu_lit_mem_s0>;
+ };
+ 
+ &cpu_l1 {
+ 	cpu-supply = <&vdd_cpu_lit_s0>;
+	mem-supply = <&vdd_cpu_lit_mem_s0>;
+ };
+ 
+ &cpu_l2 {
+ 	cpu-supply = <&vdd_cpu_lit_s0>;
+	mem-supply = <&vdd_cpu_lit_mem_s0>;
+ };
+ 
+ &cpu_l3 {
+ 	cpu-supply = <&vdd_cpu_lit_s0>;
+	mem-supply = <&vdd_cpu_lit_mem_s0>;
+};
+
+&display_subsystem {
+	clocks = <&hdptxphy_hdmi_clk0>;
+	clock-names = "hdmi0_phy_pll";
+ };
+ 
+ &i2c0 {
+@@ -312,6 +337,53 @@ hym8563: rtc@51 {
+ 		pinctrl-0 = <&hym8563_int>;
+ 		wakeup-source;
+ 	};
+
+	usbc0: usb-typec@22 {
+		compatible = "fcs,fusb302";
+		reg = <0x22>;
+		interrupt-parent = <&gpio0>;
+		interrupts = <RK_PD3 IRQ_TYPE_LEVEL_LOW>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&usbc0_int>;
+		vbus-supply = <&vbus5v0_typec>;
+
+		usb_con: connector {
+			compatible = "usb-c-connector";
+			label = "USB-C";
+			data-role = "dual";
+			power-role = "dual";
+			try-power-role = "source";
+			op-sink-microwatt = <1000000>;
+			sink-pdos = <PDO_FIXED(5000, 2000, PDO_FIXED_USB_COMM)>;
+			source-pdos = <PDO_FIXED(5000, 1500, PDO_FIXED_USB_COMM)>;
+
+			ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@0 {
+					reg = <0>;
+					usbc0_hs: endpoint {
+						remote-endpoint = <&usb_host0_xhci_drd_sw>;
+					};
+				};
+
+				port@1 {
+					reg = <1>;
+					usbc0_ss: endpoint {
+						remote-endpoint = <&usbdp_phy0_typec_ss>;
+					};
+				};
+
+				port@2 {
+					reg = <2>;
+					usbc0_sbu: endpoint {
+						remote-endpoint = <&usbdp_phy0_typec_sbu>;
+					};
+				};
+			};
+		};
+	};
+ };
+ 
+ &i2c7 {
+@@ -409,6 +481,14 @@ hp_detect: hp-detect {
+ 	};
+ 
+ 	usb {
+		typec5v_pwren: typec5v-pwren {
+			rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+
+		usbc0_int: usbc0-int {
+			rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+
+ 		vcc5v0_usb20_en: vcc5v0-usb20-en {
+ 			rockchip,pins = <3 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>;
+ 		};
+@@ -536,7 +616,7 @@ regulator-state-mem {
+ 				};
+ 			};
+ 
+-			vdd_cpu_lit_s0: dcdc-reg2 {
+			vdd_cpu_lit_s0: vdd_cpu_lit_mem_s0: dcdc-reg2 {
+ 				regulator-name = "vdd_cpu_lit_s0";
+ 				regulator-always-on;
+ 				regulator-boot-on;
+@@ -803,6 +883,22 @@ &tsadc {
+ 	status = "okay";
+ };
+ 
+&u2phy0 {
+	status = "okay";
+};
+
+&u2phy0_otg {
+	status = "okay";
+};
+
+&u2phy1 {
+	status = "okay";
+};
+
+&u2phy1_otg {
+	status = "okay";
+};
+
+ &u2phy2 {
+ 	status = "okay";
+ };
+@@ -831,6 +927,44 @@ &uart9 {
+ 	status = "okay";
+ };
+ 
+&usbdp_phy0 {
+	orientation-switch;
+	mode-switch;
+	sbu1-dc-gpios = <&gpio4 RK_PA6 GPIO_ACTIVE_HIGH>;
+	sbu2-dc-gpios = <&gpio4 RK_PA7 GPIO_ACTIVE_HIGH>;
+	status = "okay";
+	svid = <0xff01>;
+
+	port {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		usbdp_phy0_typec_ss: endpoint@0 {
+			reg = <0>;
+			remote-endpoint = <&usbc0_ss>;
+		};
+
+		usbdp_phy0_typec_sbu: endpoint@1 {
+			reg = <1>;
+			remote-endpoint = <&usbc0_sbu>;
+		};
+	};
+};
+
+&usbdp_phy0_u3 {
+	status = "okay";
+};
+
+&usbdp_phy1 {
+	rockchip,dp-lane-mux = <2 3>;
+	status = "okay";
+};
+
+&usbdp_phy1_u3 {
+	status = "okay";
+};
+
+
+ &usb_host0_ehci {
+ 	status = "okay";
+ };
+@@ -839,6 +973,20 @@ &usb_host0_ohci {
+ 	status = "okay";
+ };
+ 
+&usb_host0_xhci {
+	dr_mode = "otg";
+	usb-role-switch;
+	status = "okay";
+
+	port {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		usb_host0_xhci_drd_sw: endpoint {
+			remote-endpoint = <&usbc0_hs>;
+		};
+	};
+};
+
+ &usb_host1_ehci {
+ 	status = "okay";
+ };
+@@ -846,3 +994,31 @@ &usb_host1_ehci {
+ &usb_host1_ohci {
+ 	status = "okay";
+ };
+
+&usb_host1_xhci {
+	status = "okay";
+};
+
+&hdmi0 {
+	status = "okay";
+};
+
+&hdmi0_in_vp0 {
+	status = "okay";
+};
+
+&hdptxphy_hdmi0 {
+	status = "okay";
+};
+
+&hdptxphy_hdmi_clk0 {
+	status = "okay";
+};
+
+&vop_mmu {
+	status = "okay";
+};
+
+&vop {
+	status = "okay";
+};
+-- 
+2.42.1
+
--- a/patch/kernel/rockchip-rk3588-edge/dt/rk3588-orangepi-5-plus.dts
+++ b/patch/kernel/rockchip-rk3588-edge/dt/rk3588-orangepi-5-plus.dts
--- a/patch/kernel/rockchip-rk3588-edge/dt/rk3588s-nanopi-r6s.dts
+++ b/patch/kernel/rockchip-rk3588-edge/dt/rk3588s-nanopi-r6s.dts
@ -224,6 +224,11 @@
 	mem-supply = <&vdd_cpu_lit_mem_s0>;
 };

+&display_subsystem {
+	clocks = <&hdptxphy_hdmi_clk0>;
+	clock-names = "hdmi0_phy_pll";
+};
+
 &i2c0 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&i2c0m2_xfer>;
@ -830,6 +835,30 @@
 	status = "okay";
 };

+&hdmi0 {
+	status = "okay";
+};
+
+&hdmi0_in_vp0 {
+	status = "okay";
+};
+
+&hdptxphy_hdmi0 {
+	status = "okay";
+};
+
+&hdptxphy_hdmi_clk0 {
+	status = "okay";
+};
+
+&vop_mmu {
+	status = "okay";
+};
+
+&vop {
+	status = "okay";
+};
+
 &wdt {
 	status = "okay";
 };
--- a/patch/kernel/rockchip-rk3588-edge/dt/rk3588s-orangepi-5.dts
+++ b/patch/kernel/rockchip-rk3588-edge/dt/rk3588s-orangepi-5.dts