Rockchip64 current: fixing broken patch

patch/kernel/archive/rockchip64-6.12/rk3588-0133-drm-rockchip-vop2-Improve-display-modes-handling.patch

@@ -67,17 +67,21 @@ index 111111111111..222222222222 100644
  #include <linux/component.h>
  #include <linux/delay.h>
  #include <linux/iopoll.h>
-@@ -212,6 +214,10 @@ struct vop2 {
+@@ -214,11 +214,13 @@ struct vop2 {
+ 	 */
+ 	unsigned int enable_count;
  	struct clk *hclk;
  	struct clk *aclk;
  	struct clk *pclk;
-+	// [CC:] hack to support additional display modes
+-	struct clk *pll_hdmiphy0;
 +	struct clk *hdmi0_phy_pll;
 +	/* list_head of internal clk */
 +	struct list_head clk_list_head;
  
  	/* optional internal rgb encoder */
  	struct rockchip_rgb *rgb;
+ 
+ 	/* must be put at the end of the struct */
 @@ -220,6 +226,19 @@ struct vop2 {
  	struct vop2_win win[];
  };
@@ -266,7 +270,9 @@ index 111111111111..222222222222 100644
  
  	drm_dbg(vop2->drm, "Update mode to %dx%d%s%d, type: %d for vp%d\n",
  		hdisplay, vdisplay, mode->flags & DRM_MODE_FLAG_INTERLACE ? "i" : "p",
-@@ -2044,11 +2193,38 @@ static void vop2_crtc_atomic_enable(struct drm_crtc *crtc,
+@@ -2238,15 +2240,43 @@ static void vop2_crtc_atomic_enable(struct drm_crtc *crtc,
+ 
+ 	vop2_vp_write(vp, RK3568_VP_DSP_VTOTAL_VS_END, vtotal << 16 | vsync_len);
  
  	if (mode->flags & DRM_MODE_FLAG_DBLCLK) {
  		dsp_ctrl |= RK3568_VP_DSP_CTRL__CORE_DCLK_DIV;
@@ -303,9 +309,12 @@ index 111111111111..222222222222 100644
 +		}
 +	}
 +
- 	clk_set_rate(vp->dclk, clock);
- 
- 	vop2_post_config(crtc);
++
+ 	/*
+ 	 * Switch to HDMI PHY PLL as DCLK source for display modes up
+ 	 * to 4K@60Hz, if available, otherwise keep using the system CRU.
+ 	 */
+ 	if (vop2->pll_hdmiphy0 && clock <= VOP2_MAX_DCLK_RATE) {
 @@ -2504,7 +2680,43 @@ static void vop2_crtc_atomic_flush(struct drm_crtc *crtc,
  	spin_unlock_irq(&crtc->dev->event_lock);
  }