qiurui
/
armbian-build
mirror of https://github.com/armbian/build.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

rockchip-rk3588-current: update kernel to v6.10

This commit is contained in:
Muhammed Efe Cetin 2024-08-07 17:47:32 +03:00 committed by Igor
parent 97c79d61fd
commit 8ceeb33c3b
100 changed files with 9916 additions and 21796 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

246
config/kernel/linux-rockchip-rk3588-6.8.config → config/kernel/linux-rockchip-rk3588-6.10.config
View File

File diff suppressed because it is too large Load Diff

2
config/sources/families/rockchip-rk3588.conf
View File

@ -42,7 +42,7 @@ case $BRANCH in
current)
# Branch based on a stable kernel release (will stay on the next LTS kernel release once released, 6.12? LTS)
LINUXFAMILY=rockchip-rk3588
KERNEL_MAJOR_MINOR="6.8" # Major and minor versions of this kernel.
KERNEL_MAJOR_MINOR="6.10" # Major and minor versions of this kernel.
LINUXCONFIG="linux-rockchip-rk3588-${KERNEL_MAJOR_MINOR}" # Attention: not -${BRANCH} (edge/current/legacy), but -${KERNEL_MAJOR_MINOR} thus 6.6 / 6.12 etc
# No need to set KERNELPATCHDIR, since default is: KERNELPATCHDIR='archive/rockchip-rk3588-${KERNEL_MAJOR_MINOR}'
;;

11
patch/kernel/archive/rockchip-rk3588-6.8/0000.patching_config.yaml → patch/kernel/archive/rockchip-rk3588-6.10/0000.patching_config.yaml
View File

@ -2,20 +2,22 @@ config: # This is file 'patch/kernel/rockchip-rk3588-edge/0000.patching_config.y
# PATCH NUMBERING INFO
#
# Patches should be ordered in such a way that general kernel patches are applied first, then SoC-related patches and at last board-specific patches
#
# Patch numbers in this folder are sorted by category:
#
# 000* for general patches
# 01** for GPU/HDMI related patches
# 08** for wireless patches
# 1*** for board patches
# 101* for Rock-5B, 1012* for Rock-5A and so on
# 1*** for board specific patches:
# 101* for Rock-5B, 102* for Rock-5A and so on
# Just some info stuff; not used by the patching scripts
name: rockchip-rk3588-edge
kind: kernel
type: mainline # or: vendor
branch: linux-6.8.y
last-known-good-tag: v6.8.3
branch: linux-6.10.y
last-known-good-tag: v6.10-rc2
maintainers:
- { github: rpardini, name: Ricardo Pardini, email: ricardo@pardini.net, armbian-forum: rpardini }
@ -43,4 +45,3 @@ config: # This is file 'patch/kernel/rockchip-rk3588-edge/0000.patching_config.y
- "Documentation/devicetree/bindings/arm/rockchip.yaml" # constant churn, conflicts on every bump, drop it. sorry.
do-not-commit-regexes: # Python-style regexes
- "^arch/([a-zA-Z0-9]+)/boot/dts/([a-zA-Z0-9]+)/Makefile$" # ignore DT Makefile patches, we've an auto-patcher now

69
patch/kernel/archive/rockchip-rk3588-6.10/0001-general-add-overlay-support.patch Normal file
View File

@ -0,0 +1,69 @@
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
From: Paolo Sabatino <paolo.sabatino@gmail.com>
Date: Sun, 2 Jun 2024 21:53:01 +0200
Subject: compile .scr and install overlays in right path
---
scripts/Makefile.dtbinst | 13 +++++++++-
scripts/Makefile.lib | 8 +++++-
2 files changed, 19 insertions(+), 2 deletions(-)
diff --git a/scripts/Makefile.dtbinst b/scripts/Makefile.dtbinst
index 111111111111..222222222222 100644
--- a/scripts/Makefile.dtbinst
+++ b/scripts/Makefile.dtbinst
@@ -33,7 +33,18 @@ endef
$(foreach d, $(sort $(dir $(dtbs))), $(eval $(call gen_install_rules,$(d))))
-dtbs := $(notdir $(dtbs))
+# Very convoluted way to flatten all the device tree
+# directories, but keep the "/overlay/" directory
+
+# topmost directory (ie: from rockchip/overlay/rk322x-emmc.dtbo extracts rockchip)
+topmost_dir = $(firstword $(subst /, ,$(dtbs)))
+# collect dtbs entries which starts with "$topmost_dir/overlay/", then remove "$topmost_dir"
+dtbs_overlays = $(subst $(topmost_dir)/,,$(filter $(topmost_dir)/overlay/%, $(dtbs)))
+# collect the non-overlay dtbs
+dtbs_regular = $(filter-out $(topmost_dir)/overlay/%, $(dtbs))
+# compose the dtbs variable flattening all the non-overlays entries
+# and appending the overlays entries
+dtbs := $(notdir $(dtbs_regular)) $(dtbs_overlays)
endif # CONFIG_ARCH_WANT_FLAT_DTB_INSTALL
diff --git a/scripts/Makefile.lib b/scripts/Makefile.lib
index 111111111111..222222222222 100644
--- a/scripts/Makefile.lib
+++ b/scripts/Makefile.lib
@@ -402,7 +402,7 @@ $(obj)/%.dtbo.S: $(obj)/%.dtbo FORCE
quiet_cmd_dtc = DTC $@
cmd_dtc = $(HOSTCC) -E $(dtc_cpp_flags) -x assembler-with-cpp -o $(dtc-tmp) $< ; \
- $(DTC) -o $@ -b 0 \
+ $(DTC) -@ -o $@ -b 0 \
$(addprefix -i,$(dir $<) $(DTC_INCLUDE)) $(DTC_FLAGS) \
-d $(depfile).dtc.tmp $(dtc-tmp) ; \
cat $(depfile).pre.tmp $(depfile).dtc.tmp > $(depfile)
@@ -431,12 +431,18 @@ quiet_cmd_dtb = $(quiet_cmd_dtc)
cmd_dtb = $(cmd_dtc)
endif
+quiet_cmd_scr = MKIMAGE $@
+cmd_scr = mkimage -C none -A $(ARCH) -T script -d $< $@
+
$(obj)/%.dtb: $(obj)/%.dts $(DTC) $(DT_TMP_SCHEMA) FORCE
$(call if_changed_dep,dtb)
$(obj)/%.dtbo: $(src)/%.dtso $(DTC) FORCE
$(call if_changed_dep,dtc)
+$(obj)/%.scr: $(src)/%.scr-cmd FORCE
+ $(call if_changed,scr)
+
dtc-tmp = $(subst $(comma),_,$(dot-target).dts.tmp)
# Bzip2
--
Armbian

0
patch/kernel/archive/rockchip-rk3588-6.8/0010-fix-clk-divisions.patch → patch/kernel/archive/rockchip-rk3588-6.10/0010-fix-clk-divisions.patch
View File

32
patch/kernel/archive/rockchip-rk3588-6.8/0011-irqchip-fix-its-timeout-issue.patch → patch/kernel/archive/rockchip-rk3588-6.10/0011-irqchip-fix-its-timeout-issue.patch
View File

@ -19,7 +19,7 @@ index 111111111111..222222222222 100644
u32 nr_ites;
u32 device_id;
bool shared;
@@ -2205,6 +2206,9 @@ static void gic_reset_prop_table(void *va)
@@ -2191,6 +2192,9 @@ static void gic_reset_prop_table(void *va)
static struct page *its_allocate_prop_table(gfp_t gfp_flags)
{
struct page *prop_page;
@ -29,7 +29,7 @@ index 111111111111..222222222222 100644
prop_page = alloc_pages(gfp_flags, get_order(LPI_PROPBASE_SZ));
if (!prop_page)
@@ -2329,6 +2333,7 @@ static int its_setup_baser(struct its_node *its, struct its_baser *baser,
@@ -2315,6 +2319,7 @@ static int its_setup_baser(struct its_node *its, struct its_baser *baser,
u32 alloc_pages, psz;
struct page *page;
void *base;
@ -37,7 +37,7 @@ index 111111111111..222222222222 100644
psz = baser->psz;
alloc_pages = (PAGE_ORDER_TO_SIZE(order) / psz);
@@ -2340,7 +2345,11 @@ static int its_setup_baser(struct its_node *its, struct its_baser *baser,
@@ -2326,7 +2331,11 @@ static int its_setup_baser(struct its_node *its, struct its_baser *baser,
order = get_order(GITS_BASER_PAGES_MAX * psz);
}
@ -50,7 +50,7 @@ index 111111111111..222222222222 100644
if (!page)
return -ENOMEM;
@@ -2390,6 +2399,15 @@ static int its_setup_baser(struct its_node *its, struct its_baser *baser,
@@ -2376,6 +2385,15 @@ static int its_setup_baser(struct its_node *its, struct its_baser *baser,
its_write_baser(its, baser, val);
tmp = baser->val;
@ -66,7 +66,7 @@ index 111111111111..222222222222 100644
if ((val ^ tmp) & GITS_BASER_SHAREABILITY_MASK) {
/*
* Shareability didn't stick. Just use
@@ -2979,7 +2997,9 @@ static int its_alloc_collections(struct its_node *its)
@@ -2965,7 +2983,9 @@ static int its_alloc_collections(struct its_node *its)
static struct page *its_allocate_pending_table(gfp_t gfp_flags)
{
struct page *pend_page;
@ -77,7 +77,7 @@ index 111111111111..222222222222 100644
pend_page = alloc_pages(gfp_flags | __GFP_ZERO,
get_order(LPI_PENDBASE_SZ));
if (!pend_page)
@@ -3138,6 +3158,11 @@ static void its_cpu_init_lpis(void)
@@ -3124,6 +3144,11 @@ static void its_cpu_init_lpis(void)
if (!rdists_support_shareable())
tmp &= ~GICR_PROPBASER_SHAREABILITY_MASK;
@ -89,7 +89,7 @@ index 111111111111..222222222222 100644
if ((tmp ^ val) & GICR_PROPBASER_SHAREABILITY_MASK) {
if (!(tmp & GICR_PROPBASER_SHAREABILITY_MASK)) {
/*
@@ -3165,6 +3190,11 @@ static void its_cpu_init_lpis(void)
@@ -3151,6 +3176,11 @@ static void its_cpu_init_lpis(void)
if (!rdists_support_shareable())
tmp &= ~GICR_PENDBASER_SHAREABILITY_MASK;
@ -101,7 +101,7 @@ index 111111111111..222222222222 100644
if (!(tmp & GICR_PENDBASER_SHAREABILITY_MASK)) {
/*
* The HW reports non-shareable, we must remove the
@@ -3328,7 +3358,11 @@ static bool its_alloc_table_entry(struct its_node *its,
@@ -3314,7 +3344,11 @@ static bool its_alloc_table_entry(struct its_node *its,
/* Allocate memory for 2nd level table */
if (!table[idx]) {
@ -114,7 +114,7 @@ index 111111111111..222222222222 100644
get_order(baser->psz));
if (!page)
return false;
@@ -3417,6 +3451,7 @@ static struct its_device *its_create_device(struct its_node *its, u32 dev_id,
@@ -3403,6 +3437,7 @@ static struct its_device *its_create_device(struct its_node *its, u32 dev_id,
int nr_lpis;
int nr_ites;
int sz;
@ -122,7 +122,7 @@ index 111111111111..222222222222 100644
if (!its_alloc_device_table(its, dev_id))
return NULL;
@@ -3432,7 +3467,15 @@ static struct its_device *its_create_device(struct its_node *its, u32 dev_id,
@@ -3418,7 +3453,15 @@ static struct its_device *its_create_device(struct its_node *its, u32 dev_id,
nr_ites = max(2, nvecs);
sz = nr_ites * (FIELD_GET(GITS_TYPER_ITT_ENTRY_SIZE, its->typer) + 1);
sz = max(sz, ITS_ITT_ALIGN) + ITS_ITT_ALIGN - 1;
@ -139,7 +139,7 @@ index 111111111111..222222222222 100644
if (alloc_lpis) {
lpi_map = its_lpi_alloc(nvecs, &lpi_base, &nr_lpis);
if (lpi_map)
@@ -3446,7 +3489,13 @@ static struct its_device *its_create_device(struct its_node *its, u32 dev_id,
@@ -3432,7 +3475,13 @@ static struct its_device *its_create_device(struct its_node *its, u32 dev_id,
if (!dev || !itt || !col_map || (!lpi_map && alloc_lpis)) {
kfree(dev);
@ -154,7 +154,7 @@ index 111111111111..222222222222 100644
bitmap_free(lpi_map);
kfree(col_map);
return NULL;
@@ -3456,6 +3505,7 @@ static struct its_device *its_create_device(struct its_node *its, u32 dev_id,
@@ -3442,6 +3491,7 @@ static struct its_device *its_create_device(struct its_node *its, u32 dev_id,
dev->its = its;
dev->itt = itt;
@ -162,7 +162,7 @@ index 111111111111..222222222222 100644
dev->nr_ites = nr_ites;
dev->event_map.lpi_map = lpi_map;
dev->event_map.col_map = col_map;
@@ -3483,7 +3533,13 @@ static void its_free_device(struct its_device *its_dev)
@@ -3469,7 +3519,13 @@ static void its_free_device(struct its_device *its_dev)
list_del(&its_dev->entry);
raw_spin_unlock_irqrestore(&its_dev->its->lock, flags);
kfree(its_dev->event_map.col_map);
@ -177,7 +177,7 @@ index 111111111111..222222222222 100644
kfree(its_dev);
}
@@ -5089,6 +5145,7 @@ static int __init its_probe_one(struct its_node *its)
@@ -5078,6 +5134,7 @@ static int __init its_probe_one(struct its_node *its)
struct page *page;
u32 ctlr;
int err;
@ -185,7 +185,7 @@ index 111111111111..222222222222 100644
its_enable_quirks(its);
@@ -5122,7 +5179,10 @@ static int __init its_probe_one(struct its_node *its)
@@ -5111,7 +5168,10 @@ static int __init its_probe_one(struct its_node *its)
}
}
@ -197,7 +197,7 @@ index 111111111111..222222222222 100644
get_order(ITS_CMD_QUEUE_SZ));
if (!page) {
err = -ENOMEM;
@@ -5151,6 +5211,11 @@ static int __init its_probe_one(struct its_node *its)
@@ -5140,6 +5200,11 @@ static int __init its_probe_one(struct its_node *its)
if (its->flags & ITS_FLAGS_FORCE_NON_SHAREABLE)
tmp &= ~GITS_CBASER_SHAREABILITY_MASK;

758
patch/kernel/archive/rockchip-rk3588-6.10/0022-RK3588-Add-Thermal-and-CpuFreq-Support.patch Normal file
View File

@ -0,0 +1,758 @@
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
From: Alexey Charkov <alchark@gmail.com>
Date: Mon, 6 May 2024 13:36:32 +0400
Subject: arm64: dts: rockchip: add thermal zones information on RK3588
This includes the necessary device tree data to allow thermal
monitoring on RK3588(s) using the on-chip TSADC device, along with
trip points for automatic thermal management.
Each of the CPU clusters (one for the little cores and two for
the big cores) get a passive cooling trip point at 85C, which
will trigger DVFS throttling of the respective cluster upon
reaching a high temperature condition.
All zones also have a critical trip point at 115C, which will
trigger a reset.
Signed-off-by: Alexey Charkov <alchark@gmail.com>
---
arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 147 ++++++++++
1 file changed, 147 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
index 111111111111..222222222222 100644
--- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
@@ -10,6 +10,7 @@
#include <dt-bindings/reset/rockchip,rk3588-cru.h>
#include <dt-bindings/phy/phy.h>
#include <dt-bindings/ata/ahci.h>
+#include <dt-bindings/thermal/thermal.h>
/ {
compatible = "rockchip,rk3588";
@@ -2368,6 +2369,152 @@ pwm15: pwm@febf0030 {
status = "disabled";
};
+ thermal_zones: thermal-zones {
+ /* sensor near the center of the SoC */
+ package_thermal: package-thermal {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-sensors = <&tsadc 0>;
+
+ trips {
+ package_crit: package-crit {
+ temperature = <115000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ /* sensor between A76 cores 0 and 1 */
+ bigcore0_thermal: bigcore0-thermal {
+ polling-delay-passive = <100>;
+ polling-delay = <0>;
+ thermal-sensors = <&tsadc 1>;
+
+ trips {
+ bigcore0_alert: bigcore0-alert {
+ temperature = <85000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+ bigcore0_crit: bigcore0-crit {
+ temperature = <115000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ cooling-maps {
+ map0 {
+ trip = <&bigcore0_alert>;
+ cooling-device =
+ <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu_b1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
+ };
+
+ /* sensor between A76 cores 2 and 3 */
+ bigcore2_thermal: bigcore2-thermal {
+ polling-delay-passive = <100>;
+ polling-delay = <0>;
+ thermal-sensors = <&tsadc 2>;
+
+ trips {
+ bigcore2_alert: bigcore2-alert {
+ temperature = <85000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+ bigcore2_crit: bigcore2-crit {
+ temperature = <115000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ cooling-maps {
+ map0 {
+ trip = <&bigcore2_alert>;
+ cooling-device =
+ <&cpu_b2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu_b3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
+ };
+
+ /* sensor between the four A55 cores */
+ little_core_thermal: littlecore-thermal {
+ polling-delay-passive = <100>;
+ polling-delay = <0>;
+ thermal-sensors = <&tsadc 3>;
+
+ trips {
+ littlecore_alert: littlecore-alert {
+ temperature = <85000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+ littlecore_crit: littlecore-crit {
+ temperature = <115000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ cooling-maps {
+ map0 {
+ trip = <&littlecore_alert>;
+ cooling-device =
+ <&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu_l1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu_l2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu_l3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
+ };
+
+ /* sensor near the PD_CENTER power domain */
+ center_thermal: center-thermal {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-sensors = <&tsadc 4>;
+
+ trips {
+ center_crit: center-crit {
+ temperature = <115000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ gpu_thermal: gpu-thermal {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-sensors = <&tsadc 5>;
+
+ trips {
+ gpu_crit: gpu-crit {
+ temperature = <115000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ npu_thermal: npu-thermal {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-sensors = <&tsadc 6>;
+
+ trips {
+ npu_crit: npu-crit {
+ temperature = <115000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+ };
+
tsadc: tsadc@fec00000 {
compatible = "rockchip,rk3588-tsadc";
reg = <0x0 0xfec00000 0x0 0x400>;
--
Armbian
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
From: Alexey Charkov <alchark@gmail.com>
Date: Mon, 6 May 2024 13:36:33 +0400
Subject: arm64: dts: rockchip: enable thermal management on all RK3588 boards
This enables the on-chip thermal monitoring sensor (TSADC) on all
RK3588(s) boards that don't have it enabled yet. It provides temperature
monitoring for the SoC and emergency thermal shutdowns, and is thus
important to have in place before CPU DVFS is enabled, as high CPU
operating performance points can overheat the chip quickly in the
absence of thermal management.
Signed-off-by: Alexey Charkov <alchark@gmail.com>
---
arch/arm64/boot/dts/rockchip/rk3588-armsom-sige7.dts | 4 ++++
arch/arm64/boot/dts/rockchip/rk3588-edgeble-neu6a-common.dtsi | 4 ++++
arch/arm64/boot/dts/rockchip/rk3588-evb1-v10.dts | 4 ++++
arch/arm64/boot/dts/rockchip/rk3588-ok3588-c.dts | 4 ++++
arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts | 4 ++++
arch/arm64/boot/dts/rockchip/rk3588-toybrick-x0.dts | 4 ++++
arch/arm64/boot/dts/rockchip/rk3588-turing-rk1.dtsi | 4 ++++
arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts | 4 ++++
8 files changed, 32 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk3588-armsom-sige7.dts b/arch/arm64/boot/dts/rockchip/rk3588-armsom-sige7.dts
index 111111111111..222222222222 100644
--- a/arch/arm64/boot/dts/rockchip/rk3588-armsom-sige7.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3588-armsom-sige7.dts
@@ -673,6 +673,10 @@ regulator-state-mem {
};
};
+&tsadc {
+ status = "okay";
+};
+
&u2phy0 {
status = "okay";
};
diff --git a/arch/arm64/boot/dts/rockchip/rk3588-edgeble-neu6a-common.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-edgeble-neu6a-common.dtsi
index 111111111111..222222222222 100644
--- a/arch/arm64/boot/dts/rockchip/rk3588-edgeble-neu6a-common.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3588-edgeble-neu6a-common.dtsi
@@ -466,3 +466,7 @@ regulator-state-mem {
};
};
};
+
+&tsadc {
+ status = "okay";
+};
diff --git a/arch/arm64/boot/dts/rockchip/rk3588-evb1-v10.dts b/arch/arm64/boot/dts/rockchip/rk3588-evb1-v10.dts
index 111111111111..222222222222 100644
--- a/arch/arm64/boot/dts/rockchip/rk3588-evb1-v10.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3588-evb1-v10.dts
@@ -1131,6 +1131,10 @@ &sata0 {
status = "okay";
};
+&tsadc {
+ status = "okay";
+};
+
&u2phy0 {
status = "okay";
};
diff --git a/arch/arm64/boot/dts/rockchip/rk3588-ok3588-c.dts b/arch/arm64/boot/dts/rockchip/rk3588-ok3588-c.dts
index 111111111111..222222222222 100644
--- a/arch/arm64/boot/dts/rockchip/rk3588-ok3588-c.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3588-ok3588-c.dts
@@ -376,6 +376,10 @@ &sdmmc {
status = "okay";
};
+&tsadc {
+ status = "okay";
+};
+
&u2phy2 {
status = "okay";
};
diff --git a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts
index 111111111111..222222222222 100644
--- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts
@@ -743,6 +743,10 @@ regulator-state-mem {
};
};
+&tsadc {
+ status = "okay";
+};
+
&uart2 {
pinctrl-0 = <&uart2m0_xfer>;
status = "okay";
diff --git a/arch/arm64/boot/dts/rockchip/rk3588-toybrick-x0.dts b/arch/arm64/boot/dts/rockchip/rk3588-toybrick-x0.dts
index 111111111111..222222222222 100644
--- a/arch/arm64/boot/dts/rockchip/rk3588-toybrick-x0.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3588-toybrick-x0.dts
@@ -648,6 +648,10 @@ regulator-state-mem {
};
};
+&tsadc {
+ status = "okay";
+};
+
&u2phy2 {
status = "okay";
};
diff --git a/arch/arm64/boot/dts/rockchip/rk3588-turing-rk1.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-turing-rk1.dtsi
index 111111111111..222222222222 100644
--- a/arch/arm64/boot/dts/rockchip/rk3588-turing-rk1.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3588-turing-rk1.dtsi
@@ -601,6 +601,10 @@ regulator-state-mem {
};
};
+&tsadc {
+ status = "okay";
+};
+
&uart2 {
pinctrl-0 = <&uart2m0_xfer>;
status = "okay";
diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts b/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts
index 111111111111..222222222222 100644
--- a/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts
@@ -699,6 +699,10 @@ regulator-state-mem {
};
};
+&tsadc {
+ status = "okay";
+};
+
&u2phy0 {
status = "okay";
};
--
Armbian
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
From: Alexey Charkov <alchark@gmail.com>
Date: Mon, 6 May 2024 13:36:34 +0400
Subject: arm64: dts: rockchip: add passive GPU cooling on RK3588
As the GPU support on RK3588 has been merged upstream, along with OPP
values, add a corresponding cooling map for passive cooling using the GPU.
Signed-off-by: Alexey Charkov <alchark@gmail.com>
---
arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 14 +++++++++-
1 file changed, 13 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
index 111111111111..222222222222 100644
--- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
@@ -2487,17 +2487,29 @@ center_crit: center-crit {
};
gpu_thermal: gpu-thermal {
- polling-delay-passive = <0>;
+ polling-delay-passive = <100>;
polling-delay = <0>;
thermal-sensors = <&tsadc 5>;
trips {
+ gpu_alert: gpu-alert {
+ temperature = <85000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
gpu_crit: gpu-crit {
temperature = <115000>;
hysteresis = <0>;
type = "critical";
};
};
+ cooling-maps {
+ map0 {
+ trip = <&gpu_alert>;
+ cooling-device =
+ <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
};
npu_thermal: npu-thermal {
--
Armbian
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
From: Alexey Charkov <alchark@gmail.com>
Date: Mon, 6 May 2024 13:36:36 +0400
Subject: arm64: dts: rockchip: Add CPU/memory regulator coupling for RK3588
RK3588 chips allow for their CPU cores to be powered by a different
supply vs. their corresponding memory interfaces, and two of the
boards currently upstream do that (EVB1 and QuartzPro64).
The voltage of the memory interface though has to match that of the
CPU cores that use it, which downstream kernels achieve by the means
of a custom cpufreq driver which adjusts both at the same time.
It seems that regulator coupling is a more appropriate generic
interface for it, so this patch introduces coupling to affected
device trees to ensure that memory interface voltage is also updated
whenever cpufreq switches between CPU OPPs.
Note that other boards, such as Radxa Rock 5B, define both the CPU
and memory interface regulators as aliases to the same DT node, so
this doesn't apply there.
Signed-off-by: Alexey Charkov <alchark@gmail.com>
---
arch/arm64/boot/dts/rockchip/rk3588-evb1-v10.dts | 12 ++++++++++
arch/arm64/boot/dts/rockchip/rk3588-quartzpro64.dts | 12 ++++++++++
2 files changed, 24 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk3588-evb1-v10.dts b/arch/arm64/boot/dts/rockchip/rk3588-evb1-v10.dts
index 111111111111..222222222222 100644
--- a/arch/arm64/boot/dts/rockchip/rk3588-evb1-v10.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3588-evb1-v10.dts
@@ -878,6 +878,8 @@ regulators {
vdd_cpu_big1_s0: dcdc-reg1 {
regulator-always-on;
regulator-boot-on;
+ regulator-coupled-with = <&vdd_cpu_big1_mem_s0>;
+ regulator-coupled-max-spread = <10000>;
regulator-min-microvolt = <550000>;
regulator-max-microvolt = <1050000>;
regulator-ramp-delay = <12500>;
@@ -890,6 +892,8 @@ regulator-state-mem {
vdd_cpu_big0_s0: dcdc-reg2 {
regulator-always-on;
regulator-boot-on;
+ regulator-coupled-with = <&vdd_cpu_big0_mem_s0>;
+ regulator-coupled-max-spread = <10000>;
regulator-min-microvolt = <550000>;
regulator-max-microvolt = <1050000>;
regulator-ramp-delay = <12500>;
@@ -902,6 +906,8 @@ regulator-state-mem {
vdd_cpu_lit_s0: dcdc-reg3 {
regulator-always-on;
regulator-boot-on;
+ regulator-coupled-with = <&vdd_cpu_lit_mem_s0>;
+ regulator-coupled-max-spread = <10000>;
regulator-min-microvolt = <550000>;
regulator-max-microvolt = <950000>;
regulator-ramp-delay = <12500>;
@@ -926,6 +932,8 @@ regulator-state-mem {
vdd_cpu_big1_mem_s0: dcdc-reg5 {
regulator-always-on;
regulator-boot-on;
+ regulator-coupled-with = <&vdd_cpu_big1_s0>;
+ regulator-coupled-max-spread = <10000>;
regulator-min-microvolt = <675000>;
regulator-max-microvolt = <1050000>;
regulator-ramp-delay = <12500>;
@@ -939,6 +947,8 @@ regulator-state-mem {
vdd_cpu_big0_mem_s0: dcdc-reg6 {
regulator-always-on;
regulator-boot-on;
+ regulator-coupled-with = <&vdd_cpu_big0_s0>;
+ regulator-coupled-max-spread = <10000>;
regulator-min-microvolt = <675000>;
regulator-max-microvolt = <1050000>;
regulator-ramp-delay = <12500>;
@@ -963,6 +973,8 @@ regulator-state-mem {
vdd_cpu_lit_mem_s0: dcdc-reg8 {
regulator-always-on;
regulator-boot-on;
+ regulator-coupled-with = <&vdd_cpu_lit_s0>;
+ regulator-coupled-max-spread = <10000>;
regulator-min-microvolt = <675000>;
regulator-max-microvolt = <950000>;
regulator-ramp-delay = <12500>;
diff --git a/arch/arm64/boot/dts/rockchip/rk3588-quartzpro64.dts b/arch/arm64/boot/dts/rockchip/rk3588-quartzpro64.dts
index 111111111111..222222222222 100644
--- a/arch/arm64/boot/dts/rockchip/rk3588-quartzpro64.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3588-quartzpro64.dts
@@ -833,6 +833,8 @@ vdd_cpu_big1_s0: dcdc-reg1 {
regulator-name = "vdd_cpu_big1_s0";
regulator-always-on;
regulator-boot-on;
+ regulator-coupled-with = <&vdd_cpu_big1_mem_s0>;
+ regulator-coupled-max-spread = <10000>;
regulator-min-microvolt = <550000>;
regulator-max-microvolt = <1050000>;
regulator-ramp-delay = <12500>;
@@ -846,6 +848,8 @@ vdd_cpu_big0_s0: dcdc-reg2 {
regulator-name = "vdd_cpu_big0_s0";
regulator-always-on;
regulator-boot-on;
+ regulator-coupled-with = <&vdd_cpu_big0_mem_s0>;
+ regulator-coupled-max-spread = <10000>;
regulator-min-microvolt = <550000>;
regulator-max-microvolt = <1050000>;
regulator-ramp-delay = <12500>;
@@ -859,6 +863,8 @@ vdd_cpu_lit_s0: dcdc-reg3 {
regulator-name = "vdd_cpu_lit_s0";
regulator-always-on;
regulator-boot-on;
+ regulator-coupled-with = <&vdd_cpu_lit_mem_s0>;
+ regulator-coupled-max-spread = <10000>;
regulator-min-microvolt = <550000>;
regulator-max-microvolt = <950000>;
regulator-ramp-delay = <12500>;
@@ -885,6 +891,8 @@ vdd_cpu_big1_mem_s0: dcdc-reg5 {
regulator-name = "vdd_cpu_big1_mem_s0";
regulator-always-on;
regulator-boot-on;
+ regulator-coupled-with = <&vdd_cpu_big1_s0>;
+ regulator-coupled-max-spread = <10000>;
regulator-min-microvolt = <675000>;
regulator-max-microvolt = <1050000>;
regulator-ramp-delay = <12500>;
@@ -899,6 +907,8 @@ vdd_cpu_big0_mem_s0: dcdc-reg6 {
regulator-name = "vdd_cpu_big0_mem_s0";
regulator-always-on;
regulator-boot-on;
+ regulator-coupled-with = <&vdd_cpu_big0_s0>;
+ regulator-coupled-max-spread = <10000>;
regulator-min-microvolt = <675000>;
regulator-max-microvolt = <1050000>;
regulator-ramp-delay = <12500>;
@@ -925,6 +935,8 @@ vdd_cpu_lit_mem_s0: dcdc-reg8 {
regulator-name = "vdd_cpu_lit_mem_s0";
regulator-always-on;
regulator-boot-on;
+ regulator-coupled-with = <&vdd_cpu_lit_s0>;
+ regulator-coupled-max-spread = <10000>;
regulator-min-microvolt = <675000>;
regulator-max-microvolt = <950000>;
regulator-ramp-delay = <12500>;
--
Armbian
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
From: Alexey Charkov <alchark@gmail.com>
Date: Mon, 6 May 2024 13:36:37 +0400
Subject: arm64: dts: rockchip: Add OPP data for CPU cores on RK3588
By default the CPUs on RK3588 start up in a conservative performance
mode. Add frequency and voltage mappings to the device tree to enable
dynamic scaling via cpufreq.
OPP values are adapted from Radxa's downstream kernel for Rock 5B [1],
stripping them down to the minimum frequency and voltage combinations
as expected by the generic upstream cpufreq-dt driver, and also dropping
those OPPs that don't differ in voltage but only in frequency (keeping
the top frequency OPP in each case).
Note that this patch ignores voltage scaling for the CPU memory
interface which the downstream kernel does through a custom cpufreq
driver, and which is why the downstream version has two sets of voltage
values for each OPP (the second one being meant for the memory
interface supply regulator). This is done instead via regulator
coupling between CPU and memory interface supplies on affected boards.
This has been tested on Rock 5B with u-boot 2023.11 compiled from
Collabora's integration tree [2] with binary bl31 and appears to be
stable both under active cooling and passive cooling (with throttling)
[1] https://github.com/radxa/kernel/blob/stable-5.10-rock5/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
[2] https://gitlab.collabora.com/hardware-enablement/rockchip-3588/u-boot
Signed-off-by: Alexey Charkov <alchark@gmail.com>
---
arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 122 ++++++++++
1 file changed, 122 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
index 111111111111..222222222222 100644
--- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
@@ -97,6 +97,7 @@ cpu_l0: cpu@0 {
clocks = <&scmi_clk SCMI_CLK_CPUL>;
assigned-clocks = <&scmi_clk SCMI_CLK_CPUL>;
assigned-clock-rates = <816000000>;
+ operating-points-v2 = <&cluster0_opp_table>;
cpu-idle-states = <&CPU_SLEEP>;
i-cache-size = <32768>;
i-cache-line-size = <64>;
@@ -116,6 +117,7 @@ cpu_l1: cpu@100 {
enable-method = "psci";
capacity-dmips-mhz = <530>;
clocks = <&scmi_clk SCMI_CLK_CPUL>;
+ operating-points-v2 = <&cluster0_opp_table>;
cpu-idle-states = <&CPU_SLEEP>;
i-cache-size = <32768>;
i-cache-line-size = <64>;
@@ -135,6 +137,7 @@ cpu_l2: cpu@200 {
enable-method = "psci";
capacity-dmips-mhz = <530>;
clocks = <&scmi_clk SCMI_CLK_CPUL>;
+ operating-points-v2 = <&cluster0_opp_table>;
cpu-idle-states = <&CPU_SLEEP>;
i-cache-size = <32768>;
i-cache-line-size = <64>;
@@ -154,6 +157,7 @@ cpu_l3: cpu@300 {
enable-method = "psci";
capacity-dmips-mhz = <530>;
clocks = <&scmi_clk SCMI_CLK_CPUL>;
+ operating-points-v2 = <&cluster0_opp_table>;
cpu-idle-states = <&CPU_SLEEP>;
i-cache-size = <32768>;
i-cache-line-size = <64>;
@@ -175,6 +179,7 @@ cpu_b0: cpu@400 {
clocks = <&scmi_clk SCMI_CLK_CPUB01>;
assigned-clocks = <&scmi_clk SCMI_CLK_CPUB01>;
assigned-clock-rates = <816000000>;
+ operating-points-v2 = <&cluster1_opp_table>;
cpu-idle-states = <&CPU_SLEEP>;
i-cache-size = <65536>;
i-cache-line-size = <64>;
@@ -194,6 +199,7 @@ cpu_b1: cpu@500 {
enable-method = "psci";
capacity-dmips-mhz = <1024>;
clocks = <&scmi_clk SCMI_CLK_CPUB01>;
+ operating-points-v2 = <&cluster1_opp_table>;
cpu-idle-states = <&CPU_SLEEP>;
i-cache-size = <65536>;
i-cache-line-size = <64>;
@@ -215,6 +221,7 @@ cpu_b2: cpu@600 {
clocks = <&scmi_clk SCMI_CLK_CPUB23>;
assigned-clocks = <&scmi_clk SCMI_CLK_CPUB23>;
assigned-clock-rates = <816000000>;
+ operating-points-v2 = <&cluster2_opp_table>;
cpu-idle-states = <&CPU_SLEEP>;
i-cache-size = <65536>;
i-cache-line-size = <64>;
@@ -234,6 +241,7 @@ cpu_b3: cpu@700 {
enable-method = "psci";
capacity-dmips-mhz = <1024>;
clocks = <&scmi_clk SCMI_CLK_CPUB23>;
+ operating-points-v2 = <&cluster2_opp_table>;
cpu-idle-states = <&CPU_SLEEP>;
i-cache-size = <65536>;
i-cache-line-size = <64>;
@@ -348,6 +356,120 @@ l3_cache: l3-cache {
};
};
+ cluster0_opp_table: opp-table-cluster0 {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp-1008000000 {
+ opp-hz = /bits/ 64 <1008000000>;
+ opp-microvolt = <675000 675000 950000>;
+ clock-latency-ns = <40000>;
+ };
+ opp-1200000000 {
+ opp-hz = /bits/ 64 <1200000000>;
+ opp-microvolt = <712500 712500 950000>;
+ clock-latency-ns = <40000>;
+ };
+ opp-1416000000 {
+ opp-hz = /bits/ 64 <1416000000>;
+ opp-microvolt = <762500 762500 950000>;
+ clock-latency-ns = <40000>;
+ opp-suspend;
+ };
+ opp-1608000000 {
+ opp-hz = /bits/ 64 <1608000000>;
+ opp-microvolt = <850000 850000 950000>;
+ clock-latency-ns = <40000>;
+ };
+ opp-1800000000 {
+ opp-hz = /bits/ 64 <1800000000>;
+ opp-microvolt = <950000 950000 950000>;
+ clock-latency-ns = <40000>;
+ };
+ };
+
+ cluster1_opp_table: opp-table-cluster1 {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp-1200000000 {
+ opp-hz = /bits/ 64 <1200000000>;
+ opp-microvolt = <675000 675000 1000000>;
+ clock-latency-ns = <40000>;
+ };
+ opp-1416000000 {
+ opp-hz = /bits/ 64 <1416000000>;
+ opp-microvolt = <725000 725000 1000000>;
+ clock-latency-ns = <40000>;
+ };
+ opp-1608000000 {
+ opp-hz = /bits/ 64 <1608000000>;
+ opp-microvolt = <762500 762500 1000000>;
+ clock-latency-ns = <40000>;
+ };
+ opp-1800000000 {
+ opp-hz = /bits/ 64 <1800000000>;
+ opp-microvolt = <850000 850000 1000000>;
+ clock-latency-ns = <40000>;
+ };
+ opp-2016000000 {
+ opp-hz = /bits/ 64 <2016000000>;
+ opp-microvolt = <925000 925000 1000000>;
+ clock-latency-ns = <40000>;
+ };
+ opp-2208000000 {
+ opp-hz = /bits/ 64 <2208000000>;
+ opp-microvolt = <987500 987500 1000000>;
+ clock-latency-ns = <40000>;
+ };
+ opp-2400000000 {
+ opp-hz = /bits/ 64 <2400000000>;
+ opp-microvolt = <1000000 1000000 1000000>;
+ clock-latency-ns = <40000>;
+ };
+ };
+
+ cluster2_opp_table: opp-table-cluster2 {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp-1200000000 {
+ opp-hz = /bits/ 64 <1200000000>;
+ opp-microvolt = <675000 675000 1000000>;
+ clock-latency-ns = <40000>;
+ };
+ opp-1416000000 {
+ opp-hz = /bits/ 64 <1416000000>;
+ opp-microvolt = <725000 725000 1000000>;
+ clock-latency-ns = <40000>;
+ };
+ opp-1608000000 {
+ opp-hz = /bits/ 64 <1608000000>;
+ opp-microvolt = <762500 762500 1000000>;
+ clock-latency-ns = <40000>;
+ };
+ opp-1800000000 {
+ opp-hz = /bits/ 64 <1800000000>;
+ opp-microvolt = <850000 850000 1000000>;
+ clock-latency-ns = <40000>;
+ };
+ opp-2016000000 {
+ opp-hz = /bits/ 64 <2016000000>;
+ opp-microvolt = <925000 925000 1000000>;
+ clock-latency-ns = <40000>;
+ };
+ opp-2208000000 {
+ opp-hz = /bits/ 64 <2208000000>;
+ opp-microvolt = <987500 987500 1000000>;
+ clock-latency-ns = <40000>;
+ };
+ opp-2400000000 {
+ opp-hz = /bits/ 64 <2400000000>;
+ opp-microvolt = <1000000 1000000 1000000>;
+ clock-latency-ns = <40000>;
+ };
+ };
+
display_subsystem: display-subsystem {
compatible = "rockchip,display-subsystem";
ports = <&vop_out>;
--
Armbian

17
patch/kernel/archive/rockchip-rk3588-6.8/0024-RK3588-Add-Crypto-Support.patch → patch/kernel/archive/rockchip-rk3588-6.10/0024-RK3588-Add-Crypto-Support.patch
View File

@ -102,7 +102,7 @@ diff --git a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi b/arch/arm64/boot/dts/roc
index 111111111111..222222222222 100644
--- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
@@ -1911,6 +1911,18 @@ sdhci: mmc@fe2e0000 {
@@ -1923,6 +1923,18 @@ sdhci: mmc@fe2e0000 {
status = "disabled";
};
@ -142,7 +142,7 @@ diff --git a/arch/arm64/boot/dts/rockchip/rk356x.dtsi b/arch/arm64/boot/dts/rock
index 111111111111..222222222222 100644
--- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
@@ -1071,6 +1071,18 @@ sdhci: mmc@fe310000 {
@@ -1113,6 +1113,18 @@ sdhci: mmc@fe310000 {
status = "disabled";
};
@ -195,7 +195,7 @@ index 111111111111..222222222222 100644
/* 0xFD7F0000 + 0x0A00 */
#define RK3588_PMU1CRU_RESET_OFFSET(id, reg, bit) [id] = (0x30000*4 + reg * 16 + bit)
@@ -806,45 +803,6 @@ static const int rk3588_register_offset[] = {
@@ -807,45 +804,6 @@ static const int rk3588_register_offset[] = {
RK3588_PMU1CRU_RESET_OFFSET(SRST_P_PMU0IOC, 5, 4),
RK3588_PMU1CRU_RESET_OFFSET(SRST_P_GPIO0, 5, 5),
RK3588_PMU1CRU_RESET_OFFSET(SRST_GPIO0, 5, 6),
@ -245,7 +245,7 @@ diff --git a/include/dt-bindings/reset/rockchip,rk3588-cru.h b/include/dt-bindin
index 111111111111..222222222222 100644
--- a/include/dt-bindings/reset/rockchip,rk3588-cru.h
+++ b/include/dt-bindings/reset/rockchip,rk3588-cru.h
@@ -716,39 +716,39 @@
@@ -716,40 +716,40 @@
#define SRST_P_GPIO0 627
#define SRST_GPIO0 628
@ -318,7 +318,8 @@ index 111111111111..222222222222 100644
+#define SRST_P_TRNG_CHK 53
+#define SRST_TRNG_S 54
#endif
#define SRST_A_HDMIRX_BIU 660
--
Armbian
@ -344,9 +345,9 @@ diff --git a/drivers/crypto/Kconfig b/drivers/crypto/Kconfig
index 111111111111..222222222222 100644
--- a/drivers/crypto/Kconfig
+++ b/drivers/crypto/Kconfig
@@ -661,6 +661,35 @@ config CRYPTO_DEV_ROCKCHIP_DEBUG
the number of requests per algorithm and other internal stats.
@@ -653,6 +653,35 @@ config CRYPTO_DEV_TEGRA
Select this to enable Tegra Security Engine which accelerates various
AES encryption/decryption and HASH algorithms.
+config CRYPTO_DEV_ROCKCHIP2
+ tristate "Rockchip's cryptographic offloader V2"

2
patch/kernel/archive/rockchip-rk3588-6.8/0025-RK3588-Add-HW-RNG-Support.patch → patch/kernel/archive/rockchip-rk3588-6.10/0025-RK3588-Add-HW-RNG-Support.patch
View File

@ -641,7 +641,7 @@ diff --git a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi b/arch/arm64/boot/dts/roc
index 111111111111..222222222222 100644
--- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
@@ -1923,6 +1923,16 @@ crypto: crypto@fe370000 {
@@ -1935,6 +1935,16 @@ crypto: crypto@fe370000 {
status = "okay";
};

311
patch/kernel/archive/rockchip-rk3588-6.10/0026-RK3588-Add-VPU121-H.264-Decoder-Support.patch Normal file
View File

@ -0,0 +1,311 @@
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
From: Sebastian Reichel <sebastian.reichel@collabora.com>
Date: Thu, 13 Jun 2024 15:48:42 +0200
Subject: media: dt-bindings: rk3568-vepu: Add RK3588 VEPU121
From: Emmanuel Gil Peyrot <linkmauve@linkmauve.fr>
This encoder-only device is present four times on this SoC, and should
support everything the rk3568 vepu supports (so JPEG, H.264 and VP8
encoding). No fallback compatible has been added, since the operating
systems might already support RK3568 VEPU and want to avoid registering
four of them separately considering they can be used as a cluster.
Signed-off-by: Emmanuel Gil Peyrot <linkmauve@linkmauve.fr>
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
---
Documentation/devicetree/bindings/media/rockchip,rk3568-vepu.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/media/rockchip,rk3568-vepu.yaml b/Documentation/devicetree/bindings/media/rockchip,rk3568-vepu.yaml
index 111111111111..222222222222 100644
--- a/Documentation/devicetree/bindings/media/rockchip,rk3568-vepu.yaml
+++ b/Documentation/devicetree/bindings/media/rockchip,rk3568-vepu.yaml
@@ -17,6 +17,7 @@ properties:
compatible:
enum:
- rockchip,rk3568-vepu
+ - rockchip,rk3588-vepu121
reg:
maxItems: 1
--
Armbian
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
From: Sebastian Reichel <sebastian.reichel@collabora.com>
Date: Thu, 13 Jun 2024 15:48:44 +0200
Subject: media: hantro: Disable multicore support
Avoid exposing equal Hantro video codecs to userspace. Equal video
codecs allow scheduling work between the cores. For that kernel support
is required, which does not yet exist. Until that is implemented avoid
exposing each core separately to userspace so that multicore can be
added in the future without breaking userspace ABI.
This was written with Rockchip RK3588 in mind (which has 4 Hantro H1
cores), but applies to all SoCs.
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
---
drivers/media/platform/verisilicon/hantro_drv.c | 37 ++++++++++
1 file changed, 37 insertions(+)
diff --git a/drivers/media/platform/verisilicon/hantro_drv.c b/drivers/media/platform/verisilicon/hantro_drv.c
index 111111111111..222222222222 100644
--- a/drivers/media/platform/verisilicon/hantro_drv.c
+++ b/drivers/media/platform/verisilicon/hantro_drv.c
@@ -992,6 +992,39 @@ static const struct media_device_ops hantro_m2m_media_ops = {
.req_queue = v4l2_m2m_request_queue,
};
+/*
+ * Some SoCs, like RK3588 have multiple identical Hantro cores, but the
+ * kernel is currently missing support for multi-core handling. Exposing
+ * separate devices for each core to userspace is bad, since that does
+ * not allow scheduling tasks properly (and creates ABI). With this workaround
+ * the driver will only probe for the first core and early exit for the other
+ * cores. Once the driver gains multi-core support, the same technique
+ * for detecting the main core can be used to cluster all cores together.
+ */
+static int hantro_disable_multicore(struct hantro_dev *vpu)
+{
+ const char *compatible;
+ struct device_node *node;
+ int ret;
+
+ /* Intentionally ignores the fallback strings */
+ ret = of_property_read_string(vpu->dev->of_node, "compatible", &compatible);
+ if (ret)
+ return ret;
+
+ /* first compatible node found from the root node is considered the main core */
+ node = of_find_compatible_node(NULL, NULL, compatible);
+ if (!node)
+ return -EINVAL; /* broken DT? */
+
+ if (vpu->dev->of_node != node) {
+ dev_info(vpu->dev, "missing multi-core support, ignoring this instance\n");
+ return -ENODEV;
+ }
+
+ return 0;
+}
+
static int hantro_probe(struct platform_device *pdev)
{
const struct of_device_id *match;
@@ -1011,6 +1044,10 @@ static int hantro_probe(struct platform_device *pdev)
match = of_match_node(of_hantro_match, pdev->dev.of_node);
vpu->variant = match->data;
+ ret = hantro_disable_multicore(vpu);
+ if (ret)
+ return ret;
+
/*
* Support for nxp,imx8mq-vpu is kept for backwards compatibility
* but it's deprecated. Please update your DTS file to use
--
Armbian
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
From: Sebastian Reichel <sebastian.reichel@collabora.com>
Date: Thu, 13 Jun 2024 15:48:45 +0200
Subject: media: hantro: Add RK3588 VEPU121
RK3588 handling is exactly the same as RK3568. This is not
handled using fallback compatibles to avoid exposing multiple
video devices on kernels not having the multicore disable
patch.
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
---
drivers/media/platform/verisilicon/hantro_drv.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/media/platform/verisilicon/hantro_drv.c b/drivers/media/platform/verisilicon/hantro_drv.c
index 111111111111..222222222222 100644
--- a/drivers/media/platform/verisilicon/hantro_drv.c
+++ b/drivers/media/platform/verisilicon/hantro_drv.c
@@ -722,6 +722,7 @@ static const struct of_device_id of_hantro_match[] = {
{ .compatible = "rockchip,rk3399-vpu", .data = &rk3399_vpu_variant, },
{ .compatible = "rockchip,rk3568-vepu", .data = &rk3568_vepu_variant, },
{ .compatible = "rockchip,rk3568-vpu", .data = &rk3568_vpu_variant, },
+ { .compatible = "rockchip,rk3588-vepu121", .data = &rk3568_vepu_variant, },
{ .compatible = "rockchip,rk3588-av1-vpu", .data = &rk3588_vpu981_variant, },
#endif
#ifdef CONFIG_VIDEO_HANTRO_IMX8M
--
Armbian
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
From: Sebastian Reichel <sebastian.reichel@collabora.com>
Date: Thu, 13 Jun 2024 15:48:46 +0200
Subject: arm64: dts: rockchip: Add VEPU121 to RK3588
From: Emmanuel Gil Peyrot <linkmauve@linkmauve.fr>
RK3588 has 4 Hantro G1 encoder-only cores. They are all independent IP,
but can be used as a cluster (i.e. sharing work between the cores).
These cores are called VEPU121 in the TRM. The TRM describes one more
VEPU121, but that is combined with a Hantro H1. That one will be handled
using the VPU binding instead.
Signed-off-by: Emmanuel Gil Peyrot <linkmauve@linkmauve.fr>
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
---
arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 80 ++++++++++
1 file changed, 80 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
index 111111111111..222222222222 100644
--- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
@@ -1282,6 +1282,86 @@ power-domain@RK3588_PD_SDMMC {
};
};
+ vepu121_0: video-codec@fdba0000 {
+ compatible = "rockchip,rk3588-vepu121";
+ reg = <0x0 0xfdba0000 0x0 0x800>;
+ interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&cru ACLK_JPEG_ENCODER0>, <&cru HCLK_JPEG_ENCODER0>;
+ clock-names = "aclk", "hclk";
+ iommus = <&vepu121_0_mmu>;
+ power-domains = <&power RK3588_PD_VDPU>;
+ };
+
+ vepu121_0_mmu: iommu@fdba0800 {
+ compatible = "rockchip,rk3588-iommu", "rockchip,rk3568-iommu";
+ reg = <0x0 0xfdba0800 0x0 0x40>;
+ interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&cru ACLK_JPEG_ENCODER0>, <&cru HCLK_JPEG_ENCODER0>;
+ clock-names = "aclk", "iface";
+ power-domains = <&power RK3588_PD_VDPU>;
+ #iommu-cells = <0>;
+ };
+
+ vepu121_1: video-codec@fdba4000 {
+ compatible = "rockchip,rk3588-vepu121";
+ reg = <0x0 0xfdba4000 0x0 0x800>;
+ interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&cru ACLK_JPEG_ENCODER1>, <&cru HCLK_JPEG_ENCODER1>;
+ clock-names = "aclk", "hclk";
+ iommus = <&vepu121_1_mmu>;
+ power-domains = <&power RK3588_PD_VDPU>;
+ };
+
+ vepu121_1_mmu: iommu@fdba4800 {
+ compatible = "rockchip,rk3588-iommu", "rockchip,rk3568-iommu";
+ reg = <0x0 0xfdba4800 0x0 0x40>;
+ interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&cru ACLK_JPEG_ENCODER1>, <&cru HCLK_JPEG_ENCODER1>;
+ clock-names = "aclk", "iface";
+ power-domains = <&power RK3588_PD_VDPU>;
+ #iommu-cells = <0>;
+ };
+
+ vepu121_2: video-codec@fdba8000 {
+ compatible = "rockchip,rk3588-vepu121";
+ reg = <0x0 0xfdba8000 0x0 0x800>;
+ interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&cru ACLK_JPEG_ENCODER2>, <&cru HCLK_JPEG_ENCODER2>;
+ clock-names = "aclk", "hclk";
+ iommus = <&vepu121_2_mmu>;
+ power-domains = <&power RK3588_PD_VDPU>;
+ };
+
+ vepu121_2_mmu: iommu@fdba8800 {
+ compatible = "rockchip,rk3588-iommu", "rockchip,rk3568-iommu";
+ reg = <0x0 0xfdba8800 0x0 0x40>;
+ interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&cru ACLK_JPEG_ENCODER2>, <&cru HCLK_JPEG_ENCODER2>;
+ clock-names = "aclk", "iface";
+ power-domains = <&power RK3588_PD_VDPU>;
+ #iommu-cells = <0>;
+ };
+
+ vepu121_3: video-codec@fdbac000 {
+ compatible = "rockchip,rk3588-vepu121";
+ reg = <0x0 0xfdbac000 0x0 0x800>;
+ interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&cru ACLK_JPEG_ENCODER3>, <&cru HCLK_JPEG_ENCODER3>;
+ clock-names = "aclk", "hclk";
+ iommus = <&vepu121_3_mmu>;
+ power-domains = <&power RK3588_PD_VDPU>;
+ };
+
+ vepu121_3_mmu: iommu@fdbac800 {
+ compatible = "rockchip,rk3588-iommu", "rockchip,rk3568-iommu";
+ reg = <0x0 0xfdbac800 0x0 0x40>;
+ interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&cru ACLK_JPEG_ENCODER3>, <&cru HCLK_JPEG_ENCODER3>;
+ clock-names = "aclk", "iface";
+ power-domains = <&power RK3588_PD_VDPU>;
+ #iommu-cells = <0>;
+ };
+
av1d: video-codec@fdc70000 {
compatible = "rockchip,rk3588-av1-vpu";
reg = <0x0 0xfdc70000 0x0 0x800>;
--
Armbian
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
From: Sebastian Reichel <sebastian.reichel@collabora.com>
Date: Thu, 13 Jun 2024 15:48:47 +0200
Subject: arm64: dts: rockchip: Add VPU121 support for RK3588
From: Jianfeng Liu <liujianfeng1994@gmail.com>
Enable Hantro G1 video decoder in RK3588's devicetree.
Tested with FFmpeg v4l2_request code taken from [1]
with MPEG2, H.264 and VP8 samples.
[1] https://github.com/LibreELEC/LibreELEC.tv/blob/master/packages/multimedia/ffmpeg/patches/v4l2-request/ffmpeg-001-v4l2-request.patch
Signed-off-by: Jianfeng Liu <liujianfeng1994@gmail.com>
Tested-by: Hugh Cole-Baker <sigmaris@gmail.com>
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
---
arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 22 ++++++++++
1 file changed, 22 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
index 111111111111..222222222222 100644
--- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
@@ -1282,6 +1282,28 @@ power-domain@RK3588_PD_SDMMC {
};
};
+ vpu121: video-codec@fdb50000 {
+ compatible = "rockchip,rk3588-vpu121", "rockchip,rk3399-vpu";
+ reg = <0x0 0xfdb50000 0x0 0x800>;
+ interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>;
+ interrupt-names = "vepu", "vdpu";
+ clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
+ clock-names = "aclk", "hclk";
+ iommus = <&vpu121_mmu>;
+ power-domains = <&power RK3588_PD_VDPU>;
+ };
+
+ vpu121_mmu: iommu@fdb50800 {
+ compatible = "rockchip,rk3588-iommu", "rockchip,rk3568-iommu";
+ reg = <0x0 0xfdb50800 0x0 0x40>;
+ interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>;
+ clock-names = "aclk", "iface";
+ clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
+ power-domains = <&power RK3588_PD_VDPU>;
+ #iommu-cells = <0>;
+ };
+
vepu121_0: video-codec@fdba0000 {
compatible = "rockchip,rk3588-vepu121";
reg = <0x0 0xfdba0000 0x0 0x800>;
--
Armbian

3746
patch/kernel/archive/rockchip-rk3588-6.10/0027-RK3588-Add-rkvdec2-Support-v3.patch Normal file
View File

File diff suppressed because it is too large Load Diff

43
patch/kernel/archive/rockchip-rk3588-6.10/0028-media-v4l2-core-Initialize-h264-frame_mbs_only_flag-.patch Normal file
View File

@ -0,0 +1,43 @@
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
From: amazingfate <liujianfeng1994@gmail.com>
Date: Fri, 21 Jun 2024 16:32:55 +0800
Subject: media: v4l2-core: Initialize h264 frame_mbs_only_flag as 1
---
drivers/media/v4l2-core/v4l2-ctrls-core.c | 13 ++++++++++
1 file changed, 13 insertions(+)
diff --git a/drivers/media/v4l2-core/v4l2-ctrls-core.c b/drivers/media/v4l2-core/v4l2-ctrls-core.c
index 111111111111..222222222222 100644
--- a/drivers/media/v4l2-core/v4l2-ctrls-core.c
+++ b/drivers/media/v4l2-core/v4l2-ctrls-core.c
@@ -111,6 +111,7 @@ static void std_init_compound(const struct v4l2_ctrl *ctrl, u32 idx,
struct v4l2_ctrl_vp9_frame *p_vp9_frame;
struct v4l2_ctrl_fwht_params *p_fwht_params;
struct v4l2_ctrl_h264_scaling_matrix *p_h264_scaling_matrix;
+ struct v4l2_ctrl_h264_sps *p_h264_sps;
struct v4l2_ctrl_av1_sequence *p_av1_sequence;
void *p = ptr.p + idx * ctrl->elem_size;
@@ -179,6 +180,18 @@ static void std_init_compound(const struct v4l2_ctrl *ctrl, u32 idx,
*/
memset(p_h264_scaling_matrix, 16, sizeof(*p_h264_scaling_matrix));
break;
+ case V4L2_CTRL_TYPE_H264_SPS:
+ p_h264_sps = p;
+ /*
+ * Without V4L2_H264_SPS_FLAG_FRAME_MBS_ONLY,
+ * frame_mbs_only_flag set to 0 will translate to a miniumum
+ * height of 32 (see H.264 specification 7-8). Some driver may
+ * have a minimum size lower then 32, which would fail
+ * validation with the SPS value. Set this flag, so that there
+ * is now doubling in the height, allowing a valid default.
+ */
+ p_h264_sps->flags = V4L2_H264_SPS_FLAG_FRAME_MBS_ONLY;
+ break;
}
}
--
Armbian

3745
patch/kernel/archive/rockchip-rk3588-6.10/0113-add-synopsys-designware-hdmi-rx-controller.patch Normal file
View File

File diff suppressed because it is too large Load Diff

2
patch/kernel/archive/rockchip-rk3588-6.8/0138-arm64-dts-rockchip-Add-HDMI0-bridge-to-rk3588.patch → patch/kernel/archive/rockchip-rk3588-6.10/0138-arm64-dts-rockchip-Add-HDMI0-bridge-to-rk3588.patch
View File

@ -14,7 +14,7 @@ diff --git a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi b/arch/arm64/boot/dts/roc
index 111111111111..222222222222 100644
--- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
@@ -1407,6 +1407,61 @@ i2s9_8ch: i2s@fddfc000 {
@@ -1516,6 +1516,61 @@ i2s9_8ch: i2s@fddfc000 {
status = "disabled";
};

2
patch/kernel/archive/rockchip-rk3588-6.8/0139-arm64-dts-rockchip-Enable-HDMI0-PHY-clk-provider-on-.patch → patch/kernel/archive/rockchip-rk3588-6.10/0139-arm64-dts-rockchip-Enable-HDMI0-PHY-clk-provider-on-.patch
View File

@ -13,7 +13,7 @@ diff --git a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi b/arch/arm64/boot/dts/roc
index 111111111111..222222222222 100644
--- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
@@ -2913,6 +2913,7 @@ hdptxphy_hdmi0: phy@fed60000 {
@@ -2985,6 +2985,7 @@ hdptxphy_hdmi0: phy@fed60000 {
reg = <0x0 0xfed60000 0x0 0x2000>;
clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>, <&cru PCLK_HDPTX0>;
clock-names = "ref", "apb";

0
patch/kernel/archive/rockchip-rk3588-6.8/0144-phy-phy-rockchip-samsung-hdptx-Add-FRL-EARC-support.patch → patch/kernel/archive/rockchip-rk3588-6.10/0144-phy-phy-rockchip-samsung-hdptx-Add-FRL-EARC-support.patch
View File

0
patch/kernel/archive/rockchip-rk3588-6.8/0145-phy-phy-rockchip-samsung-hdptx-Add-clock-provider.patch → patch/kernel/archive/rockchip-rk3588-6.10/0145-phy-phy-rockchip-samsung-hdptx-Add-clock-provider.patch
View File

0
patch/kernel/archive/rockchip-rk3588-6.8/0146-drm-rockchip-vop2-Improve-display-modes-handling-on-.patch → patch/kernel/archive/rockchip-rk3588-6.10/0146-drm-rockchip-vop2-Improve-display-modes-handling-on-.patch
View File

27
patch/kernel/archive/rockchip-rk3588-6.8/0147-arm64-dts-rockchip-rk3588-add-VDPU-and-RGA2-nodes.patch → patch/kernel/archive/rockchip-rk3588-6.10/0147-arm64-dts-rockchip-rk3588-add-RGA2-node.patch
View File

@ -4,38 +4,17 @@ Date: Mon, 13 May 2024 20:29:49 +0300
Subject: arm64: dts: rockchip: rk3588: add VDPU and RGA2 nodes
---
arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 32 ++++++++++
1 file changed, 32 insertions(+)
arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 11 ++++++++++
1 file changed, 11 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
index 111111111111..222222222222 100644
--- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
@@ -848,6 +848,38 @@ gpu: gpu@fb000000 {
@@ -726,6 +726,17 @@ mmu600_php: iommu@fcb00000 {
status = "disabled";
};
+ vpu: video-codec@fdb50000 {
+ compatible = "rockchip,rk3568-vpu";
+ reg = <0x0 0xfdb50000 0x0 0x800>;
+ interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>;
+ interrupt-names = "vdpu";
+ clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
+ clock-names = "aclk", "hclk";
+ iommus = <&vdpu_mmu>;
+ power-domains = <&power RK3588_PD_VDPU>;
+ };
+
+ vdpu_mmu: iommu@fdb50800 {
+ compatible = "rockchip,rk3568-iommu";
+ reg = <0x0 0xfdb50800 0x0 0x40>;
+ interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>;
+ clock-names = "aclk", "iface";
+ clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
+ power-domains = <&power RK3588_PD_VDPU>;
+ #iommu-cells = <0>;
+ };
+
+ rga: rga@fdb80000 {
+ compatible = "rockchip,rk3568-rga", "rockchip,rk3288-rga";
+ reg = <0x0 0xfdb80000 0x0 0x1000>;

8
patch/kernel/archive/rockchip-rk3588-6.8/0137-drm-bridge-synopsys-Add-initial-support-for-DW-HDMI-.patch → patch/kernel/archive/rockchip-rk3588-6.10/0161-drm-bridge-synopsys-Add-initial-support-for-DW-HDMI-Controller.patch
View File

@ -3276,7 +3276,7 @@ diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c b/drivers/gpu/drm/bridge/
index 111111111111..222222222222 100644
--- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
+++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
@@ -162,6 +162,8 @@ struct dw_hdmi {
@@ -163,6 +163,8 @@ struct dw_hdmi {
void __iomem *regs;
bool sink_is_hdmi;
bool sink_has_audio;
@ -3285,7 +3285,7 @@ index 111111111111..222222222222 100644
struct pinctrl *pinctrl;
struct pinctrl_state *default_state;
@@ -254,6 +256,25 @@ static void hdmi_mask_writeb(struct dw_hdmi *hdmi, u8 data, unsigned int reg,
@@ -255,6 +257,25 @@ static void hdmi_mask_writeb(struct dw_hdmi *hdmi, u8 data, unsigned int reg,
hdmi_modb(hdmi, data << shift, mask, reg);
}
@ -3311,7 +3311,7 @@ index 111111111111..222222222222 100644
static void dw_hdmi_i2c_init(struct dw_hdmi *hdmi)
{
hdmi_writeb(hdmi, HDMI_PHY_I2CM_INT_ADDR_DONE_POL,
@@ -2531,6 +2552,45 @@ static int dw_hdmi_connector_atomic_check(struct drm_connector *connector,
@@ -2539,6 +2560,45 @@ static int dw_hdmi_connector_atomic_check(struct drm_connector *connector,
return 0;
}
@ -3357,7 +3357,7 @@ index 111111111111..222222222222 100644
static void dw_hdmi_connector_force(struct drm_connector *connector)
{
struct dw_hdmi *hdmi = container_of(connector, struct dw_hdmi,
@@ -3682,6 +3742,35 @@ void dw_hdmi_unbind(struct dw_hdmi *hdmi)
@@ -3668,6 +3728,35 @@ void dw_hdmi_unbind(struct dw_hdmi *hdmi)
}
EXPORT_SYMBOL_GPL(dw_hdmi_unbind);

25
patch/kernel/archive/rockchip-rk3588-6.10/0162-drm-bridge-synopsys-Fix-HDMI-Controller.patch Normal file
View File

@ -0,0 +1,25 @@
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
From: ColorfulRhino <unknown-email@domain.tld>
Date: Wed, 12 Jun 2024 12:17:18 +0200
Subject: Fix HDMI controller patch at
drivers/gpu/drm/bridge/synopsys/dw-hdmi-qp.c
---
drivers/gpu/drm/bridge/synopsys/dw-hdmi-qp.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi-qp.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi-qp.c
index 111111111111..222222222222 100644
--- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi-qp.c
+++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi-qp.c
@@ -5,6 +5,7 @@
* Algea Cao <algea.cao@rock-chips.com>
*/
#include <linux/clk.h>
+#include <linux/debugfs.h>
#include <linux/delay.h>
#include <linux/dma-mapping.h>
#include <linux/err.h>
--
Armbian

190
patch/kernel/archive/rockchip-rk3588-6.10/0170-drm-rockchip-vop2-add-clocks-reset-support.patch Normal file
View File

@ -0,0 +1,190 @@
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
From: Detlev Casanova <detlev.casanova@collabora.com>
Date: Fri, 3 May 2024 14:27:39 -0400
Subject: vop2: Add clock resets support
At the end of initialization, each VP clock needs to be reset before
they can be used.
Failing to do so can put the VOP in an undefined state where the
generated HDMI signal is either lost or not matching the selected mode.
Signed-off-by: Detlev Casanova <detlev.casanova@collabora.com>
---
drivers/gpu/drm/rockchip/rockchip_drm_vop2.c | 30 ++++++++++
1 file changed, 30 insertions(+)
diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c
index 111111111111..222222222222 100644
--- a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c
+++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c
@@ -19,6 +19,7 @@
#include <linux/platform_device.h>
#include <linux/pm_runtime.h>
#include <linux/regmap.h>
+#include <linux/reset.h>
#include <linux/swab.h>
#include <drm/drm.h>
@@ -159,6 +160,7 @@ struct vop2_win {
struct vop2_video_port {
struct drm_crtc crtc;
struct vop2 *vop2;
+ struct reset_control *dclk_rst;
struct clk *dclk;
unsigned int id;
const struct vop2_video_port_data *data;
@@ -2064,6 +2066,26 @@ static struct vop2_clk *vop2_clk_get(struct vop2 *vop2, const char *name)
return NULL;
}
+static int vop2_clk_reset(struct vop2_video_port *vp)
+{
+ struct reset_control *rstc = vp->dclk_rst;
+ struct vop2 *vop2 = vp->vop2;
+ int ret;
+
+ if (!rstc)
+ return 0;
+
+ ret = reset_control_assert(rstc);
+ if (ret < 0)
+ drm_warn(vop2->drm, "failed to assert reset\n");
+ udelay(10);
+ ret = reset_control_deassert(rstc);
+ if (ret < 0)
+ drm_warn(vop2->drm, "failed to deassert reset\n");
+
+ return ret;
+}
+
static void vop2_crtc_atomic_enable(struct drm_crtc *crtc,
struct drm_atomic_state *state)
{
@@ -2233,6 +2255,8 @@ static void vop2_crtc_atomic_enable(struct drm_crtc *crtc,
vop2_vp_write(vp, RK3568_VP_DSP_CTRL, dsp_ctrl);
+ vop2_clk_reset(vp);
+
drm_crtc_vblank_on(crtc);
vop2_unlock(vop2);
@@ -2920,6 +2944,12 @@ static int vop2_create_crtcs(struct vop2 *vop2)
vp->data = vp_data;
snprintf(dclk_name, sizeof(dclk_name), "dclk_vp%d", vp->id);
+ vp->dclk_rst = devm_reset_control_get_optional(vop2->dev, dclk_name);
+ if (IS_ERR(vp->dclk_rst)) {
+ drm_err(vop2->drm, "failed to get %s reset\n", dclk_name);
+ return PTR_ERR(vp->dclk_rst);
+ }
+
vp->dclk = devm_clk_get(vop2->dev, dclk_name);
if (IS_ERR(vp->dclk)) {
drm_err(vop2->drm, "failed to get %s\n", dclk_name);
--
Armbian
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
From: Detlev Casanova <detlev.casanova@collabora.com>
Date: Fri, 3 May 2024 14:28:12 -0400
Subject: arm64: dts: rockchip: Add VOP clock resets for rk3588s
This adds the needed clock resets for all rk3588(s) based SOCs.
Signed-off-by: Detlev Casanova <detlev.casanova@collabora.com>
---
arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
index 111111111111..222222222222 100644
--- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
@@ -1429,6 +1429,14 @@ vop: vop@fdd90000 {
"pclk_vop";
iommus = <&vop_mmu>;
power-domains = <&power RK3588_PD_VOP>;
+ resets = <&cru SRST_D_VOP0>,
+ <&cru SRST_D_VOP1>,
+ <&cru SRST_D_VOP2>,
+ <&cru SRST_D_VOP3>;
+ reset-names = "dclk_vp0",
+ "dclk_vp1",
+ "dclk_vp2",
+ "dclk_vp3";
rockchip,grf = <&sys_grf>;
rockchip,vop-grf = <&vop_grf>;
rockchip,vo1-grf = <&vo1_grf>;
--
Armbian
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
From: Detlev Casanova <detlev.casanova@collabora.com>
Date: Mon, 6 May 2024 13:54:01 -0400
Subject: dt-bindings: display: vop2: Add VP clock resets
Add the documentation for VOP2 video ports reset clocks.
One reset can be set per video port.
Signed-off-by: Detlev Casanova <detlev.casanova@collabora.com>
---
Documentation/devicetree/bindings/display/rockchip/rockchip-vop2.yaml | 27 ++++++++++
1 file changed, 27 insertions(+)
diff --git a/Documentation/devicetree/bindings/display/rockchip/rockchip-vop2.yaml b/Documentation/devicetree/bindings/display/rockchip/rockchip-vop2.yaml
index 111111111111..222222222222 100644
--- a/Documentation/devicetree/bindings/display/rockchip/rockchip-vop2.yaml
+++ b/Documentation/devicetree/bindings/display/rockchip/rockchip-vop2.yaml
@@ -65,6 +65,22 @@ properties:
- const: dclk_vp3
- const: pclk_vop
+ resets:
+ minItems: 3
+ items:
+ - description: Pixel clock reset for video port 0.
+ - description: Pixel clock reset for video port 1.
+ - description: Pixel clock reset for video port 2.
+ - description: Pixel clock reset for video port 3.
+
+ reset-names:
+ minItems: 3
+ items:
+ - const: dclk_vp0
+ - const: dclk_vp1
+ - const: dclk_vp2
+ - const: dclk_vp3
+
rockchip,grf:
$ref: /schemas/types.yaml#/definitions/phandle
description:
@@ -128,6 +144,11 @@ allOf:
clock-names:
minItems: 7
+ resets:
+ minItems: 4
+ reset-names:
+ minItems: 4
+
ports:
required:
- port@0
@@ -183,6 +204,12 @@ examples:
"dclk_vp0",
"dclk_vp1",
"dclk_vp2";
+ resets = <&cru SRST_VOP0>,
+ <&cru SRST_VOP1>,
+ <&cru SRST_VOP2>;
+ reset-names = "dclk_vp0",
+ "dclk_vp1",
+ "dclk_vp2";
power-domains = <&power RK3568_PD_VO>;
iommus = <&vop_mmu>;
vop_out: ports {
--
Armbian

0
patch/kernel/archive/rockchip-rk3588-6.8/0801-wireless-add-bcm43752.patch → patch/kernel/archive/rockchip-rk3588-6.10/0801-wireless-add-bcm43752.patch
View File

0
patch/kernel/archive/rockchip-rk3588-6.8/0802-wireless-add-clk-property.patch → patch/kernel/archive/rockchip-rk3588-6.10/0802-wireless-add-clk-property.patch
View File

4
patch/kernel/archive/rockchip-rk3588-6.8/1010-arm64-dts-rock-5b-Slow-down-emmc-to-hs200-and-add-ts.patch → patch/kernel/archive/rockchip-rk3588-6.10/1010-arm64-dts-rock-5b-Slow-down-emmc-to-hs200-and-add-ts.patch
View File

@ -11,7 +11,7 @@ diff --git a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts b/arch/arm64/boot/d
index 111111111111..222222222222 100644
--- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts
@@ -359,8 +359,7 @@ &sdhci {
@@ -371,8 +371,7 @@ &sdhci {
no-sdio;
no-sd;
non-removable;
@ -21,7 +21,7 @@ index 111111111111..222222222222 100644
status = "okay";
};
@@ -400,6 +399,10 @@ &sdio {
@@ -412,6 +411,10 @@ &sdio {
status = "okay";
};

2
patch/kernel/archive/rockchip-rk3588-6.8/1011-board-rock-5b-arm64-dts-enable-spi-flash.patch → patch/kernel/archive/rockchip-rk3588-6.10/1011-board-rock-5b-arm64-dts-enable-spi-flash.patch
View File

@ -13,7 +13,7 @@ diff --git a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts b/arch/arm64/boot/d
index 111111111111..222222222222 100644
--- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts
@@ -409,6 +409,33 @@ &uart6 {
@@ -421,6 +421,33 @@ &uart6 {
status = "okay";
};

6
patch/kernel/archive/rockchip-rk3588-6.8/1012-arm64-dts-rockchip-Enable-HDMI0-on-rock-5b.patch → patch/kernel/archive/rockchip-rk3588-6.10/1012-arm64-dts-rockchip-Enable-HDMI0-on-rock-5b.patch
View File

@ -22,8 +22,8 @@ index 111111111111..222222222222 100644
#include "rk3588.dtsi"
/ {
@@ -173,6 +174,20 @@ &cpu_l3 {
cpu-supply = <&vdd_cpu_lit_s0>;
@@ -185,6 +186,20 @@ &gpu {
status = "okay";
};
+&hdmi0 {
@ -43,7 +43,7 @@ index 111111111111..222222222222 100644
&i2c0 {
pinctrl-names = "default";
pinctrl-0 = <&i2c0m2_xfer>;
@@ -821,3 +836,18 @@ &usb_host1_xhci {
@@ -837,3 +852,18 @@ &usb_host1_xhci {
&usb_host2_xhci {
status = "okay";
};

2
patch/kernel/archive/rockchip-rk3588-6.8/1014-arm64-dts-rockchip-Make-use-of-HDMI0-PHY-PLL-on-rock5b.patch → patch/kernel/archive/rockchip-rk3588-6.10/1014-arm64-dts-rockchip-Make-use-of-HDMI0-PHY-PLL-on-rock5b.patch
View File

@ -24,7 +24,7 @@ diff --git a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts b/arch/arm64/boot/d
index 111111111111..222222222222 100644
--- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts
@@ -179,6 +179,11 @@ &gpu {
@@ -186,6 +186,11 @@ &gpu {
status = "okay";
};

68
patch/kernel/archive/rockchip-rk3588-6.10/1015-board-rock5b-automatic-fan-control.patch Normal file
View File

@ -0,0 +1,68 @@
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
From: Alexey Charkov <alchark@gmail.com>
Date: Mon, 6 May 2024 13:36:35 +0400
Subject: arm64: dts: rockchip: enable automatic fan control on Rock 5B
This links the PWM fan on Radxa Rock 5B as an active cooling device
managed automatically by the thermal subsystem, with a target SoC
temperature of 65C and a minimum-spin interval from 55C to 65C to
ensure airflow when the system gets warm
Helped-by: Dragan Simic <dsimic@manjaro.org>
Reviewed-by: Dragan Simic <dsimic@manjaro.org>
Signed-off-by: Alexey Charkov <alchark@gmail.com>
---
arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts | 30 +++++++++-
1 file changed, 29 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts
index 111111111111..222222222222 100644
--- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts
@@ -53,7 +53,7 @@ led_rgb_b {
fan: pwm-fan {
compatible = "pwm-fan";
- cooling-levels = <0 95 145 195 255>;
+ cooling-levels = <0 120 150 180 210 240 255>;
fan-supply = <&vcc5v0_sys>;
pwms = <&pwm1 0 50000 0>;
#cooling-cells = <2>;
@@ -299,6 +299,34 @@ i2s0_8ch_p0_0: endpoint {
};
};
+&package_thermal {
+ polling-delay = <1000>;
+
+ trips {
+ package_fan0: package-fan0 {
+ temperature = <55000>;
+ hysteresis = <2000>;
+ type = "active";
+ };
+ package_fan1: package-fan1 {
+ temperature = <65000>;
+ hysteresis = <2000>;
+ type = "active";
+ };
+ };
+
+ cooling-maps {
+ map1 {
+ trip = <&package_fan0>;
+ cooling-device = <&fan THERMAL_NO_LIMIT 1>;
+ };
+ map2 {
+ trip = <&package_fan1>;
+ cooling-device = <&fan 2 THERMAL_NO_LIMIT>;
+ };
+ };
+};
+
&pcie2x1l0 {
pinctrl-names = "default";
pinctrl-0 = <&pcie2_0_rst>;
--
Armbian

2
patch/kernel/archive/rockchip-rk3588-6.8/1020-Add-HDMI-and-VOP2-to-Rock-5A.patch → patch/kernel/archive/rockchip-rk3588-6.10/1020-Add-HDMI-and-VOP2-to-Rock-5A.patch
View File

@ -19,7 +19,7 @@ index 111111111111..222222222222 100644
#include "rk3588s.dtsi"
/ {
@@ -760,3 +761,32 @@ &usb_host1_ohci {
@@ -765,3 +766,32 @@ &usb_host1_ohci {
&usb_host2_xhci {
status = "okay";
};

2
patch/kernel/archive/rockchip-rk3588-6.8/1021-arch-arm64-dts-enable-gpu-node-for-rock-5a.patch → patch/kernel/archive/rockchip-rk3588-6.10/1021-arch-arm64-dts-enable-gpu-node-for-rock-5a.patch
View File

@ -23,7 +23,7 @@ index 111111111111..222222222222 100644
&mdio1 {
rgmii_phy1: ethernet-phy@1 {
/* RTL8211F */
@@ -433,6 +438,7 @@ rk806_dvs3_null: dvs3-null-pins {
@@ -434,6 +439,7 @@ rk806_dvs3_null: dvs3-null-pins {
regulators {
vdd_gpu_s0: vdd_gpu_mem_s0: dcdc-reg1 {
regulator-name = "vdd_gpu_s0";

39
patch/kernel/archive/rockchip-rk3588-6.8/1021-arm64-dts-Add-missing-nodes-to-Orange-Pi-5-Plus.patch → patch/kernel/archive/rockchip-rk3588-6.10/1021-arm64-dts-Add-missing-nodes-to-Orange-Pi-5-Plus.patch
View File

@ -4,8 +4,8 @@ Date: Thu, 16 Nov 2023 18:15:09 +0300
Subject: arm64: dts: Add missing nodes to Orange Pi 5 Plus
---
arch/arm64/boot/dts/rockchip/rk3588-orangepi-5-plus.dts | 182 +++++++++-
1 file changed, 181 insertions(+), 1 deletion(-)
arch/arm64/boot/dts/rockchip/rk3588-orangepi-5-plus.dts | 203 +++++++++-
1 file changed, 202 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/rockchip/rk3588-orangepi-5-plus.dts b/arch/arm64/boot/dts/rockchip/rk3588-orangepi-5-plus.dts
index 111111111111..222222222222 100644
@ -113,8 +113,16 @@ index 111111111111..222222222222 100644
};
&i2c7 {
@@ -385,7 +459,7 @@ &pcie3x4 {
@@ -383,9 +457,15 @@ &pcie3x4 {
};
&pinctrl {
+ hdmirx {
+ hdmirx_5v_detection: hdmirx-5v-detection {
+ rockchip,pins = <1 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
hym8563 {
hym8563_int: hym8563-int {
- rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
@ -122,7 +130,7 @@ index 111111111111..222222222222 100644
};
};
@@ -408,6 +482,14 @@ hp_detect: hp-detect {
@@ -408,6 +488,14 @@ hp_detect: hp-detect {
};
usb {
@ -137,7 +145,7 @@ index 111111111111..222222222222 100644
vcc5v0_usb20_en: vcc5v0-usb20-en {
rockchip,pins = <3 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>;
};
@@ -803,6 +885,22 @@ &tsadc {
@@ -803,6 +891,22 @@ &tsadc {
status = "okay";
};
@ -160,7 +168,7 @@ index 111111111111..222222222222 100644
&u2phy2 {
status = "okay";
};
@@ -831,6 +929,35 @@ &uart9 {
@@ -831,6 +935,35 @@ &uart9 {
status = "okay";
};
@ -196,7 +204,7 @@ index 111111111111..222222222222 100644
&usb_host0_ehci {
status = "okay";
};
@@ -839,6 +966,20 @@ &usb_host0_ohci {
@@ -839,6 +972,20 @@ &usb_host0_ohci {
status = "okay";
};
@ -217,7 +225,7 @@ index 111111111111..222222222222 100644
&usb_host1_ehci {
status = "okay";
};
@@ -846,3 +987,42 @@ &usb_host1_ehci {
@@ -846,3 +993,57 @@ &usb_host1_ehci {
&usb_host1_ohci {
status = "okay";
};
@ -234,12 +242,27 @@ index 111111111111..222222222222 100644
+
+&hdmi0 {
+ status = "okay";
+ enable-gpios = <&gpio4 RK_PB1 GPIO_ACTIVE_HIGH>;
+ cec-enable = "true";
+};
+
+&hdptxphy_hdmi0 {
+ status = "okay";
+};
+
+&hdmi_receiver {
+ status = "okay";
+ hpd-gpios = <&gpio1 RK_PC6 GPIO_ACTIVE_LOW>;
+ pinctrl-0 = <&hdmim1_rx_cec &hdmim1_rx_hpdin &hdmim1_rx_scl
+ &hdmim1_rx_sda &hdmirx_5v_detection>;
+ pinctrl-names = "default";
+};
+
+&hdmi_receiver_cma {
+ status = "okay";
+};
+
+
+&vop_mmu {
+ status = "okay";
+};

0
patch/kernel/archive/rockchip-rk3588-6.8/1023-arm64-dts-rockchip-add-PCIe-for-M.2-E-Key-to-rock-5a.patch → patch/kernel/archive/rockchip-rk3588-6.10/1023-arm64-dts-rockchip-add-PCIe-for-M.2-E-Key-to-rock-5a.patch
View File

64
patch/kernel/archive/rockchip-rk3588-6.10/1031-arm64-dts-rockchip-Add-HDMI-support-to-ArmSoM-Sige7.patch Normal file
View File

@ -0,0 +1,64 @@
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
From: Jianfeng Liu <liujianfeng1994@gmail.com>
Date: Thu, 6 Jun 2024 23:28:01 +0800
Subject: arm64: dts: rockchip: Add HDMI support to ArmSoM Sige7
---
arch/arm64/boot/dts/rockchip/rk3588-armsom-sige7.dts | 30 ++++++++++
1 file changed, 30 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk3588-armsom-sige7.dts b/arch/arm64/boot/dts/rockchip/rk3588-armsom-sige7.dts
index 111111111111..222222222222 100644
--- a/arch/arm64/boot/dts/rockchip/rk3588-armsom-sige7.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3588-armsom-sige7.dts
@@ -4,6 +4,7 @@
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/leds/common.h>
+#include <dt-bindings/soc/rockchip,vop2.h>
#include "rk3588.dtsi"
/ {
@@ -164,6 +165,20 @@ &gpu {
status = "okay";
};
+&hdmi0 {
+ status = "okay";
+};
+
+&hdmi0_in {
+ hdmi0_in_vp0: endpoint {
+ remote-endpoint = <&vp0_out_hdmi0>;
+ };
+};
+
+&hdptxphy_hdmi0 {
+ status = "okay";
+};
+
&i2c0 {
pinctrl-names = "default";
pinctrl-0 = <&i2c0m2_xfer>;
@@ -723,3 +738,18 @@ &usb_host1_xhci {
dr_mode = "host";
status = "okay";
};
+
+&vop {
+ status = "okay";
+};
+
+&vop_mmu {
+ status = "okay";
+};
+
+&vp0 {
+ vp0_out_hdmi0: endpoint@ROCKCHIP_VOP2_EP_HDMI0 {
+ reg = <ROCKCHIP_VOP2_EP_HDMI0>;
+ remote-endpoint = <&hdmi0_in_vp0>;
+ };
+};
--
Armbian

39
patch/kernel/archive/rockchip-rk3588-6.10/1032-arm64-dts-rockchip-Add-ap6275p-wireless-support-to-A.patch Normal file
View File

@ -0,0 +1,39 @@
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
From: Jianfeng Liu <liujianfeng1994@gmail.com>
Date: Thu, 6 Jun 2024 23:29:39 +0800
Subject: arm64: dts: rockchip: Add ap6275p wireless support to ArmSoM Sige7
---
arch/arm64/boot/dts/rockchip/rk3588-armsom-sige7.dts | 16 ++++++++++
1 file changed, 16 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk3588-armsom-sige7.dts b/arch/arm64/boot/dts/rockchip/rk3588-armsom-sige7.dts
index 111111111111..222222222222 100644
--- a/arch/arm64/boot/dts/rockchip/rk3588-armsom-sige7.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3588-armsom-sige7.dts
@@ -283,6 +283,22 @@ &pcie2x1l0 {
&pcie2x1l1 {
reset-gpios = <&gpio3 RK_PD4 GPIO_ACTIVE_HIGH>;
status = "okay";
+
+ pcie@0,0 {
+ reg = <0x300000 0 0 0 0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges;
+ device_type = "pci";
+ bus-range = <0x30 0x3f>;
+
+ wifi: wifi@0,0 {
+ compatible = "pci14e4,449d";
+ reg = <0x310000 0 0 0 0>;
+ clocks = <&hym8563>;
+ clock-names = "32k";
+ };
+ };
};
/* phy0 - left ethernet port */
--
Armbian

325
patch/kernel/archive/rockchip-rk3588-6.10/1040-board-khadas-edge2-add-nodes.patch Normal file
View File

@ -0,0 +1,325 @@
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
From: Muhammed Efe Cetin <efectn@protonmail.com>
Date: Mon, 12 Feb 2024 17:35:13 +0300
Subject: arm64: dts: rockchip: Add USB-C to Khadas Edge 2
Khadas Edge 2 has 2x Type-C port. One just supports PD and
controlled by MCU. The other one supports PD, DP Alt mode and DRD. This
commit adds support for DRD.
Signed-off-by: Muhammed Efe Cetin <efectn@protonmail.com>
---
arch/arm64/boot/dts/rockchip/rk3588s-khadas-edge2.dts | 120 ++++++++++
1 file changed, 120 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-khadas-edge2.dts b/arch/arm64/boot/dts/rockchip/rk3588s-khadas-edge2.dts
index 111111111111..222222222222 100644
--- a/arch/arm64/boot/dts/rockchip/rk3588s-khadas-edge2.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3588s-khadas-edge2.dts
@@ -6,6 +6,7 @@
#include <dt-bindings/input/input.h>
#include <dt-bindings/pinctrl/rockchip.h>
#include <dt-bindings/leds/common.h>
+#include <dt-bindings/usb/pd.h>
#include "rk3588s.dtsi"
/ {
@@ -76,6 +77,18 @@ blue_led: led-2 {
};
};
+ vbus5v0_typec: vbus5v0-typec-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vbus5v0_typec";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ enable-active-high;
+ gpio = <&gpio3 RK_PA4 GPIO_ACTIVE_HIGH>;
+ vin-supply = <&vcc5v0_sys>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&typec5v_pwren>;
+ };
+
vcc3v3_pcie_wl: vcc3v3-pcie-wl-regulator {
compatible = "regulator-fixed";
enable-active-high;
@@ -224,6 +237,56 @@ regulator-state-mem {
&i2c2 {
status = "okay";
+ usbc0: usb-typec@22 {
+ compatible = "fcs,fusb302";
+ reg = <0x22>;
+ interrupt-parent = <&gpio1>;
+ interrupts = <RK_PB5 IRQ_TYPE_LEVEL_LOW>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&usbc0_int>;
+ vbus-supply = <&vbus5v0_typec>;
+ status = "okay";
+
+ usb_con: connector {
+ compatible = "usb-c-connector";
+ label = "USB-C";
+ data-role = "dual";
+ power-role = "dual";
+ try-power-role = "source";
+ op-sink-microwatt = <1000000>;
+ sink-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)
+ PDO_FIXED(9000, 3000, PDO_FIXED_USB_COMM)
+ PDO_FIXED(12000, 3000, PDO_FIXED_USB_COMM)>;
+ source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ usbc0_orien_sw: endpoint {
+ remote-endpoint = <&usbdp_phy0_orientation_switch>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ usbc0_role_sw: endpoint {
+ remote-endpoint = <&dwc3_0_role_switch>;
+ };
+ };
+
+ port@2 {
+ reg = <2>;
+ dp_altmode_mux: endpoint {
+ remote-endpoint = <&usbdp_phy0_dp_altmode_mux>;
+ };
+ };
+ };
+ };
+ };
+
hym8563: rtc@51 {
compatible = "haoyu,hym8563";
reg = <0x51>;
@@ -256,6 +319,16 @@ vcc5v0_host_en: vcc5v0-host-en {
};
};
+ usb-typec {
+ usbc0_int: usbc0-int {
+ rockchip,pins = <1 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+
+ typec5v_pwren: typec5v-pwren {
+ rockchip,pins = <3 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
ir-receiver {
ir_receiver_pin: ir-receiver-pin {
rockchip,pins = <1 RK_PA7 RK_FUNC_GPIO &pcfg_pull_none>;
@@ -681,6 +754,15 @@ &uart9 {
status = "okay";
};
+&u2phy0 {
+ status = "okay";
+};
+
+&u2phy0_otg {
+ status = "okay";
+};
+
+
&u2phy2 {
status = "okay";
};
@@ -707,6 +789,44 @@ &usb_host0_ohci {
status = "okay";
};
+&usbdp_phy0 {
+ orientation-switch;
+ mode-switch;
+ svid = <0xff01>;
+ sbu1-dc-gpios = <&gpio4 RK_PA0 GPIO_ACTIVE_HIGH>;
+ sbu2-dc-gpios = <&gpio4 RK_PA1 GPIO_ACTIVE_HIGH>;
+ status = "okay";
+
+ port {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ usbdp_phy0_orientation_switch: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&usbc0_orien_sw>;
+ };
+
+ usbdp_phy0_dp_altmode_mux: endpoint@1 {
+ reg = <1>;
+ remote-endpoint = <&dp_altmode_mux>;
+ };
+ };
+};
+
+&usb_host0_xhci {
+ usb-role-switch;
+ status = "okay";
+
+ port {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ dwc3_0_role_switch: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&usbc0_role_sw>;
+ };
+ };
+};
+
&usb_host1_ehci {
status = "okay";
};
--
Armbian
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
From: Muhammed Efe Cetin <efectn@protonmail.com>
Date: Mon, 12 Feb 2024 17:35:13 +0300
Subject: arm64: dts: rockchip: Add bluetooth rfkill to Khadas Edge 2
---
arch/arm64/boot/dts/rockchip/rk3588s-khadas-edge2.dts | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-khadas-edge2.dts b/arch/arm64/boot/dts/rockchip/rk3588s-khadas-edge2.dts
index 111111111111..222222222222 100644
--- a/arch/arm64/boot/dts/rockchip/rk3588s-khadas-edge2.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3588s-khadas-edge2.dts
@@ -116,6 +116,15 @@ vcc5v0_host: vcc5v0-host-regulator {
vin-supply = <&vcc5v0_sys>;
};
+ bluetooth-rfkill {
+ compatible = "rfkill-gpio";
+ label = "rfkill-bluetooth";
+ radio-type = "bluetooth";
+ shutdown-gpios = <&gpio0 RK_PD4 GPIO_ACTIVE_LOW>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&bt_reset_pin>;
+ };
+
vcc5v0_sys: vcc5v0-sys-regulator {
compatible = "regulator-fixed";
regulator-name = "vcc5v0_sys";
--
Armbian
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
From: Muhammed Efe Cetin <efectn@protonmail.com>
Date: Mon, 19 Feb 2024 23:32:11 +0300
Subject: arm64: dts: rockchip: Add HDMI & VOP2 to Khadas Edge 2
---
arch/arm64/boot/dts/rockchip/rk3588s-khadas-edge2.dts | 36 ++++++++++
1 file changed, 36 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-khadas-edge2.dts b/arch/arm64/boot/dts/rockchip/rk3588s-khadas-edge2.dts
index 111111111111..222222222222 100644
--- a/arch/arm64/boot/dts/rockchip/rk3588s-khadas-edge2.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3588s-khadas-edge2.dts
@@ -7,6 +7,7 @@
#include <dt-bindings/pinctrl/rockchip.h>
#include <dt-bindings/leds/common.h>
#include <dt-bindings/usb/pd.h>
+#include <dt-bindings/soc/rockchip,vop2.h>
#include "rk3588s.dtsi"
/ {
@@ -823,6 +824,7 @@ usbdp_phy0_dp_altmode_mux: endpoint@1 {
};
&usb_host0_xhci {
+ dr-mode = "otg";
usb-role-switch;
status = "okay";
@@ -847,3 +849,37 @@ &usb_host1_ohci {
&usb_host2_xhci {
status = "okay";
};
+
+&hdmi0 {
+ status = "okay";
+};
+
+&hdptxphy_hdmi0 {
+ status = "okay";
+};
+
+&display_subsystem {
+ clocks = <&hdptxphy_hdmi0>;
+ clock-names = "hdmi0_phy_pll";
+};
+
+&vop_mmu {
+ status = "okay";
+};
+
+&hdmi0_in {
+ hdmi0_in_vp0: endpoint {
+ remote-endpoint = <&vp0_out_hdmi0>;
+ };
+};
+
+&vop {
+ status = "okay";
+};
+
+&vp0 {
+ vp0_out_hdmi0: endpoint@ROCKCHIP_VOP2_EP_HDMI0 {
+ reg = <ROCKCHIP_VOP2_EP_HDMI0>;
+ remote-endpoint = <&hdmi0_in_vp0>;
+ };
+};
--
Armbian
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
From: Muhammed Efe Cetin <efectn@protonmail.com>
Date: Sat, 2 Mar 2024 19:13:59 +0300
Subject: arm64: dts: rockchip: Add AP6275P wireless support to Khadas Edge 2
---
arch/arm64/boot/dts/rockchip/rk3588s-khadas-edge2.dts | 17 ++++++++++
1 file changed, 17 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-khadas-edge2.dts b/arch/arm64/boot/dts/rockchip/rk3588s-khadas-edge2.dts
index 111111111111..222222222222 100644
--- a/arch/arm64/boot/dts/rockchip/rk3588s-khadas-edge2.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3588s-khadas-edge2.dts
@@ -366,6 +366,23 @@ &pcie2x1l2 {
reset-gpios = <&gpio3 RK_PD1 GPIO_ACTIVE_HIGH>;
vpcie3v3-supply = <&vcc3v3_pcie_wl>;
status = "okay";
+
+ pcie@0,0 {
+ reg = <0x400000 0 0 0 0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges;
+ device_type = "pci";
+ bus-range = <0x40 0x4f>;
+
+ wifi: wifi@0,0 {
+ compatible = "pci14e4,449d";
+ reg = <0x410000 0 0 0 0>;
+ clocks = <&hym8563>;
+ clock-names = "32k";
+ };
+ };
+
};
&pwm11 {
--
Armbian

6
patch/kernel/archive/rockchip-rk3588-6.8/1041-board-khadas-edge2-mcu.patch → patch/kernel/archive/rockchip-rk3588-6.10/1041-board-khadas-edge2-mcu.patch
View File

@ -31,7 +31,7 @@ index 111111111111..222222222222 100644
+ .max_register = KHADAS_MCU_SYS_RST_REG,
.volatile_reg = khadas_mcu_reg_volatile,
.writeable_reg = khadas_mcu_reg_writeable,
.cache_type = REGCACHE_RBTREE,
.cache_type = REGCACHE_MAPLE,
};
static struct mfd_cell khadas_mcu_fan_cells[] = {
@ -343,7 +343,7 @@ diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-khadas-edge2.dts b/arch/arm64/
index 111111111111..222222222222 100644
--- a/arch/arm64/boot/dts/rockchip/rk3588s-khadas-edge2.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3588s-khadas-edge2.dts
@@ -307,6 +307,13 @@ hym8563: rtc@51 {
@@ -304,6 +304,13 @@ hym8563: rtc@51 {
clock-output-names = "hym8563";
wakeup-source;
};
@ -373,7 +373,7 @@ diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-khadas-edge2.dts b/arch/arm64/
index 111111111111..222222222222 100644
--- a/arch/arm64/boot/dts/rockchip/rk3588s-khadas-edge2.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3588s-khadas-edge2.dts
@@ -316,6 +316,62 @@ khadas_mcu: system-controller@18 {
@@ -313,6 +313,62 @@ khadas_mcu: system-controller@18 {
};
};

18
patch/kernel/archive/rockchip-rk3588-6.8/1016-arm64-dts-rockchip-Add-NanoPC-T6-SPI-Flash.patch → patch/kernel/archive/rockchip-rk3588-6.10/1051-arm64-dts-rockchip-Add-NanoPC-T6-SPI-Flash.patch
View File

@ -9,17 +9,10 @@ Signed-off-by: Ricardo Pardini <ricardo@pardini.net>
1 file changed, 14 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dts b/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dts
index 997b516c2533c..5ef2cc5fe0679 100644
index 111111111111..222222222222 100644
--- a/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dts
@@ -541,20 +541,34 @@ &sdmmc {
cap-sd-highspeed;
disable-wp;
no-mmc;
no-sdio;
sd-uhs-sdr104;
vmmc-supply = <&vcc_3v3_s3>;
vqmmc-supply = <&vccio_sd_s0>;
@@ -576,6 +576,20 @@ &sdmmc {
status = "okay";
};
@ -40,13 +33,6 @@ index 997b516c2533c..5ef2cc5fe0679 100644
&spi2 {
status = "okay";
assigned-clocks = <&cru CLK_SPI2>;
assigned-clock-rates = <200000000>;
pinctrl-names = "default";
pinctrl-0 = <&spi2m2_cs0 &spi2m2_pins>;
num-cs = <1>;
pmic@0 {
compatible = "rockchip,rk806";
--
Armbian

0
patch/kernel/archive/rockchip-rk3588-6.8/dt/rk3588-bananapi-m7.dts → patch/kernel/archive/rockchip-rk3588-6.10/dt/rk3588-bananapi-m7.dts
View File

0
patch/kernel/archive/rockchip-rk3588-6.8/dt/rk3588-hinlink-h88k.dts → patch/kernel/archive/rockchip-rk3588-6.10/dt/rk3588-hinlink-h88k.dts
View File

0
patch/kernel/archive/rockchip-rk3588-6.8/dt/rk3588-mixtile-blade3.dts → patch/kernel/archive/rockchip-rk3588-6.10/dt/rk3588-mixtile-blade3.dts
View File

0
patch/kernel/archive/rockchip-rk3588-6.8/dt/rk3588-nanopc-cm3588-nas.dts → patch/kernel/archive/rockchip-rk3588-6.10/dt/rk3588-nanopc-cm3588-nas.dts
View File

0
patch/kernel/archive/rockchip-rk3588-6.8/dt/rk3588s-nanopi-r6c.dts → patch/kernel/archive/rockchip-rk3588-6.10/dt/rk3588s-nanopi-r6c.dts
View File

0
patch/kernel/archive/rockchip-rk3588-6.8/dt/rk3588s-nanopi-r6s.dts → patch/kernel/archive/rockchip-rk3588-6.10/dt/rk3588s-nanopi-r6s.dts
View File

523
patch/kernel/archive/rockchip-rk3588-6.8/dt/rk3588-armsom-sige7.dts → patch/kernel/archive/rockchip-rk3588-6.10/dt/rk3588s-orangepi-5.dts
View File

@ -4,95 +4,71 @@
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/leds/common.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/pinctrl/rockchip.h>
#include <dt-bindings/usb/pd.h>
#include <dt-bindings/soc/rockchip,vop2.h>
#include "rk3588.dtsi"
#include "rk3588s.dtsi"
/ {
model = "ArmSoM Sige7";
compatible = "armsom,sige7", "rockchip,rk3588";
model = "Xunlong Orange Pi 5";
compatible = "xunlong,orangepi-5", "rockchip,rk3588s";
aliases {
mmc0 = &sdhci;
mmc1 = &sdmmc;
ethernet0 = &gmac1;
mmc0 = &sdmmc;
};
chosen {
stdout-path = "serial2:1500000n8";
};
analog-sound {
compatible = "audio-graph-card";
dais = <&i2s0_8ch_p0>;
label = "rk3588-es8316";
hp-det-gpio = <&gpio1 RK_PD5 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&hp_detect>;
routing = "MIC2", "Mic Jack",
"Headphones", "HPOL",
"Headphones", "HPOR";
widgets = "Microphone", "Mic Jack",
"Headphone", "Headphones";
adc-keys {
compatible = "adc-keys";
io-channels = <&saradc 1>;
io-channel-names = "buttons";
keyup-threshold-microvolt = <1800000>;
poll-interval = <100>;
button-recovery {
label = "Recovery";
linux,code = <KEY_VENDOR>;
press-threshold-microvolt = <1800>;
};
};
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 = <&led_rgb_g>;
pinctrl-0 = <&leds_gpio>;
led_green: led-0 {
color = <LED_COLOR_ID_GREEN>;
function = LED_FUNCTION_STATUS;
gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>;
led-1 {
gpios = <&gpio1 RK_PA2 GPIO_ACTIVE_HIGH>;
label = "status_led";
linux,default-trigger = "heartbeat";
};
};
led_red: led-1 {
color = <LED_COLOR_ID_RED>;
function = LED_FUNCTION_STATUS;
gpios = <&gpio4 RK_PC5 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "none";
hdmi0-con {
compatible = "hdmi-connector";
type = "a";
port {
hdmi0_con_in: endpoint {
remote-endpoint = <&hdmi0_out_con>;
};
};
};
fan: pwm-fan {
compatible = "pwm-fan";
cooling-levels = <0 95 145 195 255>;
fan-supply = <&vcc5v0_sys>;
pwms = <&pwm1 0 50000 0>;
#cooling-cells = <2>;
};
vcc3v3_pcie2x1l2: vcc3v3-pcie2x1l2-regulator {
compatible = "regulator-fixed";
regulator-name = "vcc3v3_pcie2x1l2";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
startup-delay-us = <5000>;
vin-supply = <&vcc_3v3_s3>;
};
vcc3v3_pcie30: vcc3v3-pcie30-regulator {
vbus_typec: vbus-typec-regulator {
compatible = "regulator-fixed";
enable-active-high;
gpios = <&gpio1 RK_PA4 GPIO_ACTIVE_HIGH>;
regulator-name = "vcc3v3_pcie30";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
startup-delay-us = <5000>;
vin-supply = <&vcc5v0_sys>;
};
vcc5v0_host: vcc5v0-host-regulator {
compatible = "regulator-fixed";
regulator-name = "vcc5v0_host";
regulator-boot-on;
regulator-always-on;
gpio = <&gpio3 RK_PC0 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&typec5v_pwren>;
regulator-name = "vbus_typec";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
enable-active-high;
gpio = <&gpio4 RK_PB0 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&vcc5v0_host_en>;
vin-supply = <&vcc5v0_sys>;
};
@ -105,13 +81,26 @@
regulator-max-microvolt = <5000000>;
};
vcc_1v1_nldo_s3: vcc-1v1-nldo-s3-regulator {
vcc_3v3_sd_s0: vcc-3v3-sd-s0-regulator {
compatible = "regulator-fixed";
regulator-name = "vcc_1v1_nldo_s3";
regulator-always-on;
enable-active-low;
gpios = <&gpio4 RK_PB5 GPIO_ACTIVE_LOW>;
regulator-name = "vcc_3v3_sd_s0";
regulator-boot-on;
regulator-min-microvolt = <1100000>;
regulator-max-microvolt = <1100000>;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
vin-supply = <&vcc_3v3_s3>;
};
vcc3v3_pcie20: vcc3v3-pcie20-regulator {
compatible = "regulator-fixed";
enable-active-high;
gpios = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>;
regulator-name = "vcc3v3_pcie20";
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
startup-delay-us = <50000>;
vin-supply = <&vcc5v0_sys>;
};
};
@ -120,10 +109,6 @@
status = "okay";
};
&combphy1_ps {
status = "okay";
};
&combphy2_psu {
status = "okay";
};
@ -160,25 +145,25 @@
cpu-supply = <&vdd_cpu_lit_s0>;
};
&gmac1 {
clock_in_out = "output";
phy-handle = <&rgmii_phy1>;
phy-mode = "rgmii-rxid";
pinctrl-0 = <&gmac1_miim
&gmac1_tx_bus2
&gmac1_rx_bus2
&gmac1_rgmii_clk
&gmac1_rgmii_bus>;
pinctrl-names = "default";
tx_delay = <0x42>;
status = "okay";
};
&gpu {
mali-supply = <&vdd_gpu_s0>;
status = "okay";
};
&hdmi0 {
status = "okay";
};
&hdmi0_in {
hdmi0_in_vp0: endpoint {
remote-endpoint = <&vp0_out_hdmi0>;
};
};
&hdptxphy_hdmi0 {
status = "okay";
};
&i2c0 {
pinctrl-names = "default";
pinctrl-0 = <&i2c0m2_xfer>;
@ -219,135 +204,133 @@
};
};
&i2c6 {
&i2c2 {
status = "okay";
vdd_npu_s0: regulator@42 {
compatible = "rockchip,rk8602";
reg = <0x42>;
fcs,suspend-voltage-selector = <1>;
regulator-name = "vdd_npu_s0";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <550000>;
regulator-max-microvolt = <950000>;
regulator-ramp-delay = <2300>;
vin-supply = <&vcc5v0_sys>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
};
&i2c6 {
pinctrl-names = "default";
pinctrl-0 = <&i2c6m3_xfer>;
status = "okay";
usbc0: usb-typec@22 {
compatible = "fcs,fusb302";
reg = <0x22>;
interrupt-parent = <&gpio0>;
interrupts = <RK_PD3 IRQ_TYPE_LEVEL_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&usbc0_int>;
vbus-supply = <&vbus_typec>;
status = "okay";
usb_con: connector {
compatible = "usb-c-connector";
label = "USB-C";
data-role = "dual";
op-sink-microwatt = <1000000>;
power-role = "dual";
sink-pdos =
<PDO_FIXED(5000, 1000, PDO_FIXED_USB_COMM)>;
source-pdos =
<PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>;
try-power-role = "source";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
usbc0_hs: endpoint {
remote-endpoint = <&usb_host0_xhci_drd_sw>;
};
};
port@1 {
reg = <1>;
usbc0_ss: endpoint {
remote-endpoint = <&usbdp_phy0_typec_ss>;
};
};
port@2 {
reg = <2>;
usbc0_sbu: endpoint {
remote-endpoint = <&usbdp_phy0_typec_sbu>;
};
};
};
};
};
hym8563: rtc@51 {
compatible = "haoyu,hym8563";
reg = <0x51>;
interrupt-parent = <&gpio0>;
interrupts = <RK_PB0 IRQ_TYPE_LEVEL_LOW>;
#clock-cells = <0>;
clock-output-names = "hym8563";
pinctrl-names = "default";
pinctrl-0 = <&hym8563_int>;
interrupt-parent = <&gpio0>;
interrupts = <RK_PB0 IRQ_TYPE_LEVEL_LOW>;
wakeup-source;
};
};
&i2c7 {
status = "okay";
es8316: audio-codec@11 {
compatible = "everest,es8316";
reg = <0x11>;
assigned-clocks = <&cru I2S0_8CH_MCLKOUT>;
assigned-clock-rates = <12288000>;
clocks = <&cru I2S0_8CH_MCLKOUT>;
clock-names = "mclk";
#sound-dai-cells = <0>;
port {
es8316_p0_0: endpoint {
remote-endpoint = <&i2s0_8ch_p0_0>;
};
};
&mdio1 {
rgmii_phy1: ethernet-phy@1 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <0x1>;
reset-assert-us = <20000>;
reset-deassert-us = <100000>;
reset-gpios = <&gpio3 RK_PB2 GPIO_ACTIVE_LOW>;
};
};
&i2s0_8ch {
pinctrl-names = "default";
pinctrl-0 = <&i2s0_lrck
&i2s0_mclk
&i2s0_sclk
&i2s0_sdi0
&i2s0_sdo0>;
status = "okay";
i2s0_8ch_p0: port {
i2s0_8ch_p0_0: endpoint {
dai-format = "i2s";
mclk-fs = <256>;
remote-endpoint = <&es8316_p0_0>;
};
};
};
/* phy1 - right ethernet port */
&pcie2x1l0 {
reset-gpios = <&gpio4 RK_PA5 GPIO_ACTIVE_HIGH>;
status = "okay";
};
/* phy2 - WiFi */
&pcie2x1l1 {
reset-gpios = <&gpio3 RK_PD4 GPIO_ACTIVE_HIGH>;
status = "okay";
pcie@0,0 {
reg = <0x300000 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
ranges;
device_type = "pci";
bus-range = <0x30 0x3f>;
wifi: wifi@0,0 {
compatible = "pci14e4,449d";
reg = <0x310000 0 0 0 0>;
clocks = <&hym8563>;
clock-names = "32k";
};
};
};
/* phy0 - left ethernet port */
&pcie2x1l2 {
reset-gpios = <&gpio3 RK_PB0 GPIO_ACTIVE_HIGH>;
status = "okay";
};
&pcie30phy {
status = "okay";
};
&pcie3x4 {
reset-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>;
vpcie3v3-supply = <&vcc3v3_pcie30>;
reset-gpios = <&gpio3 RK_PD1 GPIO_ACTIVE_HIGH>;
vpcie3v3-supply = <&vcc3v3_pcie20>;
status = "okay";
};
&pinctrl {
gpio-func {
leds_gpio: leds-gpio {
rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
hym8563 {
hym8563_int: hym8563-int {
rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
leds {
led_rgb_g: led-rgb-g {
rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>;
usb-typec {
usbc0_int: usbc0-int {
rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>;
};
led_rgb_r: led-rgb-r {
rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>;
typec5v_pwren: typec5v-pwren {
rockchip,pins = <3 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
sound {
hp_detect: hp-detect {
rockchip,pins = <1 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
usb {
vcc5v0_host_en: vcc5v0-host-en {
rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
};
&pwm1 {
status = "okay";
};
&saradc {
@ -355,52 +338,50 @@
status = "okay";
};
&sdhci {
bus-width = <8>;
no-sdio;
no-sd;
non-removable;
mmc-hs200-1_8v;
status = "okay";
};
&sdmmc {
bus-width = <4>;
cap-mmc-highspeed;
cap-sd-highspeed;
disable-wp;
max-frequency = <200000000>;
no-sdio;
max-frequency = <150000000>;
no-mmc;
no-sdio;
sd-uhs-sdr104;
vmmc-supply = <&vcc_3v3_s3>;
vmmc-supply = <&vcc_3v3_sd_s0>;
vqmmc-supply = <&vccio_sd_s0>;
status = "okay";
};
&sfc {
pinctrl-names = "default";
pinctrl-0 = <&fspim0_pins>;
status = "okay";
flash@0 {
compatible = "jedec,spi-nor";
reg = <0x0>;
spi-max-frequency = <100000000>;
spi-rx-bus-width = <4>;
spi-tx-bus-width = <1>;
};
};
&spi2 {
status = "okay";
assigned-clocks = <&cru CLK_SPI2>;
assigned-clock-rates = <200000000>;
num-cs = <1>;
pinctrl-names = "default";
pinctrl-0 = <&spi2m2_cs0 &spi2m2_pins>;
status = "okay";
pmic@0 {
compatible = "rockchip,rk806";
spi-max-frequency = <1000000>;
reg = <0x0>;
interrupt-parent = <&gpio0>;
interrupts = <7 IRQ_TYPE_LEVEL_LOW>;
gpio-controller;
#gpio-cells = <2>;
pinctrl-names = "default";
pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>,
<&rk806_dvs2_null>, <&rk806_dvs3_null>;
<&rk806_dvs2_null>, <&rk806_dvs3_null>;
spi-max-frequency = <1000000>;
system-power-controller;
vcc1-supply = <&vcc5v0_sys>;
@ -419,6 +400,9 @@
vcc14-supply = <&vcc_1v1_nldo_s3>;
vcca-supply = <&vcc5v0_sys>;
gpio-controller;
#gpio-cells = <2>;
rk806_dvs1_null: dvs1-null-pins {
pins = "gpio_pwrctrl1";
function = "pin_fun0";
@ -435,13 +419,12 @@
};
regulators {
vdd_gpu_s0: vdd_gpu_mem_s0: dcdc-reg1 {
regulator-always-on;
vdd_gpu_s0: dcdc-reg1 {
regulator-name = "vdd_gpu_s0";
regulator-boot-on;
regulator-min-microvolt = <550000>;
regulator-max-microvolt = <950000>;
regulator-ramp-delay = <12500>;
regulator-name = "vdd_gpu_s0";
regulator-enable-ramp-delay = <400>;
regulator-state-mem {
@ -449,13 +432,13 @@
};
};
vdd_cpu_lit_s0: vdd_cpu_lit_mem_s0: dcdc-reg2 {
vdd_cpu_lit_s0: dcdc-reg2 {
regulator-name = "vdd_cpu_lit_s0";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <550000>;
regulator-max-microvolt = <950000>;
regulator-ramp-delay = <12500>;
regulator-name = "vdd_cpu_lit_s0";
regulator-state-mem {
regulator-off-in-suspend;
@ -463,12 +446,12 @@
};
vdd_log_s0: dcdc-reg3 {
regulator-name = "vdd_log_s0";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <675000>;
regulator-max-microvolt = <750000>;
regulator-ramp-delay = <12500>;
regulator-name = "vdd_log_s0";
regulator-state-mem {
regulator-off-in-suspend;
@ -476,13 +459,13 @@
};
};
vdd_vdenc_s0: vdd_vdenc_mem_s0: dcdc-reg4 {
vdd_vdenc_s0: dcdc-reg4 {
regulator-name = "vdd_vdenc_s0";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <550000>;
regulator-max-microvolt = <950000>;
regulator-ramp-delay = <12500>;
regulator-name = "vdd_vdenc_s0";
regulator-state-mem {
regulator-off-in-suspend;
@ -490,12 +473,12 @@
};
vdd_ddr_s0: dcdc-reg5 {
regulator-name = "vdd_ddr_s0";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <675000>;
regulator-max-microvolt = <900000>;
regulator-ramp-delay = <12500>;
regulator-name = "vdd_ddr_s0";
regulator-state-mem {
regulator-off-in-suspend;
@ -503,10 +486,12 @@
};
};
vdd2_ddr_s3: dcdc-reg6 {
vcc_1v1_nldo_s3: vdd2_ddr_s3: dcdc-reg6 {
regulator-name = "vdd2_ddr_s3";
regulator-always-on;
regulator-boot-on;
regulator-name = "vdd2_ddr_s3";
regulator-max-microvolt = <1100000>;
regulator-min-microvolt = <1100000>;
regulator-state-mem {
regulator-on-in-suspend;
@ -514,12 +499,12 @@
};
vcc_2v0_pldo_s3: dcdc-reg7 {
regulator-name = "vdd_2v0_pldo_s3";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <2000000>;
regulator-max-microvolt = <2000000>;
regulator-ramp-delay = <12500>;
regulator-name = "vdd_2v0_pldo_s3";
regulator-state-mem {
regulator-on-in-suspend;
@ -528,11 +513,11 @@
};
vcc_3v3_s3: dcdc-reg8 {
regulator-name = "vcc_3v3_s3";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-name = "vcc_3v3_s3";
regulator-state-mem {
regulator-on-in-suspend;
@ -541,9 +526,9 @@
};
vddq_ddr_s0: dcdc-reg9 {
regulator-name = "vddq_ddr_s0";
regulator-always-on;
regulator-boot-on;
regulator-name = "vddq_ddr_s0";
regulator-state-mem {
regulator-off-in-suspend;
@ -551,11 +536,11 @@
};
vcc_1v8_s3: dcdc-reg10 {
regulator-name = "vcc_1v8_s3";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-name = "vcc_1v8_s3";
regulator-state-mem {
regulator-on-in-suspend;
@ -564,11 +549,11 @@
};
avcc_1v8_s0: pldo-reg1 {
regulator-name = "avcc_1v8_s0";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-name = "avcc_1v8_s0";
regulator-state-mem {
regulator-off-in-suspend;
@ -576,11 +561,11 @@
};
vcc_1v8_s0: pldo-reg2 {
regulator-name = "vcc_1v8_s0";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-name = "vcc_1v8_s0";
regulator-state-mem {
regulator-off-in-suspend;
@ -589,11 +574,11 @@
};
avdd_1v2_s0: pldo-reg3 {
regulator-name = "avdd_1v2_s0";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
regulator-name = "avdd_1v2_s0";
regulator-state-mem {
regulator-off-in-suspend;
@ -601,12 +586,12 @@
};
vcc_3v3_s0: pldo-reg4 {
regulator-name = "vcc_3v3_s0";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-ramp-delay = <12500>;
regulator-name = "vcc_3v3_s0";
regulator-state-mem {
regulator-off-in-suspend;
@ -614,12 +599,12 @@
};
vccio_sd_s0: pldo-reg5 {
regulator-name = "vccio_sd_s0";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-ramp-delay = <12500>;
regulator-name = "vccio_sd_s0";
regulator-state-mem {
regulator-off-in-suspend;
@ -627,11 +612,11 @@
};
pldo6_s3: pldo-reg6 {
regulator-name = "pldo6_s3";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-name = "pldo6_s3";
regulator-state-mem {
regulator-on-in-suspend;
@ -640,11 +625,11 @@
};
vdd_0v75_s3: nldo-reg1 {
regulator-name = "vdd_0v75_s3";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <750000>;
regulator-max-microvolt = <750000>;
regulator-name = "vdd_0v75_s3";
regulator-state-mem {
regulator-on-in-suspend;
@ -653,11 +638,11 @@
};
vdd_ddr_pll_s0: nldo-reg2 {
regulator-name = "vdd_ddr_pll_s0";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <850000>;
regulator-max-microvolt = <850000>;
regulator-name = "vdd_ddr_pll_s0";
regulator-state-mem {
regulator-off-in-suspend;
@ -666,11 +651,11 @@
};
avdd_0v75_s0: nldo-reg3 {
regulator-name = "avdd_0v75_s0";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <750000>;
regulator-max-microvolt = <750000>;
regulator-name = "avdd_0v75_s0";
regulator-state-mem {
regulator-off-in-suspend;
@ -678,11 +663,11 @@
};
vdd_0v85_s0: nldo-reg4 {
regulator-name = "vdd_0v85_s0";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <850000>;
regulator-max-microvolt = <850000>;
regulator-name = "vdd_0v85_s0";
regulator-state-mem {
regulator-off-in-suspend;
@ -690,11 +675,11 @@
};
vdd_0v75_s0: nldo-reg5 {
regulator-name = "vdd_0v75_s0";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <750000>;
regulator-max-microvolt = <750000>;
regulator-name = "vdd_0v75_s0";
regulator-state-mem {
regulator-off-in-suspend;
@ -704,6 +689,10 @@
};
};
&tsadc {
status = "okay";
};
&u2phy0 {
status = "okay";
};
@ -712,11 +701,11 @@
status = "okay";
};
&u2phy1 {
&u2phy2 {
status = "okay";
};
&u2phy1_otg {
&u2phy2_host {
status = "okay";
};
@ -725,7 +714,6 @@
};
&u2phy3_host {
phy-supply = <&vcc5v0_host>;
status = "okay";
};
@ -734,8 +722,47 @@
status = "okay";
};
&usbdp_phy1 {
&usbdp_phy0 {
mode-switch;
orientation-switch;
sbu1-dc-gpios = <&gpio4 RK_PA5 GPIO_ACTIVE_HIGH>;
sbu2-dc-gpios = <&gpio4 RK_PA7 GPIO_ACTIVE_HIGH>;
status = "okay";
port {
#address-cells = <1>;
#size-cells = <0>;
usbdp_phy0_typec_ss: endpoint@0 {
reg = <0>;
remote-endpoint = <&usbc0_ss>;
};
usbdp_phy0_typec_sbu: endpoint@1 {
reg = <1>;
remote-endpoint = <&usbc0_sbu>;
};
};
};
&usb_host0_ehci {
status = "okay";
};
&usb_host0_ohci {
status = "okay";
};
&usb_host0_xhci {
dr_mode = "host";
usb-role-switch;
status = "okay";
port {
usb_host0_xhci_drd_sw: endpoint {
remote-endpoint = <&usbc0_hs>;
};
};
};
&usb_host1_ehci {
@ -746,11 +773,31 @@
status = "okay";
};
&usb_host1_xhci {
dr_mode = "host";
&usb_host2_xhci {
status = "okay";
};
&hdptxphy_hdmi0 {
status = "okay";
};
&hdmi0 {
enable-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>;
status = "okay";
};
&hdmi0_in {
hdmi0_in_vp0: endpoint {
remote-endpoint = <&vp0_out_hdmi0>;
};
};
&hdmi0_out {
hdmi0_out_con: endpoint {
remote-endpoint = <&hdmi0_con_in>;
};
};
&vop {
status = "okay";
};

0
patch/kernel/archive/rockchip-rk3588-6.8/dt/rk3588s-orangepi-5b.dts → patch/kernel/archive/rockchip-rk3588-6.10/dt/rk3588s-orangepi-5b.dts
View File

0
patch/kernel/archive/rockchip-rk3588-6.8/dt/rk3588s-rock-5c.dts → patch/kernel/archive/rockchip-rk3588-6.10/dt/rk3588s-rock-5c.dts
View File

4
patch/kernel/archive/rockchip-rk3588-6.8/overlay/Makefile → patch/kernel/archive/rockchip-rk3588-6.10/overlay/Makefile
View File

@ -40,8 +40,6 @@ dtbo-$(CONFIG_ARCH_ROCKCHIP) += \
rockchip-rk3588-uart7-m2.dtbo \
rockchip-rk3588-uart8-m1.dtbo
targets += $(dtbo-y)
dtb-y += $(dtbo-y)
always := $(dtbo-y)
clean-files := *.dtbo

0
patch/kernel/archive/rockchip-rk3588-6.8/overlay/rockchip-rk3588-i2c8-m2.dts → patch/kernel/archive/rockchip-rk3588-6.10/overlay/rockchip-rk3588-i2c8-m2.dtso
View File

0
patch/kernel/archive/rockchip-rk3588-6.8/overlay/rockchip-rk3588-pwm0-m0.dts → patch/kernel/archive/rockchip-rk3588-6.10/overlay/rockchip-rk3588-pwm0-m0.dtso
View File

0
patch/kernel/archive/rockchip-rk3588-6.8/overlay/rockchip-rk3588-pwm0-m1.dts → patch/kernel/archive/rockchip-rk3588-6.10/overlay/rockchip-rk3588-pwm0-m1.dtso
View File

0
patch/kernel/archive/rockchip-rk3588-6.8/overlay/rockchip-rk3588-pwm0-m2.dts → patch/kernel/archive/rockchip-rk3588-6.10/overlay/rockchip-rk3588-pwm0-m2.dtso
View File

0
patch/kernel/archive/rockchip-rk3588-6.8/overlay/rockchip-rk3588-pwm1-m0.dts → patch/kernel/archive/rockchip-rk3588-6.10/overlay/rockchip-rk3588-pwm1-m0.dtso
View File

0
patch/kernel/archive/rockchip-rk3588-6.8/overlay/rockchip-rk3588-pwm1-m1.dts → patch/kernel/archive/rockchip-rk3588-6.10/overlay/rockchip-rk3588-pwm1-m1.dtso
View File

0
patch/kernel/archive/rockchip-rk3588-6.8/overlay/rockchip-rk3588-pwm1-m2.dts → patch/kernel/archive/rockchip-rk3588-6.10/overlay/rockchip-rk3588-pwm1-m2.dtso
View File

0
patch/kernel/archive/rockchip-rk3588-6.8/overlay/rockchip-rk3588-pwm10-m0.dts → patch/kernel/archive/rockchip-rk3588-6.10/overlay/rockchip-rk3588-pwm10-m0.dtso
View File

0
patch/kernel/archive/rockchip-rk3588-6.8/overlay/rockchip-rk3588-pwm11-m0.dts → patch/kernel/archive/rockchip-rk3588-6.10/overlay/rockchip-rk3588-pwm11-m0.dtso
View File

0
patch/kernel/archive/rockchip-rk3588-6.8/overlay/rockchip-rk3588-pwm11-m1.dts → patch/kernel/archive/rockchip-rk3588-6.10/overlay/rockchip-rk3588-pwm11-m1.dtso
View File

0
patch/kernel/archive/rockchip-rk3588-6.8/overlay/rockchip-rk3588-pwm12-m0.dts → patch/kernel/archive/rockchip-rk3588-6.10/overlay/rockchip-rk3588-pwm12-m0.dtso
View File

0
patch/kernel/archive/rockchip-rk3588-6.8/overlay/rockchip-rk3588-pwm13-m0.dts → patch/kernel/archive/rockchip-rk3588-6.10/overlay/rockchip-rk3588-pwm13-m0.dtso
View File

0
patch/kernel/archive/rockchip-rk3588-6.8/overlay/rockchip-rk3588-pwm13-m2.dts → patch/kernel/archive/rockchip-rk3588-6.10/overlay/rockchip-rk3588-pwm13-m2.dtso
View File

0
patch/kernel/archive/rockchip-rk3588-6.8/overlay/rockchip-rk3588-pwm14-m0.dts → patch/kernel/archive/rockchip-rk3588-6.10/overlay/rockchip-rk3588-pwm14-m0.dtso
View File

0
patch/kernel/archive/rockchip-rk3588-6.8/overlay/rockchip-rk3588-pwm14-m1.dts → patch/kernel/archive/rockchip-rk3588-6.10/overlay/rockchip-rk3588-pwm14-m1.dtso
View File

0
patch/kernel/archive/rockchip-rk3588-6.8/overlay/rockchip-rk3588-pwm14-m2.dts → patch/kernel/archive/rockchip-rk3588-6.10/overlay/rockchip-rk3588-pwm14-m2.dtso
View File

0
patch/kernel/archive/rockchip-rk3588-6.8/overlay/rockchip-rk3588-pwm15-m0.dts → patch/kernel/archive/rockchip-rk3588-6.10/overlay/rockchip-rk3588-pwm15-m0.dtso
View File

0
patch/kernel/archive/rockchip-rk3588-6.8/overlay/rockchip-rk3588-pwm15-m1.dts → patch/kernel/archive/rockchip-rk3588-6.10/overlay/rockchip-rk3588-pwm15-m1.dtso
View File

0
patch/kernel/archive/rockchip-rk3588-6.8/overlay/rockchip-rk3588-pwm15-m2.dts → patch/kernel/archive/rockchip-rk3588-6.10/overlay/rockchip-rk3588-pwm15-m2.dtso
View File

0
patch/kernel/archive/rockchip-rk3588-6.8/overlay/rockchip-rk3588-pwm15-m3.dts → patch/kernel/archive/rockchip-rk3588-6.10/overlay/rockchip-rk3588-pwm15-m3.dtso
View File

0
patch/kernel/archive/rockchip-rk3588-6.8/overlay/rockchip-rk3588-pwm2-m1.dts → patch/kernel/archive/rockchip-rk3588-6.10/overlay/rockchip-rk3588-pwm2-m1.dtso
View File

0
patch/kernel/archive/rockchip-rk3588-6.8/overlay/rockchip-rk3588-pwm3-m0.dts → patch/kernel/archive/rockchip-rk3588-6.10/overlay/rockchip-rk3588-pwm3-m0.dtso
View File

0
patch/kernel/archive/rockchip-rk3588-6.8/overlay/rockchip-rk3588-pwm3-m1.dts → patch/kernel/archive/rockchip-rk3588-6.10/overlay/rockchip-rk3588-pwm3-m1.dtso
View File

0
patch/kernel/archive/rockchip-rk3588-6.8/overlay/rockchip-rk3588-pwm3-m2.dts → patch/kernel/archive/rockchip-rk3588-6.10/overlay/rockchip-rk3588-pwm3-m2.dtso
View File

0
patch/kernel/archive/rockchip-rk3588-6.8/overlay/rockchip-rk3588-pwm3-m3.dts → patch/kernel/archive/rockchip-rk3588-6.10/overlay/rockchip-rk3588-pwm3-m3.dtso
View File

0
patch/kernel/archive/rockchip-rk3588-6.8/overlay/rockchip-rk3588-pwm5-m2.dts → patch/kernel/archive/rockchip-rk3588-6.10/overlay/rockchip-rk3588-pwm5-m2.dtso
View File

0
patch/kernel/archive/rockchip-rk3588-6.8/overlay/rockchip-rk3588-pwm6-m0.dts → patch/kernel/archive/rockchip-rk3588-6.10/overlay/rockchip-rk3588-pwm6-m0.dtso
View File

0
patch/kernel/archive/rockchip-rk3588-6.8/overlay/rockchip-rk3588-pwm6-m2.dts → patch/kernel/archive/rockchip-rk3588-6.10/overlay/rockchip-rk3588-pwm6-m2.dtso
View File

0
patch/kernel/archive/rockchip-rk3588-6.8/overlay/rockchip-rk3588-pwm7-m0.dts → patch/kernel/archive/rockchip-rk3588-6.10/overlay/rockchip-rk3588-pwm7-m0.dtso
View File

0
patch/kernel/archive/rockchip-rk3588-6.8/overlay/rockchip-rk3588-pwm7-m3.dts → patch/kernel/archive/rockchip-rk3588-6.10/overlay/rockchip-rk3588-pwm7-m3.dtso
View File

0
patch/kernel/archive/rockchip-rk3588-6.8/overlay/rockchip-rk3588-pwm8-m0.dts → patch/kernel/archive/rockchip-rk3588-6.10/overlay/rockchip-rk3588-pwm8-m0.dtso
View File

0
patch/kernel/archive/rockchip-rk3588-6.8/overlay/rockchip-rk3588-sata1.dts → patch/kernel/archive/rockchip-rk3588-6.10/overlay/rockchip-rk3588-sata1.dtso
View File

0
patch/kernel/archive/rockchip-rk3588-6.8/overlay/rockchip-rk3588-sata2.dts → patch/kernel/archive/rockchip-rk3588-6.10/overlay/rockchip-rk3588-sata2.dtso
View File

0
patch/kernel/archive/rockchip-rk3588-6.8/overlay/rockchip-rk3588-uart1-m1.dts → patch/kernel/archive/rockchip-rk3588-6.10/overlay/rockchip-rk3588-uart1-m1.dtso
View File

0
patch/kernel/archive/rockchip-rk3588-6.8/overlay/rockchip-rk3588-uart3-m1.dts → patch/kernel/archive/rockchip-rk3588-6.10/overlay/rockchip-rk3588-uart3-m1.dtso
View File

0
patch/kernel/archive/rockchip-rk3588-6.8/overlay/rockchip-rk3588-uart4-m2.dts → patch/kernel/archive/rockchip-rk3588-6.10/overlay/rockchip-rk3588-uart4-m2.dtso
View File

0
patch/kernel/archive/rockchip-rk3588-6.8/overlay/rockchip-rk3588-uart6-m1.dts → patch/kernel/archive/rockchip-rk3588-6.10/overlay/rockchip-rk3588-uart6-m1.dtso
View File

0
patch/kernel/archive/rockchip-rk3588-6.8/overlay/rockchip-rk3588-uart7-m2.dts → patch/kernel/archive/rockchip-rk3588-6.10/overlay/rockchip-rk3588-uart7-m2.dtso
View File

0
patch/kernel/archive/rockchip-rk3588-6.8/overlay/rockchip-rk3588-uart8-m1.dts → patch/kernel/archive/rockchip-rk3588-6.10/overlay/rockchip-rk3588-uart8-m1.dtso
View File

84
patch/kernel/archive/rockchip-rk3588-6.8/0001-general-add-overlay-support.patch
View File

@ -1,84 +0,0 @@
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
From: zador-blood-stained <zador-blood-stained@users.noreply.github.com>
Date: Sat, 11 Feb 2017 20:32:53 +0300
Subject: add overlay support
- rpardini: real overlays are now bare in "overlay" directory and are handled
directly by the patching scripts. No more null-patching of overlays.
- no readme, no fixups
---
scripts/Makefile.dtbinst | 6 +++-
scripts/Makefile.lib | 17 ++++++++++
2 files changed, 22 insertions(+), 1 deletion(-)
diff --git a/scripts/Makefile.dtbinst b/scripts/Makefile.dtbinst
index 111111111111..222222222222 100644
--- a/scripts/Makefile.dtbinst
+++ b/scripts/Makefile.dtbinst
@@ -18,9 +18,10 @@ include $(srctree)/scripts/Kbuild.include
include $(kbuild-file)
dtbs := $(addprefix $(dst)/, $(dtb-y) $(if $(CONFIG_OF_ALL_DTBS),$(dtb-)))
+dtbos := $(addprefix $(dst)/, $(dtbo-y))
subdirs := $(addprefix $(obj)/, $(subdir-y) $(subdir-m))
-__dtbs_install: $(dtbs) $(subdirs)
+__dtbs_install: $(dtbs) $(dtbos) $(subdirs)
@:
quiet_cmd_dtb_install = INSTALL $@
@@ -32,6 +33,9 @@ $(dst)/%.dtb: $(obj)/%.dtb
$(dst)/%.dtbo: $(obj)/%.dtbo
$(call cmd,dtb_install)
+$(dst)/%.dtbo: $(obj)/%.dtbo
+ $(call cmd,dtb_install)
+
PHONY += $(subdirs)
$(subdirs):
$(Q)$(MAKE) $(dtbinst)=$@ dst=$(if $(CONFIG_ARCH_WANT_FLAT_DTB_INSTALL),$(dst),$(patsubst $(obj)/%,$(dst)/%,$@))
diff --git a/scripts/Makefile.lib b/scripts/Makefile.lib
index 111111111111..222222222222 100644
--- a/scripts/Makefile.lib
+++ b/scripts/Makefile.lib
@@ -88,6 +88,9 @@ base-dtb-y := $(filter %.dtb, $(call real-search, $(multi-dtb-y), .dtb, -dtbs))
always-y += $(dtb-y)
+# Overlay targets
+extra-y += $(dtbo-y)
+
# Add subdir path
ifneq ($(obj),.)
@@ -343,6 +346,9 @@ DTC ?= $(objtree)/scripts/dtc/dtc
DTC_FLAGS += -Wno-interrupt_provider \
-Wno-unique_unit_address
+# Overlay support
+DTC_FLAGS += -@ -Wno-unit_address_format -Wno-simple_bus_reg
+
# Disable noisy checks by default
ifeq ($(findstring 1,$(KBUILD_EXTRA_WARN)),)
DTC_FLAGS += -Wno-unit_address_vs_reg \
@@ -421,6 +427,17 @@ $(obj)/%.dtb: $(src)/%.dts $(DTC) $(DT_TMP_SCHEMA) FORCE
$(obj)/%.dtbo: $(src)/%.dtso $(DTC) FORCE
$(call if_changed_dep,dtc)
+quiet_cmd_dtco = DTCO $@
+cmd_dtco = mkdir -p $(dir ${dtc-tmp}) ; \
+ $(CPP) $(dtc_cpp_flags) -x assembler-with-cpp -o $(dtc-tmp) $< ; \
+ $(DTC) -O dtb -o $@ -b 0 \
+ -i $(dir $<) $(DTC_FLAGS) \
+ -d $(depfile).dtc.tmp $(dtc-tmp) ; \
+ cat $(depfile).pre.tmp $(depfile).dtc.tmp > $(depfile)
+
+$(obj)/%.dtbo: $(src)/%.dts FORCE
+ $(call if_changed_dep,dtco)
+
dtc-tmp = $(subst $(comma),_,$(dot-target).dts.tmp)
# Bzip2
--
Armbian

34
patch/kernel/archive/rockchip-rk3588-6.8/0005-tools-Makefile-delete-missing-cgroup_clean.patch
View File

@ -1,34 +0,0 @@
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
From: amazingfate <liujianfeng1994@gmail.com>
Date: Wed, 24 Jan 2024 18:03:52 +0800
Subject: tools/Makefile: delete missing cgroup_clean
---
tools/Makefile | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/tools/Makefile b/tools/Makefile
index 111111111111..222222222222 100644
--- a/tools/Makefile
+++ b/tools/Makefile
@@ -169,7 +169,7 @@ acpi_clean:
cpupower_clean:
$(call descend,power/cpupower,clean)
-cgroup_clean counter_clean hv_clean firewire_clean bootconfig_clean spi_clean usb_clean virtio_clean mm_clean wmi_clean bpf_clean iio_clean gpio_clean objtool_clean leds_clean pci_clean firmware_clean debugging_clean tracing_clean:
+counter_clean hv_clean firewire_clean bootconfig_clean spi_clean usb_clean virtio_clean mm_clean wmi_clean bpf_clean iio_clean gpio_clean objtool_clean leds_clean pci_clean firmware_clean debugging_clean tracing_clean:
$(call descend,$(@:_clean=),clean)
libapi_clean:
@@ -209,7 +209,7 @@ freefall_clean:
build_clean:
$(call descend,build,clean)
-clean: acpi_clean cgroup_clean counter_clean cpupower_clean hv_clean firewire_clean \
+clean: acpi_clean counter_clean cpupower_clean hv_clean firewire_clean \
perf_clean selftests_clean turbostat_clean bootconfig_clean spi_clean usb_clean virtio_clean \
mm_clean bpf_clean iio_clean x86_energy_perf_policy_clean tmon_clean \
freefall_clean build_clean libbpf_clean libsubcmd_clean \
--
Armbian

2602
patch/kernel/archive/rockchip-rk3588-6.8/0021-RK3588-Add-USB3-DRD-Support.patch
View File

File diff suppressed because it is too large Load Diff

626
patch/kernel/archive/rockchip-rk3588-6.8/0022-RK3588-Add-Cpufreq-Support.patch
View File

@ -1,626 +0,0 @@
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
From: Alexey Charkov <alchark@gmail.com>
Date: Thu, 29 Feb 2024 23:26:32 +0400
Subject: arm64: dts: rockchip: enable built-in thermal monitoring on RK3588
Include thermal zones information in device tree for RK3588 variants.
This also enables the TSADC controller unconditionally on all boards
to ensure that thermal protections are in place via throttling and
emergency reset, once OPPs are added to enable CPU DVFS.
The default settings (using CRU as the emergency reset mechanism)
should work on all boards regardless of their wiring, as CRU resets
do not depend on any external components. Boards that have the TSHUT
signal wired to the reset line of the PMIC may opt to switch to GPIO
tshut mode instead (rockchip,hw-tshut-mode = <1>;)
It seems though that downstream kernels don't use that, even for
those boards where the wiring allows for GPIO based tshut, such as
Radxa Rock 5B [1], [2], [3]
[1] https://github.com/radxa/kernel/blob/stable-5.10-rock5/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts#L540
[2] https://github.com/radxa/kernel/blob/stable-5.10-rock5/arch/arm64/boot/dts/rockchip/rk3588s.dtsi#L5433
[3] https://dl.radxa.com/rock5/5b/docs/hw/radxa_rock_5b_v1423_sch.pdf page 11 (TSADC_SHUT_H)
Signed-off-by: Alexey Charkov <alchark@gmail.com>
Link: https://lore.kernel.org/r/20240229-rk-dts-additions-v3-1-6afe8473a631@gmail.com
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
---
arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 176 +++++++++-
1 file changed, 175 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
index 111111111111..222222222222 100644
--- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
@@ -10,6 +10,7 @@
#include <dt-bindings/reset/rockchip,rk3588-cru.h>
#include <dt-bindings/phy/phy.h>
#include <dt-bindings/ata/ahci.h>
+#include <dt-bindings/thermal/thermal.h>
/ {
compatible = "rockchip,rk3588";
@@ -2286,7 +2287,180 @@ tsadc: tsadc@fec00000 {
pinctrl-1 = <&tsadc_shut>;
pinctrl-names = "gpio", "otpout";
#thermal-sensor-cells = <1>;
- status = "disabled";
+ status = "okay";
+ };
+
+ thermal_zones: thermal-zones {
+ /* sensor near the center of the SoC */
+ package_thermal: package-thermal {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-sensors = <&tsadc 0>;
+
+ trips {
+ package_crit: package-crit {
+ temperature = <115000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ /* sensor between A76 cores 0 and 1 */
+ bigcore0_thermal: bigcore0-thermal {
+ polling-delay-passive = <100>;
+ polling-delay = <0>;
+ thermal-sensors = <&tsadc 1>;
+
+ trips {
+ /* threshold to start collecting temperature
+ * statistics e.g. with the IPA governor
+ */
+ bigcore0_alert0: bigcore0-alert0 {
+ temperature = <75000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+ /* actual control temperature */
+ bigcore0_alert1: bigcore0-alert1 {
+ temperature = <85000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+ bigcore0_crit: bigcore0-crit {
+ temperature = <115000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ cooling-maps {
+ map0 {
+ trip = <&bigcore0_alert1>;
+ cooling-device =
+ <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu_b1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
+ };
+
+ /* sensor between A76 cores 2 and 3 */
+ bigcore2_thermal: bigcore2-thermal {
+ polling-delay-passive = <100>;
+ polling-delay = <0>;
+ thermal-sensors = <&tsadc 2>;
+
+ trips {
+ /* threshold to start collecting temperature
+ * statistics e.g. with the IPA governor
+ */
+ bigcore2_alert0: bigcore2-alert0 {
+ temperature = <75000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+ /* actual control temperature */
+ bigcore2_alert1: bigcore2-alert1 {
+ temperature = <85000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+ bigcore2_crit: bigcore2-crit {
+ temperature = <115000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ cooling-maps {
+ map0 {
+ trip = <&bigcore2_alert1>;
+ cooling-device =
+ <&cpu_b2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu_b3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
+ };
+
+ /* sensor between the four A55 cores */
+ little_core_thermal: littlecore-thermal {
+ polling-delay-passive = <100>;
+ polling-delay = <0>;
+ thermal-sensors = <&tsadc 3>;
+
+ trips {
+ /* threshold to start collecting temperature
+ * statistics e.g. with the IPA governor
+ */
+ littlecore_alert0: littlecore-alert0 {
+ temperature = <75000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+ /* actual control temperature */
+ littlecore_alert1: littlecore-alert1 {
+ temperature = <85000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+ littlecore_crit: littlecore-crit {
+ temperature = <115000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ cooling-maps {
+ map0 {
+ trip = <&littlecore_alert1>;
+ cooling-device =
+ <&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu_l1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu_l2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu_l3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
+ };
+
+ /* sensor near the PD_CENTER power domain */
+ center_thermal: center-thermal {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-sensors = <&tsadc 4>;
+
+ trips {
+ center_crit: center-crit {
+ temperature = <115000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ gpu_thermal: gpu-thermal {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-sensors = <&tsadc 5>;
+
+ trips {
+ gpu_crit: gpu-crit {
+ temperature = <115000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ npu_thermal: npu-thermal {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-sensors = <&tsadc 6>;
+
+ trips {
+ npu_crit: npu-crit {
+ temperature = <115000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
};
saradc: adc@fec10000 {
--
Armbian
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
From: Alexey Charkov <alchark@gmail.com>
Date: Thu, 29 Feb 2024 23:26:35 +0400
Subject: arm64: dts: rockchip: Add OPP data for CPU cores on RK3588
By default the CPUs on RK3588 start up in a conservative performance
mode. Add frequency and voltage mappings to the device tree to enable
dynamic scaling via cpufreq.
OPP values are adapted from Radxa's downstream kernel for Rock 5B [1],
stripping them down to the minimum frequency and voltage combinations
as expected by the generic upstream cpufreq-dt driver, and also dropping
those OPPs that don't differ in voltage but only in frequency (keeping
the top frequency OPP in each case).
Note that this patch ignores voltage scaling for the CPU memory
interface which the downstream kernel does through a custom cpufreq
driver, and which is why the downstream version has two sets of voltage
values for each OPP (the second one being meant for the memory
interface supply regulator). This is done instead via regulator
coupling between CPU and memory interface supplies on affected boards.
This has been tested on Rock 5B with u-boot 2023.11 compiled from
Collabora's integration tree [2] with binary bl31 and appears to be
stable both under active cooling and passive cooling (with throttling)
[1] https://github.com/radxa/kernel/blob/stable-5.10-rock5/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
[2] https://gitlab.collabora.com/hardware-enablement/rockchip-3588/u-boot
Signed-off-by: Alexey Charkov <alchark@gmail.com>
Link: https://lore.kernel.org/r/20240229-rk-dts-additions-v3-4-6afe8473a631@gmail.com
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
---
arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 122 ++++++++++
1 file changed, 122 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
index 111111111111..222222222222 100644
--- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
@@ -97,6 +97,7 @@ cpu_l0: cpu@0 {
clocks = <&scmi_clk SCMI_CLK_CPUL>;
assigned-clocks = <&scmi_clk SCMI_CLK_CPUL>;
assigned-clock-rates = <816000000>;
+ operating-points-v2 = <&cluster0_opp_table>;
cpu-idle-states = <&CPU_SLEEP>;
i-cache-size = <32768>;
i-cache-line-size = <64>;
@@ -116,6 +117,7 @@ cpu_l1: cpu@100 {
enable-method = "psci";
capacity-dmips-mhz = <530>;
clocks = <&scmi_clk SCMI_CLK_CPUL>;
+ operating-points-v2 = <&cluster0_opp_table>;
cpu-idle-states = <&CPU_SLEEP>;
i-cache-size = <32768>;
i-cache-line-size = <64>;
@@ -135,6 +137,7 @@ cpu_l2: cpu@200 {
enable-method = "psci";
capacity-dmips-mhz = <530>;
clocks = <&scmi_clk SCMI_CLK_CPUL>;
+ operating-points-v2 = <&cluster0_opp_table>;
cpu-idle-states = <&CPU_SLEEP>;
i-cache-size = <32768>;
i-cache-line-size = <64>;
@@ -154,6 +157,7 @@ cpu_l3: cpu@300 {
enable-method = "psci";
capacity-dmips-mhz = <530>;
clocks = <&scmi_clk SCMI_CLK_CPUL>;
+ operating-points-v2 = <&cluster0_opp_table>;
cpu-idle-states = <&CPU_SLEEP>;
i-cache-size = <32768>;
i-cache-line-size = <64>;
@@ -175,6 +179,7 @@ cpu_b0: cpu@400 {
clocks = <&scmi_clk SCMI_CLK_CPUB01>;
assigned-clocks = <&scmi_clk SCMI_CLK_CPUB01>;
assigned-clock-rates = <816000000>;
+ operating-points-v2 = <&cluster1_opp_table>;
cpu-idle-states = <&CPU_SLEEP>;
i-cache-size = <65536>;
i-cache-line-size = <64>;
@@ -194,6 +199,7 @@ cpu_b1: cpu@500 {
enable-method = "psci";
capacity-dmips-mhz = <1024>;
clocks = <&scmi_clk SCMI_CLK_CPUB01>;
+ operating-points-v2 = <&cluster1_opp_table>;
cpu-idle-states = <&CPU_SLEEP>;
i-cache-size = <65536>;
i-cache-line-size = <64>;
@@ -215,6 +221,7 @@ cpu_b2: cpu@600 {
clocks = <&scmi_clk SCMI_CLK_CPUB23>;
assigned-clocks = <&scmi_clk SCMI_CLK_CPUB23>;
assigned-clock-rates = <816000000>;
+ operating-points-v2 = <&cluster2_opp_table>;
cpu-idle-states = <&CPU_SLEEP>;
i-cache-size = <65536>;
i-cache-line-size = <64>;
@@ -234,6 +241,7 @@ cpu_b3: cpu@700 {
enable-method = "psci";
capacity-dmips-mhz = <1024>;
clocks = <&scmi_clk SCMI_CLK_CPUB23>;
+ operating-points-v2 = <&cluster2_opp_table>;
cpu-idle-states = <&CPU_SLEEP>;
i-cache-size = <65536>;
i-cache-line-size = <64>;
@@ -348,6 +356,120 @@ l3_cache: l3-cache {
};
};
+ cluster0_opp_table: opp-table-cluster0 {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp-1008000000 {
+ opp-hz = /bits/ 64 <1008000000>;
+ opp-microvolt = <675000 675000 950000>;
+ clock-latency-ns = <40000>;
+ };
+ opp-1200000000 {
+ opp-hz = /bits/ 64 <1200000000>;
+ opp-microvolt = <712500 712500 950000>;
+ clock-latency-ns = <40000>;
+ };
+ opp-1416000000 {
+ opp-hz = /bits/ 64 <1416000000>;
+ opp-microvolt = <762500 762500 950000>;
+ clock-latency-ns = <40000>;
+ opp-suspend;
+ };
+ opp-1608000000 {
+ opp-hz = /bits/ 64 <1608000000>;
+ opp-microvolt = <850000 850000 950000>;
+ clock-latency-ns = <40000>;
+ };
+ opp-1800000000 {
+ opp-hz = /bits/ 64 <1800000000>;
+ opp-microvolt = <950000 950000 950000>;
+ clock-latency-ns = <40000>;
+ };
+ };
+
+ cluster1_opp_table: opp-table-cluster1 {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp-1200000000 {
+ opp-hz = /bits/ 64 <1200000000>;
+ opp-microvolt = <675000 675000 1000000>;
+ clock-latency-ns = <40000>;
+ };
+ opp-1416000000 {
+ opp-hz = /bits/ 64 <1416000000>;
+ opp-microvolt = <725000 725000 1000000>;
+ clock-latency-ns = <40000>;
+ };
+ opp-1608000000 {
+ opp-hz = /bits/ 64 <1608000000>;
+ opp-microvolt = <762500 762500 1000000>;
+ clock-latency-ns = <40000>;
+ };
+ opp-1800000000 {
+ opp-hz = /bits/ 64 <1800000000>;
+ opp-microvolt = <850000 850000 1000000>;
+ clock-latency-ns = <40000>;
+ };
+ opp-2016000000 {
+ opp-hz = /bits/ 64 <2016000000>;
+ opp-microvolt = <925000 925000 1000000>;
+ clock-latency-ns = <40000>;
+ };
+ opp-2208000000 {
+ opp-hz = /bits/ 64 <2208000000>;
+ opp-microvolt = <987500 987500 1000000>;
+ clock-latency-ns = <40000>;
+ };
+ opp-2400000000 {
+ opp-hz = /bits/ 64 <2400000000>;
+ opp-microvolt = <1000000 1000000 1000000>;
+ clock-latency-ns = <40000>;
+ };
+ };
+
+ cluster2_opp_table: opp-table-cluster2 {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp-1200000000 {
+ opp-hz = /bits/ 64 <1200000000>;
+ opp-microvolt = <675000 675000 1000000>;
+ clock-latency-ns = <40000>;
+ };
+ opp-1416000000 {
+ opp-hz = /bits/ 64 <1416000000>;
+ opp-microvolt = <725000 725000 1000000>;
+ clock-latency-ns = <40000>;
+ };
+ opp-1608000000 {
+ opp-hz = /bits/ 64 <1608000000>;
+ opp-microvolt = <762500 762500 1000000>;
+ clock-latency-ns = <40000>;
+ };
+ opp-1800000000 {
+ opp-hz = /bits/ 64 <1800000000>;
+ opp-microvolt = <850000 850000 1000000>;
+ clock-latency-ns = <40000>;
+ };
+ opp-2016000000 {
+ opp-hz = /bits/ 64 <2016000000>;
+ opp-microvolt = <925000 925000 1000000>;
+ clock-latency-ns = <40000>;
+ };
+ opp-2208000000 {
+ opp-hz = /bits/ 64 <2208000000>;
+ opp-microvolt = <987500 987500 1000000>;
+ clock-latency-ns = <40000>;
+ };
+ opp-2400000000 {
+ opp-hz = /bits/ 64 <2400000000>;
+ opp-microvolt = <1000000 1000000 1000000>;
+ clock-latency-ns = <40000>;
+ };
+ };
+
firmware {
optee: optee {
compatible = "linaro,optee-tz";
--
Armbian
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
From: Alexey Charkov <alchark@gmail.com>
Date: Thu, 29 Feb 2024 23:26:36 +0400
Subject: arm64: dts: rockchip: Add further granularity in RK3588 CPU OPPs
This introduces additional OPPs that share the same voltage as
another OPP already present in the .dtsi but with lower frequency.
The idea is to try and limit system throughput more gradually upon
reaching the throttling condition for workloads that are close to
sustainable power already, thus avoiding needless performance loss.
My limited synthetic benchmarking [1] showed around 3.8% performance
benefit when these are in place, other things equal (not meant to
be comprehensive). Though dmesg complains about these OPPs being
'inefficient':
[ 9.009561] cpu cpu0: EM: OPP:816000 is inefficient
[ 9.009580] cpu cpu0: EM: OPP:600000 is inefficient
[ 9.009591] cpu cpu0: EM: OPP:408000 is inefficient
[ 9.011370] cpu cpu4: EM: OPP:2352000 is inefficient
[ 9.011379] cpu cpu4: EM: OPP:2304000 is inefficient
[ 9.011384] cpu cpu4: EM: OPP:2256000 is inefficient
[ 9.011389] cpu cpu4: EM: OPP:600000 is inefficient
[ 9.011393] cpu cpu4: EM: OPP:408000 is inefficient
[ 9.012978] cpu cpu6: EM: OPP:2352000 is inefficient
[ 9.012987] cpu cpu6: EM: OPP:2304000 is inefficient
[ 9.012992] cpu cpu6: EM: OPP:2256000 is inefficient
[ 9.012996] cpu cpu6: EM: OPP:600000 is inefficient
[ 9.013000] cpu cpu6: EM: OPP:408000 is inefficient
[1] https://lore.kernel.org/linux-rockchip/CABjd4YxqarUCbZ-a2XLe3TWJ-qjphGkyq=wDnctnEhdoSdPPpw@mail.gmail.com/T/#me92aa0ee25e6eeb1d1501ce85f5af4e58b3b13c5
Signed-off-by: Alexey Charkov <alchark@gmail.com>
Link: https://lore.kernel.org/r/20240229-rk-dts-additions-v3-5-6afe8473a631@gmail.com
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
---
arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 87 ++++++++++
1 file changed, 87 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
index 111111111111..222222222222 100644
--- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
@@ -360,6 +360,21 @@ cluster0_opp_table: opp-table-cluster0 {
compatible = "operating-points-v2";
opp-shared;
+ opp-408000000 {
+ opp-hz = /bits/ 64 <408000000>;
+ opp-microvolt = <675000 675000 950000>;
+ clock-latency-ns = <40000>;
+ };
+ opp-600000000 {
+ opp-hz = /bits/ 64 <600000000>;
+ opp-microvolt = <675000 675000 950000>;
+ clock-latency-ns = <40000>;
+ };
+ opp-816000000 {
+ opp-hz = /bits/ 64 <816000000>;
+ opp-microvolt = <675000 675000 950000>;
+ clock-latency-ns = <40000>;
+ };
opp-1008000000 {
opp-hz = /bits/ 64 <1008000000>;
opp-microvolt = <675000 675000 950000>;
@@ -392,6 +407,27 @@ cluster1_opp_table: opp-table-cluster1 {
compatible = "operating-points-v2";
opp-shared;
+ opp-408000000 {
+ opp-hz = /bits/ 64 <408000000>;
+ opp-microvolt = <675000 675000 1000000>;
+ clock-latency-ns = <40000>;
+ opp-suspend;
+ };
+ opp-600000000 {
+ opp-hz = /bits/ 64 <600000000>;
+ opp-microvolt = <675000 675000 1000000>;
+ clock-latency-ns = <40000>;
+ };
+ opp-816000000 {
+ opp-hz = /bits/ 64 <816000000>;
+ opp-microvolt = <675000 675000 1000000>;
+ clock-latency-ns = <40000>;
+ };
+ opp-1008000000 {
+ opp-hz = /bits/ 64 <1008000000>;
+ opp-microvolt = <675000 675000 1000000>;
+ clock-latency-ns = <40000>;
+ };
opp-1200000000 {
opp-hz = /bits/ 64 <1200000000>;
opp-microvolt = <675000 675000 1000000>;
@@ -422,6 +458,21 @@ opp-2208000000 {
opp-microvolt = <987500 987500 1000000>;
clock-latency-ns = <40000>;
};
+ opp-2256000000 {
+ opp-hz = /bits/ 64 <2256000000>;
+ opp-microvolt = <1000000 1000000 1000000>;
+ clock-latency-ns = <40000>;
+ };
+ opp-2304000000 {
+ opp-hz = /bits/ 64 <2304000000>;
+ opp-microvolt = <1000000 1000000 1000000>;
+ clock-latency-ns = <40000>;
+ };
+ opp-2352000000 {
+ opp-hz = /bits/ 64 <2352000000>;
+ opp-microvolt = <1000000 1000000 1000000>;
+ clock-latency-ns = <40000>;
+ };
opp-2400000000 {
opp-hz = /bits/ 64 <2400000000>;
opp-microvolt = <1000000 1000000 1000000>;
@@ -433,6 +484,27 @@ cluster2_opp_table: opp-table-cluster2 {
compatible = "operating-points-v2";
opp-shared;
+ opp-408000000 {
+ opp-hz = /bits/ 64 <408000000>;
+ opp-microvolt = <675000 675000 1000000>;
+ clock-latency-ns = <40000>;
+ opp-suspend;
+ };
+ opp-600000000 {
+ opp-hz = /bits/ 64 <600000000>;
+ opp-microvolt = <675000 675000 1000000>;
+ clock-latency-ns = <40000>;
+ };
+ opp-816000000 {
+ opp-hz = /bits/ 64 <816000000>;
+ opp-microvolt = <675000 675000 1000000>;
+ clock-latency-ns = <40000>;
+ };
+ opp-1008000000 {
+ opp-hz = /bits/ 64 <1008000000>;
+ opp-microvolt = <675000 675000 1000000>;
+ clock-latency-ns = <40000>;
+ };
opp-1200000000 {
opp-hz = /bits/ 64 <1200000000>;
opp-microvolt = <675000 675000 1000000>;
@@ -463,6 +535,21 @@ opp-2208000000 {
opp-microvolt = <987500 987500 1000000>;
clock-latency-ns = <40000>;
};
+ opp-2256000000 {
+ opp-hz = /bits/ 64 <2256000000>;
+ opp-microvolt = <1000000 1000000 1000000>;
+ clock-latency-ns = <40000>;
+ };
+ opp-2304000000 {
+ opp-hz = /bits/ 64 <2304000000>;
+ opp-microvolt = <1000000 1000000 1000000>;
+ clock-latency-ns = <40000>;
+ };
+ opp-2352000000 {
+ opp-hz = /bits/ 64 <2352000000>;
+ opp-microvolt = <1000000 1000000 1000000>;
+ clock-latency-ns = <40000>;
+ };
opp-2400000000 {
opp-hz = /bits/ 64 <2400000000>;
opp-microvolt = <1000000 1000000 1000000>;
--
Armbian

1091
patch/kernel/archive/rockchip-rk3588-6.8/0135-phy-rockchip-Add-Samsung-HDMI-eDP-Combo-PHY-driver.patch
View File

File diff suppressed because it is too large Load Diff

54
patch/kernel/archive/rockchip-rk3588-6.8/0136-arm64-dts-rockchip-Add-HDMI0-PHY-to-rk3588.patch
View File

@ -1,54 +0,0 @@
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
From: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
Date: Mon, 19 Feb 2024 22:46:25 +0200
Subject: arm64: dts: rockchip: Add HDMI0 PHY to rk3588
Add DT nodes for HDMI0 PHY and related syscon found on RK3588 SoC.
Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
---
arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 21 ++++++++++
1 file changed, 21 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
index 111111111111..222222222222 100644
--- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
@@ -859,6 +859,11 @@ u2phy3_host: host-port {
};
};
+ hdptxphy0_grf: syscon@fd5e0000 {
+ compatible = "rockchip,rk3588-hdptxphy-grf", "syscon";
+ reg = <0x0 0xfd5e0000 0x0 0x100>;
+ };
+
ioc: syscon@fd5f0000 {
compatible = "rockchip,rk3588-ioc", "syscon";
reg = <0x0 0xfd5f0000 0x0 0x10000>;
@@ -2848,6 +2853,22 @@ usbdp_phy0: phy@fed80000 {
status = "disabled";
};
+ hdptxphy_hdmi0: phy@fed60000 {
+ compatible = "rockchip,rk3588-hdptx-phy";
+ reg = <0x0 0xfed60000 0x0 0x2000>;
+ clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>, <&cru PCLK_HDPTX0>;
+ clock-names = "ref", "apb";
+ #phy-cells = <0>;
+ resets = <&cru SRST_HDPTX0>, <&cru SRST_P_HDPTX0>,
+ <&cru SRST_HDPTX0_INIT>, <&cru SRST_HDPTX0_CMN>,
+ <&cru SRST_HDPTX0_LANE>, <&cru SRST_HDPTX0_ROPLL>,
+ <&cru SRST_HDPTX0_LCPLL>;
+ reset-names = "phy", "apb", "init", "cmn", "lane", "ropll",
+ "lcpll";
+ rockchip,grf = <&hdptxphy0_grf>;
+ status = "disabled";
+ };
+
combphy0_ps: phy@fee00000 {
compatible = "rockchip,rk3588-naneng-combphy";
reg = <0x0 0xfee00000 0x0 0x100>;
--
Armbian

14855
patch/kernel/archive/rockchip-rk3588-6.8/0141-panthor-v6.patch
View File

File diff suppressed because it is too large Load Diff

151
patch/kernel/archive/rockchip-rk3588-6.8/0142-arm64-dts-rockchip-rk3588-Add-GPU-nodes.patch
View File

@ -1,151 +0,0 @@
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
From: Boris Brezillon <boris.brezillon@collabora.com>
Date: Mon, 7 Aug 2023 17:30:58 +0200
Subject: arm64: dts: rockchip: rk3588: Add GPU nodes
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
---
arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 120 ++++++++++
1 file changed, 120 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
index 111111111111..222222222222 100644
--- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
@@ -733,6 +733,121 @@ usb_host2_xhci: usb@fcd00000 {
status = "disabled";
};
+ gpu_opp_table: gpu-opp-table {
+ compatible = "operating-points-v2";
+
+ nvmem-cells = <&gpu_leakage>;
+ nvmem-cell-names = "leakage";
+
+ rockchip,pvtm-voltage-sel = <
+ 0 815 0
+ 816 835 1
+ 836 860 2
+ 861 885 3
+ 886 910 4
+ 911 9999 5
+ >;
+ rockchip,pvtm-pvtpll;
+ rockchip,pvtm-offset = <0x1c>;
+ rockchip,pvtm-sample-time = <1100>;
+ rockchip,pvtm-freq = <800000>;
+ rockchip,pvtm-volt = <750000>;
+ rockchip,pvtm-ref-temp = <25>;
+ rockchip,pvtm-temp-prop = <(-135) (-135)>;
+ rockchip,pvtm-thermal-zone = "gpu-thermal";
+
+ clocks = <&cru CLK_GPU>;
+ clock-names = "clk";
+ rockchip,grf = <&gpu_grf>;
+ volt-mem-read-margin = <
+ 855000 1
+ 765000 2
+ 675000 3
+ 495000 4
+ >;
+ low-volt-mem-read-margin = <4>;
+ intermediate-threshold-freq = <400000>; /* KHz */
+
+ rockchip,temp-hysteresis = <5000>;
+ rockchip,low-temp = <10000>;
+ rockchip,low-temp-min-volt = <750000>;
+ rockchip,high-temp = <85000>;
+ rockchip,high-temp-max-freq = <800000>;
+
+ opp-300000000 {
+ opp-hz = /bits/ 64 <300000000>;
+ opp-microvolt = <675000 675000 850000>;
+ };
+ opp-400000000 {
+ opp-hz = /bits/ 64 <400000000>;
+ opp-microvolt = <675000 675000 850000>;
+ };
+ opp-500000000 {
+ opp-hz = /bits/ 64 <500000000>;
+ opp-microvolt = <675000 675000 850000>;
+ };
+ opp-600000000 {
+ opp-hz = /bits/ 64 <600000000>;
+ opp-microvolt = <675000 675000 850000>;
+ };
+ opp-700000000 {
+ opp-hz = /bits/ 64 <700000000>;
+ opp-microvolt = <700000 700000 850000>;
+ opp-microvolt-L2 = <687500 687500 850000>;
+ opp-microvolt-L3 = <675000 675000 850000>;
+ opp-microvolt-L4 = <675000 675000 850000>;
+ opp-microvolt-L5 = <675000 675000 850000>;
+ };
+ opp-800000000 {
+ opp-hz = /bits/ 64 <800000000>;
+ opp-microvolt = <750000 750000 850000>;
+ opp-microvolt-L1 = <737500 737500 850000>;
+ opp-microvolt-L2 = <725000 725000 850000>;
+ opp-microvolt-L3 = <712500 712500 850000>;
+ opp-microvolt-L4 = <700000 700000 850000>;
+ opp-microvolt-L5 = <700000 700000 850000>;
+ };
+ opp-900000000 {
+ opp-hz = /bits/ 64 <900000000>;
+ opp-microvolt = <800000 800000 850000>;
+ opp-microvolt-L1 = <787500 787500 850000>;
+ opp-microvolt-L2 = <775000 775000 850000>;
+ opp-microvolt-L3 = <762500 762500 850000>;
+ opp-microvolt-L4 = <750000 750000 850000>;
+ opp-microvolt-L5 = <737500 737500 850000>;
+ };
+ opp-1000000000 {
+ opp-hz = /bits/ 64 <1000000000>;
+ opp-microvolt = <850000 850000 850000>;
+ opp-microvolt-L1 = <837500 837500 850000>;
+ opp-microvolt-L2 = <825000 825000 850000>;
+ opp-microvolt-L3 = <812500 812500 850000>;
+ opp-microvolt-L4 = <800000 800000 850000>;
+ opp-microvolt-L5 = <787500 787500 850000>;
+ };
+ };
+
+ gpu: gpu@fb000000 {
+ compatible = "rockchip,rk3588-mali", "arm,mali-valhall-csf";
+ reg = <0x0 0xfb000000 0x0 0x200000>;
+ interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH 0>;
+ interrupt-names = "job", "mmu", "gpu";
+
+ clock-names = "core", "coregroup", "stacks";
+ clocks = <&cru CLK_GPU>, <&cru CLK_GPU_COREGROUP>,
+ <&cru CLK_GPU_STACKS>;
+ assigned-clocks = <&scmi_clk SCMI_CLK_GPU>;
+ assigned-clock-rates = <200000000>;
+ power-domains = <&power RK3588_PD_GPU>;
+ operating-points-v2 = <&gpu_opp_table>;
+ #cooling-cells = <2>;
+ dynamic-power-coefficient = <2982>;
+
+ status = "disabled";
+ };
+
pmu1grf: syscon@fd58a000 {
compatible = "rockchip,rk3588-pmugrf", "syscon", "simple-mfd";
reg = <0x0 0xfd58a000 0x0 0x10000>;
@@ -3033,6 +3148,11 @@ gpio4: gpio@fec50000 {
};
};
+ gpu_grf: syscon@fd5a0000 {
+ compatible = "rockchip,rk3588-gpu-grf", "syscon";
+ reg = <0x0 0xfd5a0000 0x0 0x100>;
+ };
+
av1d: video-codec@fdc70000 {
compatible = "rockchip,rk3588-av1-vpu";
reg = <0x0 0xfdc70000 0x0 0x800>;
--
Armbian

38
patch/kernel/archive/rockchip-rk3588-6.8/1013-arm64-dts-rockchip-rk3588-rock5b-Add-GPU-node.patch
View File

@ -1,38 +0,0 @@
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
From: Boris Brezillon <boris.brezillon@collabora.com>
Date: Tue, 8 Aug 2023 12:05:22 +0200
Subject: arm64: dts: rockchip: rk3588-rock5b: Add GPU node
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
---
arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts
index 111111111111..222222222222 100644
--- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts
@@ -174,6 +174,11 @@ &cpu_l3 {
cpu-supply = <&vdd_cpu_lit_s0>;
};
+&gpu {
+ mali-supply = <&vdd_gpu_s0>;
+ status = "okay";
+};
+
&hdmi0 {
status = "okay";
};
@@ -509,6 +514,7 @@ rk806_dvs3_null: dvs3-null-pins {
regulators {
vdd_gpu_s0: vdd_gpu_mem_s0: dcdc-reg1 {
+ regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <550000>;
regulator-max-microvolt = <950000>;
--
Armbian

25
patch/kernel/archive/rockchip-rk3588-6.8/1022-arm64-dts-rockchip-support-poweroff-on-rock-5a.patch
View File

@ -1,25 +0,0 @@
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
From: amazingfate <liujianfeng1994@gmail.com>
Date: Thu, 28 Mar 2024 10:59:29 +0800
Subject: arm64: dts: rockchip: support poweroff on rock-5a
---
arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts b/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts
index 111111111111..222222222222 100644
--- a/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts
@@ -401,6 +401,8 @@ pmic@0 {
<&rk806_dvs2_null>, <&rk806_dvs3_null>;
spi-max-frequency = <1000000>;
+ system-power-controller;
+
vcc1-supply = <&vcc5v0_sys>;
vcc2-supply = <&vcc5v0_sys>;
vcc3-supply = <&vcc5v0_sys>;
--
Armbian

318
patch/kernel/archive/rockchip-rk3588-6.8/1031-Add-missing-nodes-to-Orange-Pi-5.patch
View File

@ -1,318 +0,0 @@
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
From: Muhammed Efe Cetin <efectn@protonmail.com>
Date: Thu, 16 Nov 2023 18:09:07 +0300
Subject: arm64: dts: Add missing nodes to Orange Pi 5
---
arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5.dts | 203 +++++++++-
1 file changed, 201 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5.dts b/arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5.dts
index 111111111111..222222222222 100644
--- a/arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5.dts
@@ -6,6 +6,8 @@
#include <dt-bindings/leds/common.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/pinctrl/rockchip.h>
+#include <dt-bindings/usb/pd.h>
+#include <dt-bindings/soc/rockchip,vop2.h>
#include "rk3588s.dtsi"
/ {
@@ -47,6 +49,40 @@ led-1 {
};
};
+ analog-sound {
+ compatible = "simple-audio-card";
+ pinctrl-names = "default";
+ pinctrl-0 = <&hp_detect>;
+ simple-audio-card,name = "Orange Pi 5 Audio";
+ simple-audio-card,bitclock-master = <&masterdai>;
+ simple-audio-card,format = "i2s";
+ simple-audio-card,frame-master = <&masterdai>;
+ simple-audio-card,hp-det-gpio = <&gpio1 RK_PD5 GPIO_ACTIVE_LOW>;
+ simple-audio-card,mclk-fs = <256>;
+ simple-audio-card,pin-switches = "Headphones", "Speaker";
+ simple-audio-card,routing =
+ "Headphones", "LOUT1",
+ "Headphones", "ROUT1",
+ "LINPUT1", "Onboard Microphone",
+ "RINPUT1", "Onboard Microphone",
+ "LINPUT2", "Microphone Jack",
+ "RINPUT2", "Microphone Jack";
+ simple-audio-card,widgets =
+ "Microphone", "Microphone Jack",
+ "Microphone", "Onboard Microphone",
+ "Headphone", "Headphones",
+ "Speaker", "Speaker";
+
+ simple-audio-card,cpu {
+ sound-dai = <&i2s1_8ch>;
+ };
+
+ masterdai: simple-audio-card,codec {
+ sound-dai = <&es8388>;
+ system-clock-frequency = <12288000>;
+ };
+ };
+
vbus_typec: vbus-typec-regulator {
compatible = "regulator-fixed";
enable-active-high;
@@ -102,34 +138,42 @@ &combphy2_psu {
&cpu_b0 {
cpu-supply = <&vdd_cpu_big0_s0>;
+ mem-supply = <&vdd_cpu_big0_s0>;
};
&cpu_b1 {
cpu-supply = <&vdd_cpu_big0_s0>;
+ mem-supply = <&vdd_cpu_big0_s0>;
};
&cpu_b2 {
cpu-supply = <&vdd_cpu_big1_s0>;
+ mem-supply = <&vdd_cpu_big1_s0>;
};
&cpu_b3 {
cpu-supply = <&vdd_cpu_big1_s0>;
+ mem-supply = <&vdd_cpu_big1_s0>;
};
&cpu_l0 {
cpu-supply = <&vdd_cpu_lit_s0>;
+ mem-supply = <&vdd_cpu_lit_mem_s0>;
};
&cpu_l1 {
cpu-supply = <&vdd_cpu_lit_s0>;
+ mem-supply = <&vdd_cpu_lit_mem_s0>;
};
&cpu_l2 {
cpu-supply = <&vdd_cpu_lit_s0>;
+ mem-supply = <&vdd_cpu_lit_mem_s0>;
};
&cpu_l3 {
cpu-supply = <&vdd_cpu_lit_s0>;
+ mem-supply = <&vdd_cpu_lit_mem_s0>;
};
&gmac1 {
@@ -223,6 +267,80 @@ hym8563: rtc@51 {
interrupts = <RK_PB0 IRQ_TYPE_LEVEL_LOW>;
wakeup-source;
};
+
+ es8388: audio-codec@10 {
+ compatible = "everest,es8388";
+ reg = <0x10>;
+ clocks = <&cru I2S1_8CH_MCLKOUT>;
+ assigned-clocks = <&cru I2S1_8CH_MCLKOUT>;
+ assigned-clock-rates = <12288000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2s1m0_mclk>;
+ #sound-dai-cells = <0>;
+ };
+
+ usbc0: usb-typec@22 {
+ compatible = "fcs,fusb302";
+ reg = <0x22>;
+ interrupt-parent = <&gpio0>;
+ interrupts = <RK_PD3 IRQ_TYPE_LEVEL_LOW>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&usbc0_int>;
+ vbus-supply = <&vbus_typec>;
+
+ usb_con: connector {
+ compatible = "usb-c-connector";
+ label = "USB-C";
+ data-role = "dual";
+ power-role = "dual";
+ try-power-role = "source";
+ op-sink-microwatt = <1000000>;
+ sink-pdos = <PDO_FIXED(5000, 1000, PDO_FIXED_USB_COMM)>;
+ source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ usbc0_hs: endpoint {
+ remote-endpoint = <&usb_host0_xhci_drd_sw>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ usbc0_ss: endpoint {
+ remote-endpoint = <&usbdp_phy0_typec_ss>;
+ };
+ };
+
+ port@2 {
+ reg = <2>;
+ usbc0_sbu: endpoint {
+ remote-endpoint = <&usbdp_phy0_typec_sbu>;
+ };
+ };
+ };
+ };
+ };
+};
+
+&i2s1_8ch {
+ rockchip,i2s-tx-route = <3 2 1 0>;
+ rockchip,i2s-rx-route = <1 3 2 0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2s1m0_sclk
+ &i2s1m0_lrck
+ &i2s1m0_sdi1
+ &i2s1m0_sdo3>;
+ status = "okay";
+};
+
+&gpu {
+ mali-supply = <&vdd_gpu_s0>;
+ status = "okay";
};
&mdio1 {
@@ -263,6 +381,12 @@ typec5v_pwren: typec5v-pwren {
rockchip,pins = <3 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
+
+ sound {
+ hp_detect: hp-detect {
+ rockchip,pins = <1 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
};
&saradc {
@@ -336,7 +460,7 @@ pmic@0 {
#gpio-cells = <2>;
rk806_dvs1_null: dvs1-null-pins {
- pins = "gpio_pwrctrl2";
+ pins = "gpio_pwrctrl1";
function = "pin_fun0";
};
@@ -364,7 +488,7 @@ regulator-state-mem {
};
};
- vdd_cpu_lit_s0: dcdc-reg2 {
+ vdd_cpu_lit_s0: vdd_cpu_lit_mem_s0: dcdc-reg2 {
regulator-name = "vdd_cpu_lit_s0";
regulator-always-on;
regulator-boot-on;
@@ -625,6 +749,14 @@ &tsadc {
status = "okay";
};
+&u2phy0 {
+ status = "okay";
+};
+
+&u2phy0_otg {
+ status = "okay";
+};
+
&u2phy2 {
status = "okay";
};
@@ -650,10 +782,48 @@ &usb_host0_ehci {
status = "okay";
};
+&usbdp_phy0 {
+ orientation-switch;
+ mode-switch;
+ sbu1-dc-gpios = <&gpio4 RK_PA5 GPIO_ACTIVE_HIGH>;
+ sbu2-dc-gpios = <&gpio4 RK_PA7 GPIO_ACTIVE_HIGH>;
+ status = "okay";
+
+ port {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ usbdp_phy0_typec_ss: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&usbc0_ss>;
+ };
+
+ usbdp_phy0_typec_sbu: endpoint@1 {
+ reg = <1>;
+ remote-endpoint = <&usbc0_sbu>;
+ };
+ };
+};
+
&usb_host0_ohci {
status = "okay";
};
+&usb_host0_xhci {
+ usb-role-switch;
+ role-switch-default-mode = "host";
+ status = "okay";
+
+ port {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ usb_host0_xhci_drd_sw: endpoint {
+ remote-endpoint = <&usbc0_hs>;
+ };
+ };
+};
+
&usb_host1_ehci {
status = "okay";
};
@@ -665,3 +835,32 @@ &usb_host1_ohci {
&usb_host2_xhci {
status = "okay";
};
+
+&hdptxphy_hdmi0 {
+ status = "okay";
+};
+
+&hdmi0 {
+ status = "okay";
+};
+
+&hdmi0_in {
+ hdmi0_in_vp0: endpoint {
+ remote-endpoint = <&vp0_out_hdmi0>;
+ };
+};
+
+&vop_mmu {
+ status = "okay";
+};
+
+&vop {
+ status = "okay";
+};
+
+&vp0 {
+ vp0_out_hdmi0: endpoint@ROCKCHIP_VOP2_EP_HDMI0 {
+ reg = <ROCKCHIP_VOP2_EP_HDMI0>;
+ remote-endpoint = <&hdmi0_in_vp0>;
+ };
+};
--
Armbian

1464
patch/kernel/archive/rockchip-rk3588-6.8/1040-board-khadas-edge2-add-nodes.patch
View File

File diff suppressed because it is too large Load Diff

30
patch/kernel/archive/rockchip-rk3588-6.8/1047-fix-initial-PERST#-GPIO-value.patch
View File

@ -1,30 +0,0 @@
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
From: yangchaohong <45483831+yangchaohong@users.noreply.github.com>
Date: Wed, 1 May 2024 08:30:43 +0100
Subject: [ARCHEOLOGY] Fix PCIe for RK35xx+Fix ROCK5A PCIe device tree
> X-Git-Archeology: - Revision b1f648ee755de73a922a33d6a432f310ea4ff3e0: https://github.com/armbian/build/commit/b1f648ee755de73a922a33d6a432f310ea4ff3e0
> X-Git-Archeology: Date: Wed, 01 May 2024 08:30:43 +0100
> X-Git-Archeology: From: yangchaohong <45483831+yangchaohong@users.noreply.github.com>
> X-Git-Archeology: Subject: Fix PCIe for RK35xx+Fix ROCK5A PCIe device tree
> X-Git-Archeology:
---
drivers/pci/controller/dwc/pcie-dw-rockchip.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/pci/controller/dwc/pcie-dw-rockchip.c b/drivers/pci/controller/dwc/pcie-dw-rockchip.c
index 111111111111..222222222222 100644
--- a/drivers/pci/controller/dwc/pcie-dw-rockchip.c
+++ b/drivers/pci/controller/dwc/pcie-dw-rockchip.c
@@ -240,7 +240,7 @@ static int rockchip_pcie_resource_get(struct platform_device *pdev,
return PTR_ERR(rockchip->apb_base);
rockchip->rst_gpio = devm_gpiod_get_optional(&pdev->dev, "reset",
- GPIOD_OUT_HIGH);
+ GPIOD_OUT_LOW);
if (IS_ERR(rockchip->rst_gpio))
return PTR_ERR(rockchip->rst_gpio);
--
Armbian