SpacemiT: Add ATF patches (OpenSBI)

Tag: 1.3 Source: https://gitee.com/bianbu-linux/opensbi Signed-off-by: Patrick Yavitz <pyavitz@armbian.com>
2024-06-25 10:37:28 -04:00 · 2024-06-25 10:37:28 -04:00 · 3440691a51
parent 93d547d52d
commit 3440691a51
5 changed files with 8580 additions and 0 deletions
--- a/patch/atf/atf-spacemit/001-v1.0alpha2.patch
+++ b/patch/atf/atf-spacemit/001-v1.0alpha2.patch
--- a/patch/atf/atf-spacemit/002-v1.0beta3.1.patch
+++ b/patch/atf/atf-spacemit/002-v1.0beta3.1.patch
--- a/patch/atf/atf-spacemit/003-v1.0rc1.patch
+++ b/patch/atf/atf-spacemit/003-v1.0rc1.patch
@ -0,0 +1,331 @@
+From 41a15ab971400502e93bbbf0d7336fa81daf25c9 Mon Sep 17 00:00:00 2001
+From: James Deng <james.deng@spacemit.com>
+Date: Tue, 30 Apr 2024 17:48:07 +0800
+Subject: [PATCH] Update for v1.0rc1
+
+---
+ include/sbi_utils/cache/cacheflush.h          | 34 +++++++++-----
+ lib/sbi/sbi_hsm.c                             |  2 +-
+ lib/utils/psci/psci_private.h                 |  2 +-
+ .../spacemit/plat/k1x/underly_implement.c     | 37 ---------------
+ lib/utils/psci/spacemit/plat/plat_pm.c        |  4 +-
+ .../generic/include/spacemit/k1x/k1x_evb.h    | 44 ++++++++++++++++-
+ .../generic/include/spacemit/k1x/k1x_fpga.h   | 47 +++++++++++++++++--
+ platform/generic/spacemit/spacemit_k1.c       | 13 +++++
+ 8 files changed, 126 insertions(+), 57 deletions(-)
+
+diff --git a/include/sbi_utils/cache/cacheflush.h b/include/sbi_utils/cache/cacheflush.h
+index c3e3532..126931b 100644
+--- a/include/sbi_utils/cache/cacheflush.h
+++ b/include/sbi_utils/cache/cacheflush.h
+@@ -167,26 +167,34 @@ static inline void __mdelay(void)
+ 		cpu_relax();
+ }
+ 
+-static inline void csi_flush_l2_cache(void)
+static inline void csi_flush_l2_cache(bool hw)
+ {
+ 	unsigned int hartid = current_hartid();
+ 
+ 	uintptr_t *cr =(MPIDR_AFFLVL1_VAL(hartid) == 0) ? (uintptr_t *)CLUSTER0_L2_CACHE_FLUSH_REG_BASE :
+ 			(uintptr_t *)CLUSTER1_L2_CACHE_FLUSH_REG_BASE;
+ 
+-	/* flush l2 cache */
+-	writel(readl(cr) | (1 << L2_CACHE_FLUSH_REQUEST_BIT_OFFSET), cr);
+-	/* k1pro */
+-	if (L2_CACHE_FLUSH_REQUEST_BIT_OFFSET == L2_CACHE_FLUSH_DONE_BIT_OFFSET)
+-		while (readl(cr) & (1 << L2_CACHE_FLUSH_DONE_BIT_OFFSET));
+-	else /* k1x */ {
+-		/* clear the request */
+-		while (1) {
+-			if ((readl(cr) & (1 << L2_CACHE_FLUSH_DONE_BIT_OFFSET)) == 0)
+-				break;
+-			__mdelay();
+	if (!hw) {
+		writel(0x0, cr);
+		/* flush l2 cache */
+		writel(readl(cr) | (1 << L2_CACHE_FLUSH_REQUEST_BIT_OFFSET), cr);
+		/* k1pro */
+		if (L2_CACHE_FLUSH_REQUEST_BIT_OFFSET == L2_CACHE_FLUSH_DONE_BIT_OFFSET)
+			while (readl(cr) & (1 << L2_CACHE_FLUSH_DONE_BIT_OFFSET));
+		else /* k1x */ {
+			/* clear the request */
+			while (1) {
+				if ((readl(cr) & (1 << L2_CACHE_FLUSH_DONE_BIT_OFFSET)) == 0)
+					break;
+				__mdelay();
+			}
+			writel(readl(cr) & ~(1 << L2_CACHE_FLUSH_REQUEST_BIT_OFFSET), cr);
+ 		}
+-		writel(readl(cr) & ~(1 << L2_CACHE_FLUSH_REQUEST_BIT_OFFSET), cr);
+	} else {
+		/* k1pro */
+		if (L2_CACHE_FLUSH_REQUEST_BIT_OFFSET == L2_CACHE_FLUSH_DONE_BIT_OFFSET)
+			return /* do nothing */;
+		writel((1 << L2_CACHE_FLUSH_HW_TYPE_BIT_OFFSET) | (1 << L2_CACHE_FLUSH_HW_EN_BIT_OFFSET), cr);
+ 	}
+ }
+ #endif
+diff --git a/lib/sbi/sbi_hsm.c b/lib/sbi/sbi_hsm.c
+index acd3c9e..51c982a 100644
+--- a/lib/sbi/sbi_hsm.c
+++ b/lib/sbi/sbi_hsm.c
+@@ -183,7 +183,7 @@ void __noreturn sbi_hsm_hart_start_finish(struct sbi_scratch *scratch,
+ 	 * */
+ 	if (cool_boot) {
+ 		csi_flush_dcache_all();
+-		csi_flush_l2_cache();
+		csi_flush_l2_cache(0);
+ 	}
+ 
+ 	sbi_hart_switch_mode(hartid, next_arg1, next_addr, next_mode, false);
+diff --git a/lib/utils/psci/psci_private.h b/lib/utils/psci/psci_private.h
+index c768d3f..0a3f260 100644
+--- a/lib/utils/psci/psci_private.h
+++ b/lib/utils/psci/psci_private.h
+@@ -182,7 +182,7 @@ static inline void psci_do_pwrdown_cache_maintenance(int hartid, uintptr_t scrat
+ 		/* disable the tcm */
+ 		csr_write(CSR_TCMCFG, 0);
+ #endif
+-		csi_flush_l2_cache();
+		csi_flush_l2_cache(0);
+ 	}
+ 
+ 	/* disable dcache */
+diff --git a/lib/utils/psci/spacemit/plat/k1x/underly_implement.c b/lib/utils/psci/spacemit/plat/k1x/underly_implement.c
+index 279e6d5..73feec4 100644
+--- a/lib/utils/psci/spacemit/plat/k1x/underly_implement.c
+++ b/lib/utils/psci/spacemit/plat/k1x/underly_implement.c
+@@ -5,43 +5,6 @@
+ #include <sbi/sbi_console.h>
+ #include <spacemit/spacemit_config.h>
+ 
+-#define C1_CPU_RESET_BASE_ADDR		(0xD4282B24)
+-
+-#define PMU_CAP_CORE0_IDLE_CFG		(0xd4282924)
+-#define PMU_CAP_CORE1_IDLE_CFG		(0xd4282928)
+-#define PMU_CAP_CORE2_IDLE_CFG		(0xd4282960)
+-#define PMU_CAP_CORE3_IDLE_CFG		(0xd4282964)
+-#define PMU_CAP_CORE4_IDLE_CFG		(0xd4282b04)
+-#define PMU_CAP_CORE5_IDLE_CFG		(0xd4282b08)
+-#define PMU_CAP_CORE6_IDLE_CFG		(0xd4282b0c)
+-#define PMU_CAP_CORE7_IDLE_CFG		(0xd4282b10)
+-
+-#define PMU_C0_CAPMP_IDLE_CFG0		(0xd4282920)
+-#define PMU_C0_CAPMP_IDLE_CFG1		(0xd42828e4)
+-#define PMU_C0_CAPMP_IDLE_CFG2		(0xd4282950)
+-#define PMU_C0_CAPMP_IDLE_CFG3		(0xd4282954)
+-#define PMU_C1_CAPMP_IDLE_CFG0		(0xd4282b14)
+-#define PMU_C1_CAPMP_IDLE_CFG1		(0xd4282b18)
+-#define PMU_C1_CAPMP_IDLE_CFG2		(0xd4282b1c)
+-#define PMU_C1_CAPMP_IDLE_CFG3		(0xd4282b20)
+-
+-#define PMU_ACPR_CLUSTER0_REG		(0xd4051090)
+-#define PMU_ACPR_CLUSTER1_REG		(0xd4051094)
+-#define PMU_ACPR_UNKONW_REG		(0xd4050038)
+-
+-
+-#define CPU_PWR_DOWN_VALUE		(0x3)
+-#define CLUSTER_PWR_DOWN_VALUE		(0x3)
+-#define CLUSTER_AXISDO_OFFSET		(31)
+-#define CLUSTER_DDRSD_OFFSET		(27)
+-#define CLUSTER_APBSD_OFFSET		(26)
+-#define CLUSTER_VCXOSD_OFFSET		(19)
+-#define CLUSTER_BIT29_OFFSET		(29)
+-#define CLUSTER_BIT14_OFFSET		(14)
+-#define CLUSTER_BIT30_OFFSET		(30)
+-#define CLUSTER_BIT25_OFFSET		(25)
+-#define CLUSTER_BIT13_OFFSET		(13)
+-
+ struct pmu_cap_wakeup {
+ 	unsigned int pmu_cap_core0_wakeup;
+ 	unsigned int pmu_cap_core1_wakeup;
+diff --git a/lib/utils/psci/spacemit/plat/plat_pm.c b/lib/utils/psci/spacemit/plat/plat_pm.c
+index da6f958..a5b9127 100644
+--- a/lib/utils/psci/spacemit/plat/plat_pm.c
+++ b/lib/utils/psci/spacemit/plat/plat_pm.c
+@@ -7,6 +7,7 @@
+ #include <sbi/sbi_console.h>
+ #include <sbi_utils/psci/plat/arm/common/arm_def.h>
+ #include <sbi_utils/irqchip/fdt_irqchip_plic.h>
+#include <sbi_utils/cache/cacheflush.h>
+ #include "underly_implement.h"
+ 
+ #define CORE_PWR_STATE(state) \
+@@ -81,6 +82,7 @@ static void spacemit_pwr_domain_off(const psci_power_state_t *target_state)
+ #endif
+                 cci_disable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(hartid));
+                 spacemit_cluster_off(hartid);
+		csi_flush_l2_cache(1);
+         }
+ 
+ 	if (SYSTEM_PWR_STATE(target_state) == ARM_LOCAL_STATE_OFF) {
+@@ -180,8 +182,8 @@ static void spacemit_pwr_domain_suspend(const psci_power_state_t *target_state)
+ 		csr_write(CSR_TCMCFG, 0);
+ #endif
+ 		cci_disable_snoop_dvm_reqs(clusterid);
+-
+ 		spacemit_cluster_off(hartid);
+		csi_flush_l2_cache(1);
+ 	}
+ 
+ 	if (SYSTEM_PWR_STATE(target_state) == ARM_LOCAL_STATE_OFF) {
+diff --git a/platform/generic/include/spacemit/k1x/k1x_evb.h b/platform/generic/include/spacemit/k1x/k1x_evb.h
+index b951105..5f5b672 100644
+--- a/platform/generic/include/spacemit/k1x/k1x_evb.h
+++ b/platform/generic/include/spacemit/k1x/k1x_evb.h
+@@ -24,6 +24,45 @@
+ #define C1_RVBADDR_LO_ADDR          (0xD4282C00 + 0x2B0)
+ #define C1_RVBADDR_HI_ADDR          (0xD4282C00 + 0X2B4)
+ 
+#define C1_CPU_RESET_BASE_ADDR		(0xD4282B24)
+
+#define PMU_CAP_CORE0_IDLE_CFG		(0xd4282924)
+#define PMU_CAP_CORE1_IDLE_CFG		(0xd4282928)
+#define PMU_CAP_CORE2_IDLE_CFG		(0xd4282960)
+#define PMU_CAP_CORE3_IDLE_CFG		(0xd4282964)
+#define PMU_CAP_CORE4_IDLE_CFG		(0xd4282b04)
+#define PMU_CAP_CORE5_IDLE_CFG		(0xd4282b08)
+#define PMU_CAP_CORE6_IDLE_CFG		(0xd4282b0c)
+#define PMU_CAP_CORE7_IDLE_CFG		(0xd4282b10)
+
+#define PMU_C0_CAPMP_IDLE_CFG0		(0xd4282920)
+#define PMU_C0_CAPMP_IDLE_CFG1		(0xd42828e4)
+#define PMU_C0_CAPMP_IDLE_CFG2		(0xd4282950)
+#define PMU_C0_CAPMP_IDLE_CFG3		(0xd4282954)
+#define PMU_C1_CAPMP_IDLE_CFG0		(0xd4282b14)
+#define PMU_C1_CAPMP_IDLE_CFG1		(0xd4282b18)
+#define PMU_C1_CAPMP_IDLE_CFG2		(0xd4282b1c)
+#define PMU_C1_CAPMP_IDLE_CFG3		(0xd4282b20)
+
+#define PMU_ACPR_CLUSTER0_REG		(0xd4051090)
+#define PMU_ACPR_CLUSTER1_REG		(0xd4051094)
+#define PMU_ACPR_UNKONW_REG		(0xd4050038)
+
+
+#define CPU_PWR_DOWN_VALUE		(0x3)
+#define CLUSTER_PWR_DOWN_VALUE		(0x3)
+#define CLUSTER_AXISDO_OFFSET		(31)
+#define CLUSTER_DDRSD_OFFSET		(27)
+#define CLUSTER_APBSD_OFFSET		(26)
+#define CLUSTER_VCXOSD_OFFSET		(19)
+#define CLUSTER_BIT29_OFFSET		(29)
+#define CLUSTER_BIT14_OFFSET		(14)
+#define CLUSTER_BIT30_OFFSET		(30)
+#define CLUSTER_BIT25_OFFSET		(25)
+#define CLUSTER_BIT13_OFFSET		(13)
+
+#define L2_HARDWARE_CACHE_FLUSH_EN	(13)
+
+ /***************************mailbox***************************/
+ #define SCMI_MAILBOX_SHARE_MEM		(0x2f902080)
+ #define PLAT_MAILBOX_REG_BASE		(0x2f824000)
+@@ -66,7 +105,10 @@
+ #define CLUSTER0_L2_CACHE_FLUSH_REG_BASE	(0xD84401B0)
+ #define CLUSTER1_L2_CACHE_FLUSH_REG_BASE	(0xD84401B4)
+ 
+-#define L2_CACHE_FLUSH_REQUEST_BIT_OFFSET	(0x1)
+#define L2_CACHE_FLUSH_REQUEST_BIT_OFFSET	(0x1) /* sw flush l2 cache */
+ #define L2_CACHE_FLUSH_DONE_BIT_OFFSET		(0x3)
+ 
+#define L2_CACHE_FLUSH_HW_TYPE_BIT_OFFSET	(0)
+#define L2_CACHE_FLUSH_HW_EN_BIT_OFFSET		(0x2)
+
+ #endif /* __K1X_EVB_CONFIG_H__ */
+diff --git a/platform/generic/include/spacemit/k1x/k1x_fpga.h b/platform/generic/include/spacemit/k1x/k1x_fpga.h
+index 4748c86..3d8964c 100644
+--- a/platform/generic/include/spacemit/k1x/k1x_fpga.h
+++ b/platform/generic/include/spacemit/k1x/k1x_fpga.h
+@@ -24,13 +24,51 @@
+ #define C1_RVBADDR_LO_ADDR          (0xD4282C00 + 0x2B0)
+ #define C1_RVBADDR_HI_ADDR          (0xD4282C00 + 0X2B4)
+ 
+#define C1_CPU_RESET_BASE_ADDR		(0xD4282B24)
+
+#define PMU_CAP_CORE0_IDLE_CFG		(0xd4282924)
+#define PMU_CAP_CORE1_IDLE_CFG		(0xd4282928)
+#define PMU_CAP_CORE2_IDLE_CFG		(0xd4282960)
+#define PMU_CAP_CORE3_IDLE_CFG		(0xd4282964)
+#define PMU_CAP_CORE4_IDLE_CFG		(0xd4282b04)
+#define PMU_CAP_CORE5_IDLE_CFG		(0xd4282b08)
+#define PMU_CAP_CORE6_IDLE_CFG		(0xd4282b0c)
+#define PMU_CAP_CORE7_IDLE_CFG		(0xd4282b10)
+
+#define PMU_C0_CAPMP_IDLE_CFG0		(0xd4282920)
+#define PMU_C0_CAPMP_IDLE_CFG1		(0xd42828e4)
+#define PMU_C0_CAPMP_IDLE_CFG2		(0xd4282950)
+#define PMU_C0_CAPMP_IDLE_CFG3		(0xd4282954)
+#define PMU_C1_CAPMP_IDLE_CFG0		(0xd4282b14)
+#define PMU_C1_CAPMP_IDLE_CFG1		(0xd4282b18)
+#define PMU_C1_CAPMP_IDLE_CFG2		(0xd4282b1c)
+#define PMU_C1_CAPMP_IDLE_CFG3		(0xd4282b20)
+
+#define PMU_ACPR_CLUSTER0_REG		(0xd4051090)
+#define PMU_ACPR_CLUSTER1_REG		(0xd4051094)
+#define PMU_ACPR_UNKONW_REG		(0xd4050038)
+
+
+#define CPU_PWR_DOWN_VALUE		(0x3)
+#define CLUSTER_PWR_DOWN_VALUE		(0x3)
+#define CLUSTER_AXISDO_OFFSET		(31)
+#define CLUSTER_DDRSD_OFFSET		(27)
+#define CLUSTER_APBSD_OFFSET		(26)
+#define CLUSTER_VCXOSD_OFFSET		(19)
+#define CLUSTER_BIT29_OFFSET		(29)
+#define CLUSTER_BIT14_OFFSET		(14)
+#define CLUSTER_BIT30_OFFSET		(30)
+#define CLUSTER_BIT25_OFFSET		(25)
+#define CLUSTER_BIT13_OFFSET		(13)
+
+#define L2_HARDWARE_CACHE_FLUSH_EN	(13)
+
+ /***************************mailbox***************************/
+ #define SCMI_MAILBOX_SHARE_MEM		(0x2f902080)
+ #define PLAT_MAILBOX_REG_BASE		(0x2f824000)
+ 
+ /****************************scmi*****************************/
+-#define PLAT_SCMI_SINGLE_CLUSTER_DOMAIN_MAP     {0, 1, 2, 3}
+-#define PLAT_SCMI_DOUBLE_CLUSTER_DOMAIN_MAP     {0, 1, 4, 5}
+#define PLAT_SCMI_DOMAIN_MAP		{0, 1, 2, 3}
+ 
+ /*************************cpu topology************************/
+ #define ARM_SYSTEM_COUNT		(1U)
+@@ -67,7 +105,10 @@
+ #define CLUSTER0_L2_CACHE_FLUSH_REG_BASE	(0xD84401B0)
+ #define CLUSTER1_L2_CACHE_FLUSH_REG_BASE	(0xD84401B4)
+ 
+-#define L2_CACHE_FLUSH_REQUEST_BIT_OFFSET	(0x1)
+#define L2_CACHE_FLUSH_REQUEST_BIT_OFFSET	(0x1) /* sw flush l2 cache */
+ #define L2_CACHE_FLUSH_DONE_BIT_OFFSET		(0x3)
+ 
+#define L2_CACHE_FLUSH_HW_TYPE_BIT_OFFSET	(0)
+#define L2_CACHE_FLUSH_HW_EN_BIT_OFFSET		(0x2)
+
+ #endif /* __K1X_FPGA_CONFIG_H__ */
+diff --git a/platform/generic/spacemit/spacemit_k1.c b/platform/generic/spacemit/spacemit_k1.c
+index 38794c2..9521884 100644
+--- a/platform/generic/spacemit/spacemit_k1.c
+++ b/platform/generic/spacemit/spacemit_k1.c
+@@ -65,6 +65,19 @@ static void wakeup_other_core(void)
+ 	unsigned char *cpu_topology = plat_get_power_domain_tree_desc();
+ #endif
+ 
+#if defined(CONFIG_PLATFORM_SPACEMIT_K1X)
+	/* enable the hw l2 cache flush method for each core */
+	writel(readl((u32 *)PMU_C0_CAPMP_IDLE_CFG0) | (1 << L2_HARDWARE_CACHE_FLUSH_EN), (u32 *)PMU_C0_CAPMP_IDLE_CFG0);
+	writel(readl((u32 *)PMU_C0_CAPMP_IDLE_CFG1) | (1 << L2_HARDWARE_CACHE_FLUSH_EN), (u32 *)PMU_C0_CAPMP_IDLE_CFG1);
+	writel(readl((u32 *)PMU_C0_CAPMP_IDLE_CFG2) | (1 << L2_HARDWARE_CACHE_FLUSH_EN), (u32 *)PMU_C0_CAPMP_IDLE_CFG2);
+	writel(readl((u32 *)PMU_C0_CAPMP_IDLE_CFG3) | (1 << L2_HARDWARE_CACHE_FLUSH_EN), (u32 *)PMU_C0_CAPMP_IDLE_CFG3);
+
+	writel(readl((u32 *)PMU_C1_CAPMP_IDLE_CFG0) | (1 << L2_HARDWARE_CACHE_FLUSH_EN), (u32 *)PMU_C1_CAPMP_IDLE_CFG0);
+	writel(readl((u32 *)PMU_C1_CAPMP_IDLE_CFG1) | (1 << L2_HARDWARE_CACHE_FLUSH_EN), (u32 *)PMU_C1_CAPMP_IDLE_CFG1);
+	writel(readl((u32 *)PMU_C1_CAPMP_IDLE_CFG2) | (1 << L2_HARDWARE_CACHE_FLUSH_EN), (u32 *)PMU_C1_CAPMP_IDLE_CFG2);
+	writel(readl((u32 *)PMU_C1_CAPMP_IDLE_CFG3) | (1 << L2_HARDWARE_CACHE_FLUSH_EN), (u32 *)PMU_C1_CAPMP_IDLE_CFG3);
+#endif
+
+ 	// hart0 is already boot up
+ 	for (i = 0; i < platform.hart_count; i++) {
+ 		hartid = platform.hart_index2id[i];
+-- 
+2.39.2
+
--- a/patch/atf/atf-spacemit/004-v1.0.patch
+++ b/patch/atf/atf-spacemit/004-v1.0.patch
@ -0,0 +1,42 @@
+From ce6e8eec55a62d9e4cb5f5a767e50e9d0c2659ff Mon Sep 17 00:00:00 2001
+From: James Deng <james.deng@spacemit.com>
+Date: Thu, 30 May 2024 23:19:43 +0800
+Subject: [PATCH] Update for v1.0
+
+---
+ debian/opensbi-spacemit.postinst | 9 ++++++++-
+ 1 file changed, 8 insertions(+), 1 deletion(-)
+
+diff --git a/debian/opensbi-spacemit.postinst b/debian/opensbi-spacemit.postinst
+index 1f6feca..9ce082e 100755
+--- a/debian/opensbi-spacemit.postinst
+++ b/debian/opensbi-spacemit.postinst
+@@ -22,9 +22,16 @@ configure)
+         case $ROOT in
+         "/dev/mmcblk0"*)
+             OPENSBI=/dev/mmcblk0p3
+            OPENSBI_SEEK=0
+             ;;
+         "/dev/mmcblk2"*)
+             OPENSBI=/dev/mmcblk2p3
+            OPENSBI_SEEK=0
+            ;;
+        "/dev/nvme0n1"*)
+            OPENSBI=/dev/mtdblock0
+            # 以KB为单位
+            OPENSBI_SEEK=448
+             ;;
+         *)
+             echo "Unsupported root=$ROOT"
+@@ -37,7 +44,7 @@ configure)
+     fi
+ 
+     if [ -n "$target" ] && [ -e $OPENSBI ]; then
+-        dd if=/usr/lib/riscv64-linux-gnu/opensbi/generic/fw_dynamic.itb of=$OPENSBI bs=1 && sync
+        dd if=/usr/lib/riscv64-linux-gnu/opensbi/generic/fw_dynamic.itb of=$OPENSBI seek=$OPENSBI_SEEK bs=1K && sync
+     fi
+     ;;
+ esac
+-- 
+2.39.2
+
--- a/patch/atf/atf-spacemit/005-v1.0.3.patch
+++ b/patch/atf/atf-spacemit/005-v1.0.3.patch
@ -0,0 +1,86 @@
+From 6f1344573d4ce0638d24d960e9a7d5ff1b0426b6 Mon Sep 17 00:00:00 2001
+From: James Deng <james.deng@spacemit.com>
+Date: Wed, 19 Jun 2024 15:18:09 +0800
+Subject: [PATCH] Update for v1.0.3
+
+---
+ .../spacemit/plat/k1x/underly_implement.c     | 24 ++++++++++++++++++-
+ .../generic/include/spacemit/k1x/k1x_evb.h    |  4 ++--
+ 2 files changed, 25 insertions(+), 3 deletions(-)
+
+diff --git a/lib/utils/psci/spacemit/plat/k1x/underly_implement.c b/lib/utils/psci/spacemit/plat/k1x/underly_implement.c
+index 73feec4..654da2d 100644
+--- a/lib/utils/psci/spacemit/plat/k1x/underly_implement.c
+++ b/lib/utils/psci/spacemit/plat/k1x/underly_implement.c
+@@ -44,6 +44,12 @@ void spacemit_top_on(u_register_t mpidr)
+ 		(1 << CLUSTER_BIT25_OFFSET) |
+ 		(1 << CLUSTER_BIT13_OFFSET));
+ 	writel(value, cluster1_acpr);
+
+	/* enable the gpio edge detected function again
+	 * */
+	value = readl((unsigned int *)0xd4051000);
+	value &= ~(1 << 21);
+	writel(value, (unsigned int *)0xd4051000);
+ }
+ 
+ /* D1P & D2 ? */
+@@ -60,6 +66,7 @@ void spacemit_top_off(u_register_t mpidr)
+ 		(1 << CLUSTER_DDRSD_OFFSET) |
+ 		(1 << CLUSTER_APBSD_OFFSET) |
+ 		(1 << CLUSTER_VCXOSD_OFFSET) |
+		(1 << 3) |
+ 		(1 << CLUSTER_BIT29_OFFSET) |
+ 		(1 << CLUSTER_BIT14_OFFSET) |
+ 		(1 << CLUSTER_BIT30_OFFSET) |
+@@ -72,6 +79,7 @@ void spacemit_top_off(u_register_t mpidr)
+ 		(1 << CLUSTER_DDRSD_OFFSET) |
+ 		(1 << CLUSTER_APBSD_OFFSET) |
+ 		(1 << CLUSTER_VCXOSD_OFFSET) |
+		(1 << 3) |
+ 		(1 << CLUSTER_BIT29_OFFSET) |
+ 		(1 << CLUSTER_BIT14_OFFSET) |
+ 		(1 << CLUSTER_BIT30_OFFSET) |
+@@ -80,9 +88,23 @@ void spacemit_top_off(u_register_t mpidr)
+ 	writel(value, cluster1_acpr);
+ 
+ 	value = readl((unsigned int *)PMU_ACPR_UNKONW_REG);
+-	value |= (1 << 2);
+	value |= (1 << 2) | (1 << 0);
+ 	writel(value, (unsigned int *)PMU_ACPR_UNKONW_REG);
+ 
+	/* disable the gpio edge detect function
+	 * this may cause the system cann't enter D2
+	 * */
+	value = readl((unsigned int *)0xd4051000);
+	value |= (1 << 21);
+	writel(value, (unsigned int *)0xd4051000);
+
+	/* enable the refbuf function which will enhance the
+	 * driving capability of the internal 26M to PLL path
+	 * */
+	value = readl((unsigned int *)0xd4090104);
+	value |= (1 << 22);
+	writel(value, (unsigned int *)0xd4090104);
+
+ 	/* for wakeup debug */
+ 	writel(0xffff, (unsigned int *)0xd4051030);
+ }
+diff --git a/platform/generic/include/spacemit/k1x/k1x_evb.h b/platform/generic/include/spacemit/k1x/k1x_evb.h
+index 5f5b672..10e8569 100644
+--- a/platform/generic/include/spacemit/k1x/k1x_evb.h
+++ b/platform/generic/include/spacemit/k1x/k1x_evb.h
+@@ -49,8 +49,8 @@
+ #define PMU_ACPR_UNKONW_REG		(0xd4050038)
+ 
+ 
+-#define CPU_PWR_DOWN_VALUE		(0x3)
+-#define CLUSTER_PWR_DOWN_VALUE		(0x3)
+#define CPU_PWR_DOWN_VALUE		(0x1b)
+#define CLUSTER_PWR_DOWN_VALUE		(0x7)
+ #define CLUSTER_AXISDO_OFFSET		(31)
+ #define CLUSTER_DDRSD_OFFSET		(27)
+ #define CLUSTER_APBSD_OFFSET		(26)
+-- 
+2.39.2
+