JIRA: https://issues.redhat.com/browse/RHEL-67693
Upstream Status: 22a9120479a40a56c13c5e473a0100fad2e017c0
commit 22a9120479a40a56c13c5e473a0100fad2e017c0
Author: Siddharth Vadapalli <s-vadapalli@ti.com>
Date: Mon Nov 4 13:14:20 2024 +0530
PCI: j721e: Deassert PERST# after a delay of PCIE_T_PVPERL_MS milliseconds
According to Section 2.2 of the PCI Express Card Electromechanical
Specification (Revision 5.1), in order to ensure that the power and the
reference clock are stable, PERST# has to be deasserted after a delay of
100 milliseconds (TPVPERL).
Currently, it is being assumed that the power is already stable, which
is not necessarily true.
Hence, change the delay to PCIE_T_PVPERL_MS to guarantee that power and
reference clock are stable.
Fixes:
|
||
---|---|---|
.. | ||
Kconfig | ||
Makefile | ||
pci-j721e.c | ||
pcie-cadence-ep.c | ||
pcie-cadence-host.c | ||
pcie-cadence-plat.c | ||
pcie-cadence.c | ||
pcie-cadence.h |