Commit Graph

2 Commits

Author SHA1 Message Date
Al Stone 77777491c9 gpio: Bulk conversion to generic_handle_domain_irq()
Bugzilla: https://bugzilla.redhat.com/show_bug.cgi?id=2071835
Tested: This is one of a series of patch sets to enable Arm SystemReady IR
 support in the kernel for NXP i.MX8 platforms.  This set updates GPIO
 support.  It has been tested via simple boot tests and by using the
 kernel GPIO tools to verify pins are being identified and can be used.

commit dbd1c54fc82051bf7f3271b43517281f5b2cff51
Author: Marc Zyngier <maz@kernel.org>
Date:   Tue May 4 17:42:18 2021 +0100

    gpio: Bulk conversion to generic_handle_domain_irq()

    Wherever possible, replace constructs that match either
    generic_handle_irq(irq_find_mapping()) or
    generic_handle_irq(irq_linear_revmap()) to a single call to
    generic_handle_domain_irq().

    Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
    Acked-by: Linus Walleij <linus.walleij@linaro.org>
    Signed-off-by: Marc Zyngier <maz@kernel.org>
    (cherry picked from commit dbd1c54fc82051bf7f3271b43517281f5b2cff51)

Signed-off-by: Al Stone <ahs3@redhat.com>
2022-08-24 13:28:24 -06:00
Sander Vanheule 0d82fb1127 gpio: Add Realtek Otto GPIO support
Realtek MIPS SoCs (platform name Otto) have GPIO controllers with up to
64 GPIOs, divided over two banks. Each bank has a set of registers for
32 GPIOs, with support for edge-triggered interrupts.

Each GPIO bank consists of four 8-bit GPIO ports (ABCD and EFGH). Most
registers pack one bit per GPIO, except for the IMR register, which
packs two bits per GPIO (AB-CD).

Although the byte order is currently assumed to have port A..D at offset
0x0..0x3, this has been observed to be reversed on other, Lexra-based,
SoCs (e.g. RTL8196E/97D/97F).

Interrupt support is disabled for the fallback devicetree-compatible
'realtek,otto-gpio'. This allows for quick support of GPIO banks in
which the byte order would be unknown. In this case, the port ordering
in the IMR registers may not match the reversed order in the other
registers (DCBA, and BA-DC or DC-BA).

Signed-off-by: Sander Vanheule <sander@svanheule.net>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com>
Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>
2021-05-05 16:07:40 +02:00