JIRA: https://issues.redhat.com/browse/RHEL-33544
Upstream Status: 6d0c39324c5fd8a788a000ab9cead1dbb2fa49a8
commit 6d0c39324c5fd8a788a000ab9cead1dbb2fa49a8
Author: Abel Vesa <abel.vesa@linaro.org>
Date: Fri Mar 1 18:59:02 2024 +0200
PCI: qcom: Add X1E80100 PCIe support
Add the compatible and the driver data for X1E80100 PCIe controller.
There are 5 controller instances found on this platform, out of which
2 are Gen3 with speeds of up to 8.0GT/s, while the other 3 are Gen4 with
speeds of up to 16GT/s.
The version of the controller is 1.38.0 for all instances, but they are
compatible with 1.9.0 config. The max link width is x8 for one
controller, x4 for two of others and x2 for the two left.
[kwilczynski: commit log]
Link: https://lore.kernel.org/linux-pci/20240301-x1e80100-pci-v4-2-7ab7e281d647@linaro.org
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>
Signed-off-by: Myron Stowe <mstowe@redhat.com>
JIRA: https://issues.redhat.com/browse/RHEL-33544
Upstream Status: bf79e33cdd89db498e00a6131e937259de5f2705
commit bf79e33cdd89db498e00a6131e937259de5f2705
Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Date: Thu Mar 7 16:35:15 2024 +0530
PCI: qcom: Enable BDF to SID translation properly
Qcom SoCs making use of ARM SMMU require BDF to SID translation table in
the driver to properly map the SID for the PCIe devices based on their BDF
identifier. This is currently achieved with the help of
qcom_pcie_config_sid_1_9_0() function for SoCs supporting the 1_9_0 config.
But With newer Qcom SoCs starting from SM8450, BDF to SID translation is
set to bypass mode by default in hardware. Due to this, the translation
table that is set in the qcom_pcie_config_sid_1_9_0() is essentially
unused and the default SID is used for all endpoints in SoCs starting from
SM8450.
This is a security concern and also warrants swapping the DeviceID in DT
while using the GIC ITS to handle MSIs from endpoints. The swapping is
currently done like below in DT when using GIC ITS:
/*
* MSIs for BDF (1:0.0) only works with Device ID 0x5980.
* Hence, the IDs are swapped.
*/
msi-map = <0x0 &gic_its 0x5981 0x1>,
<0x100 &gic_its 0x5980 0x1>;
Here, swapping of the DeviceIDs ensure that the endpoint with BDF (1:0.0)
gets the DeviceID 0x5980 which is associated with the default SID as per
the iommu mapping in DT. So MSIs were delivered with IDs swapped so far.
But this also means the Root Port (0:0.0) won't receive any MSIs (for PME,
AER etc...)
So let's fix these issues by clearing the BDF to SID bypass mode for all
SoCs making use of the 1_9_0 config. This allows the PCIe devices to use
the correct SID, thus avoiding the DeviceID swapping hack in DT and also
achieving the isolation between devices.
Fixes: 4c93988221 ("PCI: qcom: Add support for configuring BDF to SID mapping for SM8250")
Link: https://lore.kernel.org/linux-pci/20240307-pci-bdf-sid-fix-v1-1-9423a7e2d63c@linaro.org
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>
Cc: stable@vger.kernel.org # 5.11
Signed-off-by: Myron Stowe <mstowe@redhat.com>
JIRA: https://issues.redhat.com/browse/RHEL-33544
Upstream Status: d1997c98781459f7b6d0bf1858f538f48454a97b
commit d1997c98781459f7b6d0bf1858f538f48454a97b
Author: Johan Hovold <johan+linaro@kernel.org>
Date: Wed Mar 6 10:56:49 2024 +0100
PCI: qcom: Disable ASPM L0s for sc8280xp, sa8540p and sa8295p
Commit 9f4f3dfad8cf ("PCI: qcom: Enable ASPM for platforms supporting
1.9.0 ops") started enabling ASPM unconditionally when the hardware
claims to support it. This triggers Correctable Errors for some PCIe
devices on machines like the Lenovo ThinkPad X13s when L0s is enabled,
which could indicate an incomplete driver ASPM implementation or that
the hardware does in fact not support L0s.
This has now been confirmed by Qualcomm to be the case for sc8280xp and
its derivate platforms (e.g. sa8540p and sa8295p). Specifically, the PHY
configuration used on these platforms is not correctly tuned for L0s and
there is currently no updated configuration available.
Add a new flag to the driver configuration data and use it to disable
ASPM L0s on sc8280xp, sa8540p and sa8295p for now.
Note that only the 1.9.0 ops enable ASPM currently.
Link: https://lore.kernel.org/r/20240306095651.4551-4-johan+linaro@kernel.org
Fixes: 9f4f3dfad8cf ("PCI: qcom: Enable ASPM for platforms supporting 1.9.0 ops")
Signed-off-by: Johan Hovold <johan+linaro@kernel.org>
Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Cc: stable@vger.kernel.org # 6.7
Signed-off-by: Myron Stowe <mstowe@redhat.com>
JIRA: https://issues.redhat.com/browse/RHEL-28627
Upstream Status: aea370b2aec9d36d6fdb8c9695c8022429b84492
Conflict(s):
Not a conflict per say, just noting that the hunk related to
drivers/pci/controller/dwc/pcie-intel-gw.c was modified during its
corresponding merge commit so the same change is being made here
(see: commit 787c72b1d45b "Merge branch 'pci/controller/dwc'").
commit aea370b2aec9d36d6fdb8c9695c8022429b84492
Author: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Date: Wed Dec 20 14:38:24 2023 +0900
PCI: dwc: Drop host prefix from struct dw_pcie_host_ops members
Since the name of the dw_pcie_host_ops struct makes it obvious that it's
for the PCIe Host, drop the host prefix from the struct members.
[kwilczynski: commit log]
Suggested-by: Serge Semin <fancer.lancer@gmail.com>
Link: https://lore.kernel.org/linux-pci/20231220053829.1921187-2-yoshihiro.shimoda.uh@renesas.com
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: Serge Semin <fancer.lancer@gmail.com>
Reviewed-by: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
Acked-by: Heiko Stuebner <heiko@sntech.de>
Acked-by: Jesper Nilsson <jesper.nilsson@axis.com>
Acked-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
Acked-by: Lei Chuanhua <lchuanhua@maxlinear.com>
Acked-by: Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp>
Signed-off-by: Myron Stowe <mstowe@redhat.com>
JIRA: https://issues.redhat.com/browse/RHEL-26162
Upstream Status: 1e560864159d002b453da42bd2c13a1805515a20
commit 1e560864159d002b453da42bd2c13a1805515a20
Author: Johan Hovold <johan+linaro@kernel.org>
Date: Tue Jan 30 11:02:43 2024 +0100
PCI/ASPM: Fix deadlock when enabling ASPM
A last minute revert in 6.7-final introduced a potential deadlock when
enabling ASPM during probe of Qualcomm PCIe controllers as reported by
lockdep:
============================================
WARNING: possible recursive locking detected
6.7.0 #40 Not tainted
--------------------------------------------
kworker/u16:5/90 is trying to acquire lock:
ffffacfa78ced000 (pci_bus_sem){++++}-{3:3}, at: pcie_aspm_pm_state_change+0x58/0xdc
but task is already holding lock:
ffffacfa78ced000 (pci_bus_sem){++++}-{3:3}, at: pci_walk_bus+0x34/0xbc
other info that might help us debug this:
Possible unsafe locking scenario:
CPU0
----
lock(pci_bus_sem);
lock(pci_bus_sem);
*** DEADLOCK ***
Call trace:
print_deadlock_bug+0x25c/0x348
__lock_acquire+0x10a4/0x2064
lock_acquire+0x1e8/0x318
down_read+0x60/0x184
pcie_aspm_pm_state_change+0x58/0xdc
pci_set_full_power_state+0xa8/0x114
pci_set_power_state+0xc4/0x120
qcom_pcie_enable_aspm+0x1c/0x3c [pcie_qcom]
pci_walk_bus+0x64/0xbc
qcom_pcie_host_post_init_2_7_0+0x28/0x34 [pcie_qcom]
The deadlock can easily be reproduced on machines like the Lenovo ThinkPad
X13s by adding a delay to increase the race window during asynchronous
probe where another thread can take a write lock.
Add a new pci_set_power_state_locked() and associated helper functions that
can be called with the PCI bus semaphore held to avoid taking the read lock
twice.
Link: https://lore.kernel.org/r/ZZu0qx2cmn7IwTyQ@hovoldconsulting.com
Link: https://lore.kernel.org/r/20240130100243.11011-1-johan+linaro@kernel.org
Fixes: f93e71aea6c6 ("Revert "PCI/ASPM: Remove pcie_aspm_pm_state_change()"")
Signed-off-by: Johan Hovold <johan+linaro@kernel.org>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Cc: <stable@vger.kernel.org> # 6.7
Signed-off-by: Myron Stowe <mstowe@redhat.com>
JIRA: https://issues.redhat.com/browse/RHEL-26162
Upstream Status: 780f52e3213e5f05bb41adebe1f2214f2f86f4a3
commit 780f52e3213e5f05bb41adebe1f2214f2f86f4a3
Author: Johan Hovold <johan+linaro@kernel.org>
Date: Tue Nov 28 09:15:10 2023 +0100
PCI: qcom: Clean up ASPM comment
Break up the newly added ASPM comment so that it fits within the soft 80
character limit and becomes more readable.
Link: https://lore.kernel.org/r/20231128081512.19387-5-johan+linaro@kernel.org
Signed-off-by: Johan Hovold <johan+linaro@kernel.org>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: Myron Stowe <mstowe@redhat.com>
JIRA: https://issues.redhat.com/browse/RHEL-26162
Upstream Status: f352ce99926048e12aa4281c32471031351aec98
commit f352ce99926048e12aa4281c32471031351aec98
Author: Johan Hovold <johan+linaro@kernel.org>
Date: Tue Nov 28 09:15:09 2023 +0100
PCI: qcom: Fix potential deadlock when enabling ASPM
The qcom_pcie_enable_aspm() helper is called from pci_walk_bus() during
host init to enable ASPM.
Since pci_walk_bus() already holds a pci_bus_sem read lock, use
pci_enable_link_state_locked() to enable link states in order to avoid a
potential deadlock (e.g. in case someone takes a write lock before
reacquiring the read lock).
This issue was reported by lockdep:
============================================
WARNING: possible recursive locking detected
6.7.0-rc1 #4 Not tainted
--------------------------------------------
kworker/u16:6/147 is trying to acquire lock:
ffffbf3ff9d2cfa0 (pci_bus_sem){++++}-{3:3}, at: pci_enable_link_state+0x74/0x1e8
but task is already holding lock:
ffffbf3ff9d2cfa0 (pci_bus_sem){++++}-{3:3}, at: pci_walk_bus+0x34/0xbc
other info that might help us debug this:
Possible unsafe locking scenario:
CPU0
----
lock(pci_bus_sem);
lock(pci_bus_sem);
*** DEADLOCK ***
Fixes: 9f4f3dfad8cf ("PCI: qcom: Enable ASPM for platforms supporting 1.9.0 ops")
Link: https://lore.kernel.org/r/20231128081512.19387-4-johan+linaro@kernel.org
Signed-off-by: Johan Hovold <johan+linaro@kernel.org>
[bhelgaas: add "potential" in subject since the deadlock has only been
reported by lockdep, include helper name in commit log]
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Myron Stowe <mstowe@redhat.com>
JIRA: https://issues.redhat.com/browse/RHEL-26162
Upstream Status: 8da2e9af0bb5217361f4ddde0d9b820b45c185e8
commit 8da2e9af0bb5217361f4ddde0d9b820b45c185e8
Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Date: Wed Oct 4 22:14:28 2023 +0530
PCI: qcom: Use PCIE_SPEED2MBS_ENC() macro for encoding link speed
Instead of hardcoding the link speed in MBps, use existing
PCIE_SPEED2MBS_ENC() macro that does the encoding of the link speed for
us. Also, let's Wrap it with QCOM_PCIE_LINK_SPEED_TO_BW() macro to do
the conversion to ICC speed.
This eliminates the need for a switch case in qcom_pcie_icc_update() and
also works for future Gen speeds without any code modifications.
Suggested-by: Bjorn Helgaas <bhelgaas@google.com>
Link: https://lore.kernel.org/linux-pci/20231004164430.39662-1-manivannan.sadhasivam@linaro.org
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Myron Stowe <mstowe@redhat.com>
JIRA: https://issues.redhat.com/browse/RHEL-26162
Upstream Status: 9f4f3dfad8cf08208fbb78b1b9cbf957c12618b9
commit 9f4f3dfad8cf08208fbb78b1b9cbf957c12618b9
Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Date: Tue Oct 10 21:29:14 2023 +0530
PCI: qcom: Enable ASPM for platforms supporting 1.9.0 ops
ASPM is supported by Qcom host controllers/bridges on most of the recent
platforms and so the devices tested so far. But for enabling ASPM by
default (without using Kconfig, kernel command-line or sysfs), BIOS has
to enable ASPM on both host bridge and downstream devices during boot.
Unfortunately, none of the BIOS available on Qcom platforms enables
ASPM. Due to this, the platforms making use of Qcom SoCs draw high power
during runtime.
To fix this power draw issue, users have to enable ASPM using Kconfig,
kernel command-line, sysfs or the BIOS has to start enabling ASPM.
The latter may happen in the future, but that won't address the issue on
current platforms. Also, asking users to enable a feature to get the power
management right would provide an unpleasant out-of-the-box experience.
So the apt solution is to enable ASPM in the controller driver itself. And
this is being accomplished by calling pci_enable_link_state() in the newly
introduced host_post_init() callback for all the devices connected to the
bus. This function enables all supported link low power states for both
host bridge and the downstream devices.
Due to limited testing, ASPM is only enabled for platforms making use of
ops_1_9_0 callbacks.
[kwilczynski: commit log]
Link: https://lore.kernel.org/linux-pci/20231010155914.9516-3-manivannan.sadhasivam@linaro.org
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>
Signed-off-by: Myron Stowe <mstowe@redhat.com>
JIRA: https://issues.redhat.com/browse/RHEL-15044
Upstream Status: 6a878a54d0053ef21f3b829dc267487c2302b012
commit 6a878a54d0053ef21f3b829dc267487c2302b012
Author: Sricharan Ramabadhran <quic_srichara@quicinc.com>
Date: Tue Sep 19 15:59:48 2023 +0530
PCI: qcom: Fix IPQ8074 enumeration
PARF_SLV_ADDR_SPACE_SIZE_2_3_3 is used by qcom_pcie_post_init_2_3_3().
This PCIe slave address space size register offset is 0x358 but was
incorrectly changed to 0x16c by 39171b33f652 ("PCI: qcom: Remove PCIE20_
prefix from register definitions").
This prevented access to slave address space registers like iATU, etc.,
so the IPQ8074 PCIe controller was not enumerated.
Revert back to the correct 0x358 offset and remove the unused
PARF_SLV_ADDR_SPACE_SIZE_2_3_3.
Fixes: 39171b33f652 ("PCI: qcom: Remove PCIE20_ prefix from register definitions")
Link: https://lore.kernel.org/r/20230919102948.1844909-1-quic_srichara@quicinc.com
Tested-by: Robert Marko <robimarko@gmail.com>
Signed-off-by: Sricharan Ramabadhran <quic_srichara@quicinc.com>
[bhelgaas: commit log]
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Manivannan Sadhasivam <mani@kernel.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Cc: stable@vger.kernel.org # v6.4+
Signed-off-by: Myron Stowe <mstowe@redhat.com>
JIRA: https://issues.redhat.com/browse/RHEL-15044
Upstream Status: c925cfaf0992f151c02f239e035ca9316224f224
commit c925cfaf0992f151c02f239e035ca9316224f224
Author: Rob Herring <robh@kernel.org>
Date: Fri Jul 14 11:48:25 2023 -0600
PCI: Explicitly include correct DT includes
The DT of_device.h and of_platform.h date back to the separate
of_platform_bus_type before it as merged into the regular platform bus. As
part of that merge prepping Arm DT support 13 years ago, they "temporarily"
include each other. They also include platform_device.h and of.h. As a
result, there's a pretty much random mix of those include files used
throughout the tree. In order to detangle these headers and replace the
implicit includes with struct declarations, users need to explicitly
include the correct includes.
Link: https://lore.kernel.org/r/20230714174827.4061572-1-robh@kernel.org
Signed-off-by: Rob Herring <robh@kernel.org>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: Myron Stowe <mstowe@redhat.com>
JIRA: https://issues.redhat.com/browse/RHEL-2570
Upstream Status: 1fdecc5bc8e81b0afba17876ff99b4131d0e03aa
commit 1fdecc5bc8e81b0afba17876ff99b4131d0e03aa
Author: Manivannan Sadhasivam <mani@kernel.org>
Date: Mon Jun 19 20:34:08 2023 +0530
PCI: qcom: Do not advertise hotplug capability for IP v2.1.0
SoCs making use of Qcom PCIe controller IP v2.1.0 do not support hotplug
functionality. But the hotplug capability bit is set by default in the
hardware. This causes the kernel PCI core to register hotplug service for
the controller and send hotplug commands to it. But those commands will
timeout generating messages as below during boot and suspend/resume.
[ 5.782159] pcieport 0001:00:00.0: pciehp: Timeout on hotplug command 0x03c0 (issued 2020 msec ago)
[ 5.810161] pcieport 0001:00:00.0: pciehp: Timeout on hotplug command 0x03c0 (issued 2048 msec ago)
[ 7.838162] pcieport 0001:00:00.0: pciehp: Timeout on hotplug command 0x07c0 (issued 2020 msec ago)
[ 7.870159] pcieport 0001:00:00.0: pciehp: Timeout on hotplug command 0x07c0 (issued 2052 msec ago)
This not only spams the console output but also induces a delay of a
couple of seconds. To fix this issue, let's clear the HPC bit in
PCI_EXP_SLTCAP register as a part of the post init sequence to not
advertise the hotplug capability for the controller.
Link: https://lore.kernel.org/r/20230619150408.8468-10-manivannan.sadhasivam@linaro.org
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org>
Signed-off-by: Myron Stowe <mstowe@redhat.com>
JIRA: https://issues.redhat.com/browse/RHEL-2570
Upstream Status: fa2dc252868403d3de9f3589f725a026b51c6f72
commit fa2dc252868403d3de9f3589f725a026b51c6f72
Author: Manivannan Sadhasivam <mani@kernel.org>
Date: Mon Jun 19 20:34:07 2023 +0530
PCI: qcom: Do not advertise hotplug capability for IP v1.0.0
SoCs making use of Qcom PCIe controller IP v1.0.0 do not support hotplug
functionality. But the hotplug capability bit is set by default in the
hardware. This causes the kernel PCI core to register hotplug service for
the controller and send hotplug commands to it. But those commands will
timeout generating messages as below during boot and suspend/resume.
[ 5.782159] pcieport 0001:00:00.0: pciehp: Timeout on hotplug command 0x03c0 (issued 2020 msec ago)
[ 5.810161] pcieport 0001:00:00.0: pciehp: Timeout on hotplug command 0x03c0 (issued 2048 msec ago)
[ 7.838162] pcieport 0001:00:00.0: pciehp: Timeout on hotplug command 0x07c0 (issued 2020 msec ago)
[ 7.870159] pcieport 0001:00:00.0: pciehp: Timeout on hotplug command 0x07c0 (issued 2052 msec ago)
This not only spams the console output but also induces a delay of a
couple of seconds. To fix this issue, let's clear the HPC bit in
PCI_EXP_SLTCAP register as a part of the post init sequence to not
advertise the hotplug capability for the controller.
Link: https://lore.kernel.org/r/20230619150408.8468-9-manivannan.sadhasivam@linaro.org
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org>
Signed-off-by: Myron Stowe <mstowe@redhat.com>
JIRA: https://issues.redhat.com/browse/RHEL-2570
Upstream Status: e35d13a5ff372244c9f9d1ea01532d26698cb046
commit e35d13a5ff372244c9f9d1ea01532d26698cb046
Author: Manivannan Sadhasivam <mani@kernel.org>
Date: Mon Jun 19 20:34:06 2023 +0530
PCI: qcom: Use post init sequence of IP v2.3.2 for v2.4.0
The post init sequence of IP v2.4.0 is same as v2.3.2. So let's reuse the
v2.3.2 sequence which now also disables hotplug capability of the
controller as it is not at all supported on any SoCs making use of this IP.
Link: https://lore.kernel.org/r/20230619150408.8468-8-manivannan.sadhasivam@linaro.org
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Myron Stowe <mstowe@redhat.com>
JIRA: https://issues.redhat.com/browse/RHEL-2570
Upstream Status: 25966e78d3035b6356d9284ad07b3033212c691b
commit 25966e78d3035b6356d9284ad07b3033212c691b
Author: Manivannan Sadhasivam <mani@kernel.org>
Date: Mon Jun 19 20:34:05 2023 +0530
PCI: qcom: Do not advertise hotplug capability for IP v2.3.2
SoCs making use of Qcom PCIe controller IP v2.3.2 do not support hotplug
functionality. But the hotplug capability bit is set by default in the
hardware. This causes the kernel PCI core to register hotplug service for
the controller and send hotplug commands to it. But those commands will
timeout generating messages as below during boot and suspend/resume.
[ 5.782159] pcieport 0001:00:00.0: pciehp: Timeout on hotplug command 0x03c0 (issued 2020 msec ago)
[ 5.810161] pcieport 0001:00:00.0: pciehp: Timeout on hotplug command 0x03c0 (issued 2048 msec ago)
[ 7.838162] pcieport 0001:00:00.0: pciehp: Timeout on hotplug command 0x07c0 (issued 2020 msec ago)
[ 7.870159] pcieport 0001:00:00.0: pciehp: Timeout on hotplug command 0x07c0 (issued 2052 msec ago)
This not only spams the console output but also induces a delay of a
couple of seconds. To fix this issue, let's clear the HPC bit in
PCI_EXP_SLTCAP register as a part of the post init sequence to not
advertise the hotplug capability for the controller.
Link: https://lore.kernel.org/r/20230619150408.8468-7-manivannan.sadhasivam@linaro.org
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org>
Signed-off-by: Myron Stowe <mstowe@redhat.com>
JIRA: https://issues.redhat.com/browse/RHEL-2570
Upstream Status: 11bce06b21a0d5f002156b2bc6573329f285a927
commit 11bce06b21a0d5f002156b2bc6573329f285a927
Author: Manivannan Sadhasivam <mani@kernel.org>
Date: Mon Jun 19 20:34:04 2023 +0530
PCI: qcom: Do not advertise hotplug capability for IPs v2.3.3 and v2.9.0
SoCs making use of Qcom PCIe controller IPs v2.3.3 and v2.9.0 do not
support hotplug functionality. But the hotplug capability bit is set by
default in the hardware. This causes the kernel PCI core to register
hotplug service for the controller and send hotplug commands to it. But
those commands will timeout generating messages as below during boot
and suspend/resume.
[ 5.782159] pcieport 0001:00:00.0: pciehp: Timeout on hotplug command 0x03c0 (issued 2020 msec ago)
[ 5.810161] pcieport 0001:00:00.0: pciehp: Timeout on hotplug command 0x03c0 (issued 2048 msec ago)
[ 7.838162] pcieport 0001:00:00.0: pciehp: Timeout on hotplug command 0x07c0 (issued 2020 msec ago)
[ 7.870159] pcieport 0001:00:00.0: pciehp: Timeout on hotplug command 0x07c0 (issued 2052 msec ago)
This not only spams the console output but also induces a delay of a
couple of seconds. To fix this issue, let's not set the HPC bit in
PCI_EXP_SLTCAP register as a part of the post init sequence to not
advertise the hotplug capability for the controller.
Link: https://lore.kernel.org/r/20230619150408.8468-6-manivannan.sadhasivam@linaro.org
Tested-by: Sricharan Ramabadhran <quic_srichara@quicinc.com>
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Myron Stowe <mstowe@redhat.com>
JIRA: https://issues.redhat.com/browse/RHEL-2570
Upstream Status: a54db86ddc153484e36266aa2da458a3d9ba0d64
commit a54db86ddc153484e36266aa2da458a3d9ba0d64
Author: Manivannan Sadhasivam <mani@kernel.org>
Date: Mon Jun 19 20:34:03 2023 +0530
PCI: qcom: Do not advertise hotplug capability for IPs v2.7.0 and v1.9.0
SoCs making use of Qcom PCIe controller IPs v2.7.0 and v1.9.0 do not
support hotplug functionality. But the hotplug capability bit is set by
default in the hardware. This causes the kernel PCI core to register
hotplug service for the controller and send hotplug commands to it. But
those commands will timeout generating messages as below during boot and
suspend/resume.
[ 5.782159] pcieport 0001:00:00.0: pciehp: Timeout on hotplug command 0x03c0 (issued 2020 msec ago)
[ 5.810161] pcieport 0001:00:00.0: pciehp: Timeout on hotplug command 0x03c0 (issued 2048 msec ago)
[ 7.838162] pcieport 0001:00:00.0: pciehp: Timeout on hotplug command 0x07c0 (issued 2020 msec ago)
[ 7.870159] pcieport 0001:00:00.0: pciehp: Timeout on hotplug command 0x07c0 (issued 2052 msec ago)
This not only spams the console output but also induces a delay of a
couple of seconds. To fix this issue, let's clear the HPC bit in
PCI_EXP_SLTCAP register as a part of the post init sequence to not
advertise the hotplug capability for the controller.
Link: https://lore.kernel.org/r/20230619150408.8468-5-manivannan.sadhasivam@linaro.org
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Myron Stowe <mstowe@redhat.com>
JIRA: https://issues.redhat.com/browse/RHEL-2570
Upstream Status: 200b8f85f2021362adcc8efb575652a2aa44c099
commit 200b8f85f2021362adcc8efb575652a2aa44c099
Author: Manivannan Sadhasivam <mani@kernel.org>
Date: Mon Jun 19 20:34:02 2023 +0530
PCI: qcom: Disable write access to read only registers for IP v2.9.0
In the post init sequence of v2.9.0, write access to read only registers
are not disabled after updating the registers. Fix it by disabling the
access after register update.
While at it, let's also add a newline after existing dw_pcie_dbi_ro_wr_en()
guard function to align with rest of the driver.
Link: https://lore.kernel.org/r/20230619150408.8468-4-manivannan.sadhasivam@linaro.org
Fixes: 0cf7c2efe8ac ("PCI: qcom: Add IPQ60xx support")
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Myron Stowe <mstowe@redhat.com>
JIRA: https://issues.redhat.com/browse/RHEL-2570
Upstream Status: 60f0072d7fb7996b9a524ef0d152e21205473192
commit 60f0072d7fb7996b9a524ef0d152e21205473192
Author: Manivannan Sadhasivam <mani@kernel.org>
Date: Mon Jun 19 20:34:01 2023 +0530
PCI: qcom: Use DWC helpers for modifying the read-only DBI registers
DWC core already exposes dw_pcie_dbi_ro_wr_{en/dis} helper APIs for
enabling and disabling the write access to read only DBI registers. So
let's use them instead of doing it manually.
Also, the existing code doesn't disable the write access when it's done.
This is also fixed now.
Link: https://lore.kernel.org/r/20230619150408.8468-3-manivannan.sadhasivam@linaro.org
Fixes: 5d76117f07 ("PCI: qcom: Add support for IPQ8074 PCIe controller")
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Myron Stowe <mstowe@redhat.com>
JIRA: https://issues.redhat.com/browse/RHEL-2570
Upstream Status: a33d700e8eea76c62120cb3dbf5e01328f18319a
commit a33d700e8eea76c62120cb3dbf5e01328f18319a
Author: Manivannan Sadhasivam <mani@kernel.org>
Date: Mon Jun 19 20:34:00 2023 +0530
PCI: qcom: Disable write access to read only registers for IP v2.3.3
In the post init sequence of v2.9.0, write access to read only registers
are not disabled after updating the registers. Fix it by disabling the
access after register update.
Link: https://lore.kernel.org/r/20230619150408.8468-2-manivannan.sadhasivam@linaro.org
Fixes: 5d76117f07 ("PCI: qcom: Add support for IPQ8074 PCIe controller")
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org>
Cc: <stable@vger.kernel.org>
Signed-off-by: Myron Stowe <mstowe@redhat.com>
Bugzilla: https://bugzilla.redhat.com/show_bug.cgi?id=2228915
Upstream Status: 6276a403c0ff2908a05d1ff4f80f961478baebbd
commit 6276a403c0ff2908a05d1ff4f80f961478baebbd
Author: Abel Vesa <abel.vesa@linaro.org>
Date: Mon Mar 20 16:46:58 2023 +0200
PCI: qcom: Add SM8550 PCIe support
SM8550 requires two additional clocks for proper working.
Add these two clocks as optional clocks (as only required by this
platform) and compatible for this platform.
While at it, let's also rename the reset variable to "rst" from
"pci_reset" to match the existing naming preference.
Link: https://lore.kernel.org/r/20230320144658.1794991-2-abel.vesa@linaro.org
Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
[lpieralisi@kernel.org: commit log rewording]
Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Reviewed-by: Manivannan Sadhasivam <mani@kernel.org>
Reviewed-by: Johan Hovold <johan+linaro@kernel.org>
Signed-off-by: Myron Stowe <mstowe@redhat.com>
Bugzilla: https://bugzilla.redhat.com/show_bug.cgi?id=2228915
Upstream Status: 7394d0a85d6f847946dfe3f114f4d3f6a3988a36
commit 7394d0a85d6f847946dfe3f114f4d3f6a3988a36
Author: Manivannan Sadhasivam <mani@kernel.org>
Date: Wed Mar 8 13:54:24 2023 +0530
PCI: qcom: Add support for SDX55 SoC
Add support for SDX55 SoC reusing the 1.9.0 config. The PCIe controller is
of version 1.10.0 but it is compatible with the 1.9.0 config. This SoC also
requires "sleep" clock which is added as an optional clock in the driver,
since it is not required on other SoCs.
Link: https://lore.kernel.org/r/20230308082424.140224-14-manivannan.sadhasivam@linaro.org
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org>
Signed-off-by: Myron Stowe <mstowe@redhat.com>
Bugzilla: https://bugzilla.redhat.com/show_bug.cgi?id=2228915
Upstream Status: c0e1eb441b1de42500cbc081b8d754caae6b27b1
commit c0e1eb441b1de42500cbc081b8d754caae6b27b1
Author: Manivannan Sadhasivam <mani@kernel.org>
Date: Mon Mar 20 12:16:44 2023 +0530
PCI: qcom: Enable async probe by default
Qcom PCIe RC driver waits for the PHY link to be up during the probe;
this consumes several milliseconds during boot.
Enable async probe by default so that other drivers can load in parallel
while this driver waits for the link to be up.
Suggested-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20230320064644.5217-1-manivannan.sadhasivam@linaro.org
Tested-by: Johan Hovold <johan+linaro@kernel.org>
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org>
Reviewed-by: Johan Hovold <johan+linaro@kernel.org>
Signed-off-by: Myron Stowe <mstowe@redhat.com>
Bugzilla: https://bugzilla.redhat.com/show_bug.cgi?id=2228915
Upstream Status: ad9b9b6e36c920234af6e86982dd48be560385b1
commit ad9b9b6e36c920234af6e86982dd48be560385b1
Author: Manivannan Sadhasivam <mani@kernel.org>
Date: Mon Apr 3 21:19:22 2023 +0530
PCI: qcom: Add support for system suspend and resume
During the system suspend, vote for minimal interconnect bandwidth (1KiB)
to keep the interconnect path active for config access and also turn OFF
the resources like clock and PHY if there are no active devices connected
to the controller. For the controllers with active devices, the resources
are kept ON as removing the resources will trigger access violation during
the late end of suspend cycle as kernel tries to access the config space of
PCIe devices to mask the MSIs.
Also, it is not desirable to put the link into L2/L3 state as that
implies VDD supply will be removed and the devices may go into powerdown
state. This will affect the lifetime of storage devices like NVMe.
And finally, during resume, turn ON the resources if the controller was
truly suspended (resources OFF) and update the interconnect bandwidth
based on PCIe Gen speed.
Suggested-by: Krishna chaitanya chundru <quic_krichai@quicinc.com>
Link: https://lore.kernel.org/r/20230403154922.20704-2-manivannan.sadhasivam@linaro.org
Tested-by: Johan Hovold <johan+linaro@kernel.org>
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org>
Reviewed-by: Johan Hovold <johan+linaro@kernel.org>
Acked-by: Dhruva Gole <d-gole@ti.com>
Signed-off-by: Myron Stowe <mstowe@redhat.com>
Bugzilla: https://bugzilla.redhat.com/show_bug.cgi?id=2228915
Upstream Status: 05f4646409625b45e315ed0c5ab1078445f5ef43
commit 05f4646409625b45e315ed0c5ab1078445f5ef43
Author: Manivannan Sadhasivam <mani@kernel.org>
Date: Thu Mar 16 13:41:17 2023 +0530
PCI: qcom: Expose link transition counts via debugfs
Qualcomm PCIe controllers have debug registers in the MHI region that
count PCIe link transitions. Expose them over debugfs to userspace to
help debug the low power issues.
Note that even though the registers are prefixed as PARF_, they don't
live under the "parf" register region. The register naming is following
the Qualcomm's internal documentation as like other registers.
While at it, let's arrange the local variables in probe function to follow
reverse XMAS tree order.
Link: https://lore.kernel.org/r/20230316081117.14288-20-manivannan.sadhasivam@linaro.org
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org>
Signed-off-by: Myron Stowe <mstowe@redhat.com>
Bugzilla: https://bugzilla.redhat.com/show_bug.cgi?id=2228915
Upstream Status: 1f70939871b260b52e9d1941f1cad740b7295c2c
commit 1f70939871b260b52e9d1941f1cad740b7295c2c
Author: Manivannan Sadhasivam <mani@kernel.org>
Date: Thu Mar 16 13:41:12 2023 +0530
PCI: qcom: Rename qcom_pcie_config_sid_sm8250() to reflect IP version
qcom_pcie_config_sid_sm8250() function no longer applies only to SM8250.
So let's rename it to reflect the actual IP version and also move its
definition to keep it sorted as per IP revisions.
Link: https://lore.kernel.org/r/20230316081117.14288-15-manivannan.sadhasivam@linaro.org
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org>
Signed-off-by: Myron Stowe <mstowe@redhat.com>
Bugzilla: https://bugzilla.redhat.com/show_bug.cgi?id=2228915
Upstream Status: 656a08820e7b10d5b6dfecdb8035e2c9411b5474
commit 656a08820e7b10d5b6dfecdb8035e2c9411b5474
Author: Manivannan Sadhasivam <mani@kernel.org>
Date: Thu Mar 16 13:41:11 2023 +0530
PCI: qcom: Use macros for defining total no. of clocks & supplies
To keep uniformity, let's use macros to define the total number of clocks
and supplies in qcom_pcie_resources_{2_7_0/2_9_0} structs.
Link: https://lore.kernel.org/r/20230316081117.14288-14-manivannan.sadhasivam@linaro.org
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org>
Signed-off-by: Myron Stowe <mstowe@redhat.com>
Bugzilla: https://bugzilla.redhat.com/show_bug.cgi?id=2228915
Upstream Status: fb0eacb2972e2f330b188e5b22955d020599bf38
commit fb0eacb2972e2f330b188e5b22955d020599bf38
Author: Manivannan Sadhasivam <mani@kernel.org>
Date: Thu Mar 16 13:41:10 2023 +0530
PCI: qcom: Use bulk reset APIs for handling resets for IP rev 2.4.0
All the resets are asserted and deasserted at the same time. So the bulk
reset APIs can be used to handle them together. This simplifies the code
a lot.
It should be noted that there were delays in-between the reset asserts and
deasserts. But going by the config used by other revisions, those delays
are not really necessary. So a single delay after all asserts and one after
deasserts is used.
The total number of resets supported is 12 but only ipq4019 is using all of
them.
Link: https://lore.kernel.org/r/20230316081117.14288-13-manivannan.sadhasivam@linaro.org
Tested-by: Sricharan Ramabadhran <quic_srichara@quicinc.com>
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org>
Signed-off-by: Myron Stowe <mstowe@redhat.com>
Bugzilla: https://bugzilla.redhat.com/show_bug.cgi?id=2228915
Upstream Status: 157fecca3558dd21b33038d6a935e8533c16043d
commit 157fecca3558dd21b33038d6a935e8533c16043d
Author: Manivannan Sadhasivam <mani@kernel.org>
Date: Thu Mar 16 13:41:09 2023 +0530
PCI: qcom: Use bulk reset APIs for handling resets for IP rev 2.3.3
All the resets are asserted and deasserted at the same time. So the bulk
reset APIs can be used to handle them together. This simplifies the code
a lot.
Link: https://lore.kernel.org/r/20230316081117.14288-12-manivannan.sadhasivam@linaro.org
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org>
Signed-off-by: Myron Stowe <mstowe@redhat.com>
Bugzilla: https://bugzilla.redhat.com/show_bug.cgi?id=2228915
Upstream Status: b699ed9b03de4fbf6eed51dfdec3c437fe3d653c
commit b699ed9b03de4fbf6eed51dfdec3c437fe3d653c
Author: Manivannan Sadhasivam <mani@kernel.org>
Date: Thu Mar 16 13:41:08 2023 +0530
PCI: qcom: Use bulk clock APIs for handling clocks for IP rev 2.3.3
All the clocks are enabled and disabled at the same time. So the bulk clock
APIs can be used to handle them together. This simplifies the code a lot.
Link: https://lore.kernel.org/r/20230316081117.14288-11-manivannan.sadhasivam@linaro.org
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org>
Signed-off-by: Myron Stowe <mstowe@redhat.com>
Bugzilla: https://bugzilla.redhat.com/show_bug.cgi?id=2228915
Upstream Status: 5329bcc4a1e7dc41fcdffaa55c73b17b527b804f
commit 5329bcc4a1e7dc41fcdffaa55c73b17b527b804f
Author: Manivannan Sadhasivam <mani@kernel.org>
Date: Thu Mar 16 13:41:07 2023 +0530
PCI: qcom: Use bulk clock APIs for handling clocks for IP rev 2.3.2
All the clocks are enabled and disabled at the same time. So the bulk clock
APIs can be used to handle them together. This simplifies the code a lot.
Link: https://lore.kernel.org/r/20230316081117.14288-10-manivannan.sadhasivam@linaro.org
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org>
Signed-off-by: Myron Stowe <mstowe@redhat.com>
Bugzilla: https://bugzilla.redhat.com/show_bug.cgi?id=2228915
Upstream Status: 5d4ffe5ec5e91c78de51f095673f1ad74438f60a
commit 5d4ffe5ec5e91c78de51f095673f1ad74438f60a
Author: Manivannan Sadhasivam <mani@kernel.org>
Date: Thu Mar 16 13:41:06 2023 +0530
PCI: qcom: Use bulk clock APIs for handling clocks for IP rev 1.0.0
All the clocks are enabled and disabled at the same time. So the bulk clock
APIs can be used to handle them together. This simplifies the code a lot.
Link: https://lore.kernel.org/r/20230316081117.14288-9-manivannan.sadhasivam@linaro.org
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org>
Signed-off-by: Myron Stowe <mstowe@redhat.com>
Bugzilla: https://bugzilla.redhat.com/show_bug.cgi?id=2228915
Upstream Status: 383215dd2fd716f151608886ff19bbe1e1a9cf91
commit 383215dd2fd716f151608886ff19bbe1e1a9cf91
Author: Manivannan Sadhasivam <mani@kernel.org>
Date: Thu Mar 16 13:41:05 2023 +0530
PCI: qcom: Use bulk reset APIs for handling resets for IP rev 2.1.0
All the resets are asserted and deasserted at the same time. So the bulk
reset APIs can be used to handle them together. This simplifies the code
a lot.
While at it, let's also move the qcom_pcie_resources_2_1_0 struct below
qcom_pcie_resources_1_0_0 to keep it sorted.
Link: https://lore.kernel.org/r/20230316081117.14288-8-manivannan.sadhasivam@linaro.org
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org>
Signed-off-by: Myron Stowe <mstowe@redhat.com>
Bugzilla: https://bugzilla.redhat.com/show_bug.cgi?id=2228915
Upstream Status: 17804668ca545232e94dee5fe87ab3eaf6391cbe
commit 17804668ca545232e94dee5fe87ab3eaf6391cbe
Author: Manivannan Sadhasivam <mani@kernel.org>
Date: Thu Mar 16 13:41:03 2023 +0530
PCI: qcom: Add missing macros for register fields
Some of the registers are changed using hardcoded bitfields without macros.
This provides no information on what the register setting is about. So add
the macros to those fields for making the code more understandable.
Link: https://lore.kernel.org/r/20230316081117.14288-6-manivannan.sadhasivam@linaro.org
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org>
Signed-off-by: Myron Stowe <mstowe@redhat.com>
Bugzilla: https://bugzilla.redhat.com/show_bug.cgi?id=2228915
Upstream Status: 57eddec8dc30ed968f31664f76548ee8d7c47c5e
commit 57eddec8dc30ed968f31664f76548ee8d7c47c5e
Author: Manivannan Sadhasivam <mani@kernel.org>
Date: Thu Mar 16 13:41:02 2023 +0530
PCI: qcom: Use bitfield definitions for register fields
To maintain uniformity throughout the driver and also to make the code
easier to read, let's make use of bitfield definitions for register fields.
Link: https://lore.kernel.org/r/20230316081117.14288-5-manivannan.sadhasivam@linaro.org
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org>
Signed-off-by: Myron Stowe <mstowe@redhat.com>
Bugzilla: https://bugzilla.redhat.com/show_bug.cgi?id=2228915
Upstream Status: 769e49d87b15c302c9aadd87c7d114cfe7052320
commit 769e49d87b15c302c9aadd87c7d114cfe7052320
Author: Manivannan Sadhasivam <mani@kernel.org>
Date: Thu Mar 16 13:41:01 2023 +0530
PCI: qcom: Sort and group registers and bitfield definitions
Sorting the registers and their bit definitions will make it easier to add
more definitions in the future and it also helps in maintenance.
While at it, let's also group the registers and bit definitions separately
as done in the pcie-qcom-ep driver.
Link: https://lore.kernel.org/r/20230316081117.14288-4-manivannan.sadhasivam@linaro.org
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org>
Signed-off-by: Myron Stowe <mstowe@redhat.com>
Bugzilla: https://bugzilla.redhat.com/show_bug.cgi?id=2228915
Upstream Status: 39171b33f6523f28c1c1256427e5f50c74b69639
commit 39171b33f6523f28c1c1256427e5f50c74b69639
Author: Manivannan Sadhasivam <mani@kernel.org>
Date: Thu Mar 16 13:41:00 2023 +0530
PCI: qcom: Remove PCIE20_ prefix from register definitions
The PCIE part is redundant and 20 doesn't represent anything across the
SoCs supported now. So let's get rid of the prefix.
This involves adding the IP version suffix to one definition of
PARF_SLV_ADDR_SPACE_SIZE that defines offset specific to that version.
The other definition is generic for the rest of the versions.
Also, the register PCIE20_LNK_CONTROL2_LINK_STATUS2 is not used anywhere,
hence removed.
Link: https://lore.kernel.org/r/20230316081117.14288-3-manivannan.sadhasivam@linaro.org
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org>
Signed-off-by: Myron Stowe <mstowe@redhat.com>
Bugzilla: https://bugzilla.redhat.com/show_bug.cgi?id=2228915
Upstream Status: 2542e16c392508800f1d9037feee881a9c444951
commit 2542e16c392508800f1d9037feee881a9c444951
Author: Manivannan Sadhasivam <mani@kernel.org>
Date: Thu Mar 16 13:40:59 2023 +0530
PCI: qcom: Fix the incorrect register usage in v2.7.0 config
Qcom PCIe IP version v2.7.0 and its derivatives don't contain the
PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT register. Instead, they have the new
PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT_V2 register. So fix the incorrect
register usage which is modifying a different register.
Also in this IP version, this register change doesn't depend on MSI
being enabled. So remove that check also.
Link: https://lore.kernel.org/r/20230316081117.14288-2-manivannan.sadhasivam@linaro.org
Fixes: ed8cc3b1fc ("PCI: qcom: Add support for SDM845 PCIe controller")
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org>
Cc: <stable@vger.kernel.org> # 5.6+
Signed-off-by: Myron Stowe <mstowe@redhat.com>
Bugzilla: https://bugzilla.redhat.com/show_bug.cgi?id=2179137
Upstream Status: f356132229b18ceef5d5ef9103bbaa9bdeb84c8d
commit f356132229b18ceef5d5ef9103bbaa9bdeb84c8d
Author: Robert Marko <robimarko@gmail.com>
Date: Fri Jan 13 17:44:47 2023 +0100
PCI: qcom: Add IPQ8074 Gen3 port support
IPQ8074 has one Gen2 and one Gen3 port, with Gen2 port already supported.
Add compatible for Gen3 port which uses the same controller as IPQ6018.
Link: https://lore.kernel.org/r/20230113164449.906002-7-robimarko@gmail.com
Signed-off-by: Robert Marko <robimarko@gmail.com>
Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: Myron Stowe <mstowe@redhat.com>
Bugzilla: https://bugzilla.redhat.com/show_bug.cgi?id=2179137
Upstream Status: 997e010de9134474dbfde52be03efd7d1bce902d
commit 997e010de9134474dbfde52be03efd7d1bce902d
Author: Johan Hovold <johan+linaro@kernel.org>
Date: Mon Oct 17 13:47:04 2022 +0200
PCI: qcom: Fix host-init error handling
Implement the new host_deinit() callback so that the PHY is powered off
and regulators and clocks are disabled also on late host-init errors.
Link: https://lore.kernel.org/r/20221017114705.8277-2-johan+linaro@kernel.org
Fixes: 82a823833f ("PCI: qcom: Add Qualcomm PCIe controller driver")
Signed-off-by: Johan Hovold <johan+linaro@kernel.org>
Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Manivannan Sadhasivam <mani@kernel.org>
Signed-off-by: Myron Stowe <mstowe@redhat.com>
Bugzilla: https://bugzilla.redhat.com/2164511
commit f90747d1b641aad244cca7d6aa20aa25f33ae8e4
Author: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Date: Tue Sep 27 12:22:05 2022 +0300
PCI: qcom: Setup PHY to work in RC mode
Call phy_set_mode_ext() to notify the PHY driver that the PHY is being
used in the RC mode.
Reviewed-by: Jingoo Han <jingoohan1@gmail.com>
Reviewed-by: Johan Hovold <johan+linaro@kernel.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Acked-by: Lorenzo Pieralisi <lpieralisi@kernel.org>
Link: https://lore.kernel.org/r/20220927092207.161501-5-dmitry.baryshkov@linaro.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Signed-off-by: Shawn Doherty <sdoherty@redhat.com>
Bugzilla: https://bugzilla.redhat.com/2164511
commit c4860af88d0cb1bb006df12615c5515ae509f73b
Author: Johan Hovold <johan+linaro@kernel.org>
Date: Wed Nov 2 10:07:05 2022 +0100
PCI: qcom: Add basic interconnect support
On Qualcomm platforms like SC8280XP and SA8540P, interconnect bandwidth
must be requested before enabling interconnect clocks.
Add basic support for managing an optional "pcie-mem" interconnect path
by setting a low constraint before enabling clocks and updating it after
the link is up.
Note that it is not possible for a controller driver to set anything but
a maximum peak bandwidth as expected average bandwidth will vary with
use case and actual use (and power policy?). This very much remains an
unresolved problem with the interconnect framework.
Also note that no constraint is set for the SC8280XP/SA8540P "cpu-pcie"
path for now as it is not clear what an appropriate constraint would be
(and the system does not crash when left unspecified).
Link: https://lore.kernel.org/r/20221102090705.23634-3-johan+linaro@kernel.org
Fixes: 70574511f3fc ("PCI: qcom: Add support for SC8280XP")
Signed-off-by: Johan Hovold <johan+linaro@kernel.org>
Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org>
Reviewed-by: Brian Masney <bmasney@redhat.com>
Reviewed-by: Manivannan Sadhasivam <mani@kernel.org>
Acked-by: Georgi Djakov <djakov@kernel.org>
Signed-off-by: Shawn Doherty <sdoherty@redhat.com>
Bugzilla: https://bugzilla.redhat.com/show_bug.cgi?id=2135902
Upstream Status: b623023225abed7a7d76cf1cc9f7187c1a3e7cff
commit b623023225abed7a7d76cf1cc9f7187c1a3e7cff
Author: Johan Hovold <johan+linaro@kernel.org>
Date: Wed Sep 28 17:54:20 2022 +0200
PCI: qcom: Drop unused post_deinit callback
Drop the unused and confusingly named post_deinit callback that was
added for the now removed pipe clock handling.
If ever needed we can add back a callback named pre_deinit (or perhaps
rather pre_phy_power_off) instead.
Link: https://lore.kernel.org/r/20220928155421.21660-2-johan+linaro@kernel.org
Signed-off-by: Johan Hovold <johan+linaro@kernel.org>
Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org>
Signed-off-by: Myron Stowe <mstowe@redhat.com>
Myron Stowe
Scott Weaver
Alessandro Carminati
Shawn Doherty