JIRA: https://issues.redhat.com/browse/RHEL-47438
Upstream Status: d66041063192497a4a97d21dbf86b79a03a7f4fb
commit d66041063192497a4a97d21dbf86b79a03a7f4fb
Author: Jian-Hong Pan <jhp@endlessos.org>
Date: Tue Oct 1 16:34:38 2024 +0800
PCI: vmd: Set devices to D0 before enabling PM L1 Substates
The remapped PCIe Root Port and the child device have PM L1 Substates
capability, but they are disabled originally.
Here is a failed example on ASUS B1400CEAE:
Capabilities: [900 v1] L1 PM Substates
L1SubCap: PCI-PM_L1.2+ PCI-PM_L1.1- ASPM_L1.2+ ASPM_L1.1- L1_PM_Substates+
PortCommonModeRestoreTime=32us PortTPowerOnTime=10us
L1SubCtl1: PCI-PM_L1.2- PCI-PM_L1.1- ASPM_L1.2+ ASPM_L1.1-
T_CommonMode=0us LTR1.2_Threshold=101376ns
L1SubCtl2: T_PwrOn=50us
Enable PCI-PM L1 PM Substates for devices below VMD while they are in D0
(see PCIe r6.0, sec 5.5.4).
Link: https://lore.kernel.org/r/20241001083438.10070-4-jhp@endlessos.org
Link: https://bugzilla.kernel.org/show_bug.cgi?id=218394
Signed-off-by: Jian-Hong Pan <jhp@endlessos.org>
Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Kuppuswamy Sathyanarayanan <sathyanarayanan.kuppuswamy@linux.intel.com>
Signed-off-by: Myron Stowe <mstowe@redhat.com>
JIRA: https://issues.redhat.com/browse/RHEL-47438
Upstream Status: b727484cace4be22be9321cc0bc9487648ba447b
commit b727484cace4be22be9321cc0bc9487648ba447b
Author: Nirmal Patel <nirmal.patel@linux.ntel.com>
Date: Fri Oct 11 10:56:57 2024 -0700
PCI: vmd: Add DID 8086:B06F and 8086:B60B for Intel client SKUs
Add support for this VMD device which supports the bus restriction mode.
The feature that turns off vector 0 for MSI-X remapping is also enabled.
Link: https://lore.kernel.org/r/20241011175657.249948-1-nirmal.patel@linux.intel.com
Signed-off-by: Nirmal Patel <nirmal.patel@linux.ntel.com>
Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Myron Stowe <mstowe@redhat.com>
JIRA: https://issues.redhat.com/browse/RHEL-67693
Upstream Status: f0639013d340580b72df95d012a93f35eeb0da64
commit f0639013d340580b72df95d012a93f35eeb0da64
Author: Krishna chaitanya chundru <quic_krichai@quicinc.com>
Date: Sat Nov 23 00:40:01 2024 +0530
PCI: qcom: Update ICC and OPP values after Link Up event
4581403f6792 ("PCI: qcom: Enumerate endpoints based on Link up event in
'global_irq' interrupt") added the Link Up-based enumeration support, but
did not update the ICC/OPP vote once link is up. Before that, the update
happened during probe and the endpoints may or may not be enumerated at
that time, so the ICC/OPP vote was not guaranteed to be accurate.
With Link Up-based enumeration support, the driver can request the accurate
vote based on the PCIe link.
Call qcom_pcie_icc_opp_update() in qcom_pcie_global_irq_thread() after
enumerating the endpoints.
Fixes: 4581403f6792 ("PCI: qcom: Enumerate endpoints based on Link up event in 'global_irq' interrupt")
Link: https://lore.kernel.org/r/20241123-remove_wait2-v5-3-b5f9e6b794c2@quicinc.com
Signed-off-by: Krishna chaitanya chundru <quic_krichai@quicinc.com>
[kwilczynski: commit log]
Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: Niklas Cassel <cassel@kernel.org>
Signed-off-by: Myron Stowe <mstowe@redhat.com>
JIRA: https://issues.redhat.com/browse/RHEL-67693
Upstream Status: 22a9120479a40a56c13c5e473a0100fad2e017c0
commit 22a9120479a40a56c13c5e473a0100fad2e017c0
Author: Siddharth Vadapalli <s-vadapalli@ti.com>
Date: Mon Nov 4 13:14:20 2024 +0530
PCI: j721e: Deassert PERST# after a delay of PCIE_T_PVPERL_MS milliseconds
According to Section 2.2 of the PCI Express Card Electromechanical
Specification (Revision 5.1), in order to ensure that the power and the
reference clock are stable, PERST# has to be deasserted after a delay of
100 milliseconds (TPVPERL).
Currently, it is being assumed that the power is already stable, which
is not necessarily true.
Hence, change the delay to PCIE_T_PVPERL_MS to guarantee that power and
reference clock are stable.
Fixes: f3e25911a4 ("PCI: j721e: Add TI J721E PCIe driver")
Fixes: f96b69713733 ("PCI: j721e: Use T_PERST_CLK_US macro")
Link: https://lore.kernel.org/r/20241104074420.1862932-1-s-vadapalli@ti.com
Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>
Signed-off-by: Myron Stowe <mstowe@redhat.com>
JIRA: https://issues.redhat.com/browse/RHEL-67693
Upstream Status: ba4a2e2317b9faeca9193ed6d3193ddc3cf2aba3
commit ba4a2e2317b9faeca9193ed6d3193ddc3cf2aba3
Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Date: Mon Oct 7 10:42:55 2024 +0530
PCI: qcom: Enable MSI interrupts together with Link up if 'Global IRQ' is supported
Currently, if 'Global IRQ' is supported by the platform, only the Link up
interrupt is enabled in the PARF_INT_ALL_MASK register. This masks MSIs
on some platforms. The MSI bits in PARF_INT_ALL_MASK register are enabled
by default in the hardware, but commit 4581403f6792 ("PCI: qcom: Enumerate
endpoints based on Link up event in 'global_irq' interrupt") disabled them
and enabled only the Link up interrupt. While MSI continued to work on the
SM8450 platform that was used to test the offending commit, on other
platforms like SM8250, X1E80100, MSIs are getting masked. And they require
enabling the MSI interrupt bits in the register to unmask (enable) the
MSIs.
Even though the MSI interrupt enable bits in PARF_INT_ALL_MASK are
described as 'diagnostic' interrupts in the internal documentation,
disabling them masks MSI on these platforms. Due to this, MSIs were not
reported to be received these platforms while supporting 'Global IRQ'.
So, enable the MSI interrupts along with the Link up interrupt in the
PARF_INT_ALL_MASK register if 'Global IRQ' is supported. This ensures that
the MSIs continue to work and also the driver is able to catch the Link
up interrupt for enumerating endpoint devices.
Fixes: 4581403f6792 ("PCI: qcom: Enumerate endpoints based on Link up event in 'global_irq' interrupt")
Closes: https://lore.kernel.org/linux-pci/9a692c98-eb0a-4d86-b642-ea655981ff53@kernel.org/
Link: https://lore.kernel.org/r/20241007051255.4378-1-manivannan.sadhasivam@linaro.org
Reported-by: Konrad Dybcio <konradybcio@kernel.org>
Tested-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> # SL7
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>
Reviewed-by: Qiang Yu <quic_qianyu@quicinc.com>
Signed-off-by: Myron Stowe <mstowe@redhat.com>
JIRA: https://issues.redhat.com/browse/RHEL-67693
Upstream Status: 308a40fb8fd9cfb1aa7d44f79980dfaef1a6c72f
commit 308a40fb8fd9cfb1aa7d44f79980dfaef1a6c72f
Author: Sean Anderson <sean.anderson@linux.dev>
Date: Fri May 31 12:13:36 2024 -0400
PCI: xilinx-nwl: Add PHY support
Add support for enabling/disabling PCIe PHYs. We can't really do
anything about failures in the disable/remove path, so just print an
error.
Link: https://lore.kernel.org/r/20240531161337.864994-7-sean.anderson@linux.dev
Signed-off-by: Sean Anderson <sean.anderson@linux.dev>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: Myron Stowe <mstowe@redhat.com>
JIRA: https://issues.redhat.com/browse/RHEL-67693
Upstream Status: cfd67903977b13f63340a4eb5a1cc890994f2c62
commit cfd67903977b13f63340a4eb5a1cc890994f2c62
Author: Sean Anderson <sean.anderson@linux.dev>
Date: Fri May 31 12:13:35 2024 -0400
PCI: xilinx-nwl: Clean up clock on probe failure/removal
Make sure we turn off the clock on probe failure and device removal.
Fixes: de0a01f52966 ("PCI: xilinx-nwl: Enable the clock through CCF")
Link: https://lore.kernel.org/r/20240531161337.864994-6-sean.anderson@linux.dev
Signed-off-by: Sean Anderson <sean.anderson@linux.dev>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: Myron Stowe <mstowe@redhat.com>
JIRA: https://issues.redhat.com/browse/RHEL-67693
Upstream Status: 78457cae24cb543650bec048927bfb4c164d060f
commit 78457cae24cb543650bec048927bfb4c164d060f
Author: Sean Anderson <sean.anderson@linux.dev>
Date: Fri May 31 12:13:34 2024 -0400
PCI: xilinx-nwl: Rate-limit misc interrupt messages
The conditions logged by the misc interrupt can occur repeatedly and
continuously. Avoid rendering the console unusable by rate-limiting
these messages.
Link: https://lore.kernel.org/r/20240531161337.864994-5-sean.anderson@linux.dev
Signed-off-by: Sean Anderson <sean.anderson@linux.dev>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: Myron Stowe <mstowe@redhat.com>
JIRA: https://issues.redhat.com/browse/RHEL-67693
Upstream Status: 0199d2f2bd8cd97b310f7ed82a067247d7456029
commit 0199d2f2bd8cd97b310f7ed82a067247d7456029
Author: Sean Anderson <sean.anderson@linux.dev>
Date: Fri May 31 12:13:32 2024 -0400
PCI: xilinx-nwl: Fix off-by-one in INTx IRQ handler
MSGF_LEG_MASK is laid out with INTA in bit 0, INTB in bit 1, INTC in bit 2,
and INTD in bit 3. Hardware IRQ numbers start at 0, and we register
PCI_NUM_INTX IRQs. So to enable INTA (aka hwirq 0) we should set bit 0.
Remove the subtraction of one.
This bug would cause INTx interrupts not to be delivered, as enabling INTB
would actually enable INTA, and enabling INTA wouldn't enable anything at
all. It is likely that this got overlooked for so long since most PCIe
hardware uses MSIs. This fixes the following UBSAN error:
UBSAN: shift-out-of-bounds in ../drivers/pci/controller/pcie-xilinx-nwl.c:389:11
shift exponent 18446744073709551615 is too large for 32-bit type 'int'
CPU: 1 PID: 61 Comm: kworker/u10:1 Not tainted 6.6.20+ #268
Hardware name: xlnx,zynqmp (DT)
Workqueue: events_unbound deferred_probe_work_func
Call trace:
dump_backtrace (arch/arm64/kernel/stacktrace.c:235)
show_stack (arch/arm64/kernel/stacktrace.c:242)
dump_stack_lvl (lib/dump_stack.c:107)
dump_stack (lib/dump_stack.c:114)
__ubsan_handle_shift_out_of_bounds (lib/ubsan.c:218 lib/ubsan.c:387)
nwl_unmask_leg_irq (drivers/pci/controller/pcie-xilinx-nwl.c:389 (discriminator 1))
irq_enable (kernel/irq/internals.h:234 kernel/irq/chip.c:170 kernel/irq/chip.c:439 kernel/irq/chip.c:432 kernel/irq/chip.c:345)
__irq_startup (kernel/irq/internals.h:239 kernel/irq/chip.c:180 kernel/irq/chip.c:250)
irq_startup (kernel/irq/chip.c:270)
__setup_irq (kernel/irq/manage.c:1800)
request_threaded_irq (kernel/irq/manage.c:2206)
pcie_pme_probe (include/linux/interrupt.h:168 drivers/pci/pcie/pme.c:348)
Fixes: 9a181e1093 ("PCI: xilinx-nwl: Modify IRQ chip for legacy interrupts")
Link: https://lore.kernel.org/r/20240531161337.864994-3-sean.anderson@linux.dev
Signed-off-by: Sean Anderson <sean.anderson@linux.dev>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Cc: stable@vger.kernel.org
Signed-off-by: Myron Stowe <mstowe@redhat.com>
JIRA: https://issues.redhat.com/browse/RHEL-67693
Upstream Status: 4654cf52cbd07cb2d6ab6f55bcc5eb2dae8b736a
commit 4654cf52cbd07cb2d6ab6f55bcc5eb2dae8b736a
Author: Riyan Dhiman <riyandhiman14@gmail.com>
Date: Sun Sep 1 14:56:02 2024 +0530
PCI: vmd: Fix indentation issue in vmd_shutdown()
The code in vmd_shutdown() had an indentation issue where spaces were
used instead of tabs. This commit corrects the indentation to use tabs,
adhering to the Linux kernel coding style guidelines.
Issue reported by the checkpatch.pl script:
ERROR: code indent should use tabs where possible
#1056: FILE: drivers/pci/controller/vmd.c:1056:
+ struct vmd_dev *vmd = pci_get_drvdata(dev);$
WARNING: please, no spaces at the start of a line
#1056: FILE: drivers/pci/controller/vmd.c:1056:
+ struct vmd_dev *vmd = pci_get_drvdata(dev);$
ERROR: code indent should use tabs where possible
#1058: FILE: drivers/pci/controller/vmd.c:1058:
+ vmd_remove_irq_domain(vmd);$
WARNING: please, no spaces at the start of a line
#1058: FILE: drivers/pci/controller/vmd.c:1058:
+ vmd_remove_irq_domain(vmd);$
No functional changes are intended.
Link: https://lore.kernel.org/linux-pci/20240901092602.17414-1-riyandhiman14@gmail.com
Signed-off-by: Riyan Dhiman <riyandhiman14@gmail.com>
[kwilczynski: commit log]
Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>
Signed-off-by: Myron Stowe <mstowe@redhat.com>
JIRA: https://issues.redhat.com/browse/RHEL-67693
Upstream Status: 5603a3491b368faf180472f4bdc6480c13c7385e
commit 5603a3491b368faf180472f4bdc6480c13c7385e
Author: Colin Ian King <colin.i.king@gmail.com>
Date: Thu Aug 22 21:59:41 2024 +0100
PCI: rcar-gen4: Make read-only const array check_addr static
Don't populate the const read-only array check_addr on the stack at
run time, instead make it static.
Link: https://lore.kernel.org/linux-pci/20240822205941.643187-1-colin.i.king@gmail.com
Signed-off-by: Colin Ian King <colin.i.king@gmail.com>
[kwilczynski: refactor array definition]
Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Myron Stowe <mstowe@redhat.com>
JIRA: https://issues.redhat.com/browse/RHEL-67693
Upstream Status: d45736b5984954da71292d858f277bac9c70cd2e
commit d45736b5984954da71292d858f277bac9c70cd2e
Author: Shashank Babu Chinta Venkata <quic_schintav@quicinc.com>
Date: Wed Sep 11 20:56:28 2024 +0530
PCI: qcom: Add equalization settings for 16.0 GT/s
During high data transmission rates such as 16.0 GT/s, there is an
increased risk of signal loss due to poor channel quality and
interference. This can impact receiver's ability to capture signals
accurately.
Hence, as signal compensation is achieved through appropriate lane
equalization, apply lane equalization settings at both transmitter
and receiver which results in an increase in the PCIe signal strength.
While at it, modify the pcie-tegra194 driver to make use of the
common GEN3_EQ_CONTROL_OFF definitions in pcie-designware.h.
Link: https://lore.kernel.org/linux-pci/20240911-pci-qcom-gen4-stability-v7-3-743f5c1fd027@linaro.org
Tested-by: Johan Hovold <johan+linaro@kernel.org>
Signed-off-by: Shashank Babu Chinta Venkata <quic_schintav@quicinc.com>
[mani: dropped the code refactoring and minor changes]
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
[kwilczynski: commit log]
Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>
Reviewed-by: Johan Hovold <johan+linaro@kernel.org>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Myron Stowe <mstowe@redhat.com>
JIRA: https://issues.redhat.com/browse/RHEL-67693
Upstream Status: 19a69cbd9d436fe503e5cb6dade76fe371244d4f
commit 19a69cbd9d436fe503e5cb6dade76fe371244d4f
Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Date: Wed Sep 11 20:56:27 2024 +0530
PCI: dwc: Always cache the maximum link speed value in dw_pcie::max_link_speed
Currently, the dw_pcie::max_link_speed has a valid value only if the
controller driver restricts the maximum link speed in the driver or if
the platform does so in the devicetree using the 'max-link-speed'
property.
But having the maximum supported link speed of the platform would be
helpful for the vendor drivers to configure any link specific settings.
So in the case of non-valid value in dw_pcie::max_link_speed, just cache
the hardware default value from Link Capability register.
While at it, remove the 'max_link_speed' argument to the
dw_pcie_link_set_max_speed() function since the value can be
retrieved within the function.
Link: https://lore.kernel.org/linux-pci/20240911-pci-qcom-gen4-stability-v7-2-743f5c1fd027@linaro.org
Tested-by: Johan Hovold <johan+linaro@kernel.org>
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
[kwilczynski: commit log]
Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>
Reviewed-by: Frank Li <Frank.Li@nxp.com>
Reviewed-by: Johan Hovold <johan+linaro@kernel.org>
Signed-off-by: Myron Stowe <mstowe@redhat.com>
JIRA: https://issues.redhat.com/browse/RHEL-67693
Upstream Status: d3745e3ae6c0eec517d431be926742b6e8b9b64a
commit d3745e3ae6c0eec517d431be926742b6e8b9b64a
Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Date: Fri Aug 30 13:53:19 2024 +0530
PCI: qcom-ep: Enable controller resources like PHY only after refclk is available
qcom_pcie_enable_resources() is called by qcom_pcie_ep_probe() and it
enables the controller resources like clocks, regulator, PHY. On one of the
new unreleased Qcom SoC, PHY enablement depends on the active refclk. And
on all of the supported Qcom endpoint SoCs, refclk comes from the host
(RC). So calling qcom_pcie_enable_resources() without refclk causes the
NoC (Network On Chip) error in the endpoint SoC and in turn results in a
whole SoC crash and rebooting into EDL (Emergency Download) mode which is
an unrecoverable state.
But qcom_pcie_enable_resources() is already called by
qcom_pcie_perst_deassert() when PERST# is deasserted, and refclk is
available at that time.
Hence, remove the unnecessary call to qcom_pcie_enable_resources() from
qcom_pcie_ep_probe() to prevent the above mentioned crash.
It should be noted that this commit prevents the crash only under normal
working condition (booting endpoint before host), but the crash may also
occur if PERST# assert happens at the wrong time. For avoiding the crash
completely, it is recommended to use SRIS mode which allows the endpoint
SoC to generate its own refclk. The driver is not supporting SRIS mode
currently, but will be added in the future.
Fixes: 869bc5253406 ("PCI: dwc: ep: Fix DBI access failure for drivers requiring refclk from host")
Link: https://lore.kernel.org/linux-pci/20240830082319.51387-1-manivannan.sadhasivam@linaro.org
Tested-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>
Signed-off-by: Myron Stowe <mstowe@redhat.com>
JIRA: https://issues.redhat.com/browse/RHEL-67693
Upstream Status: 10ba0854c5e6165b58e17bda5fb671e729fecf9e
commit 10ba0854c5e6165b58e17bda5fb671e729fecf9e
Author: Prudhvi Yarlagadda <quic_pyarlaga@quicinc.com>
Date: Wed Aug 14 15:03:38 2024 -0700
PCI: qcom: Disable mirroring of DBI and iATU register space in BAR region
PARF hardware block which is a wrapper on top of DWC PCIe controller
mirrors the DBI and ATU register space. It uses PARF_SLV_ADDR_SPACE_SIZE
register to get the size of the memory block to be mirrored and uses
PARF_DBI_BASE_ADDR, PARF_ATU_BASE_ADDR registers to determine the base
address of DBI and ATU space inside the memory block that is being
mirrored.
When a memory region which is located above the SLV_ADDR_SPACE_SIZE
boundary is used for BAR region then there could be an overlap of DBI and
ATU address space that is getting mirrored and the BAR region. This
results in DBI and ATU address space contents getting updated when a PCIe
function driver tries updating the BAR/MMIO memory region. Reference
memory map of the PCIe memory region with DBI and ATU address space
overlapping BAR region is as below.
|---------------|
| |
| |
------- --------|---------------|
| | |---------------|
| | | DBI |
| | |---------------|---->DBI_BASE_ADDR
| | | |
| | | |
| PCIe | |---->2*SLV_ADDR_SPACE_SIZE
| BAR/MMIO|---------------|
| Region | ATU |
| | |---------------|---->ATU_BASE_ADDR
| | | |
PCIe | |---------------|
Memory | | DBI |
Region | |---------------|---->DBI_BASE_ADDR
| | | |
| --------| |
| | |---->SLV_ADDR_SPACE_SIZE
| |---------------|
| | ATU |
| |---------------|---->ATU_BASE_ADDR
| | |
| |---------------|
| | DBI |
| |---------------|---->DBI_BASE_ADDR
| | |
| | |
----------------|---------------|
| |
| |
| |
|---------------|
Currently memory region beyond the SLV_ADDR_SPACE_SIZE boundary is not
used for BAR region which is why the above mentioned issue is not
encountered. This issue is discovered as part of internal testing when we
tried moving the BAR region beyond the SLV_ADDR_SPACE_SIZE boundary. Hence
we are trying to fix this.
As PARF hardware block mirrors DBI and ATU register space after every
PARF_SLV_ADDR_SPACE_SIZE (default 0x1000000) boundary multiple, program
maximum possible size to this register by writing 0x80000000 to it(it
considers only powers of 2 as values) to avoid mirroring DBI and ATU to
BAR/MMIO region. Write the physical base address of DBI and ATU register
blocks to PARF_DBI_BASE_ADDR (default 0x0) and PARF_ATU_BASE_ADDR (default
0x1000) respectively to make sure DBI and ATU blocks are at expected
memory locations.
The register offsets PARF_DBI_BASE_ADDR_V2, PARF_SLV_ADDR_SPACE_SIZE_V2
and PARF_ATU_BASE_ADDR are applicable for platforms that use Qcom IP
rev 1.9.0, 2.7.0 and 2.9.0. PARF_DBI_BASE_ADDR_V2 and
PARF_SLV_ADDR_SPACE_SIZE_V2 are applicable for Qcom IP rev 2.3.3.
PARF_DBI_BASE_ADDR and PARF_SLV_ADDR_SPACE_SIZE are applicable for Qcom
IP rev 1.0.0, 2.3.2 and 2.4.0. Update init()/post_init() functions of the
respective Qcom IP versions to program applicable PARF_DBI_BASE_ADDR,
PARF_SLV_ADDR_SPACE_SIZE and PARF_ATU_BASE_ADDR register offsets. Update
the SLV_ADDR_SPACE_SZ macro to 0x80000000 to set highest bit in
PARF_SLV_ADDR_SPACE_SIZE register.
Cache DBI and iATU physical addresses in 'struct dw_pcie' so that
pcie_qcom.c driver can program these addresses in the PARF_DBI_BASE_ADDR
and PARF_ATU_BASE_ADDR registers.
Suggested-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Link: https://lore.kernel.org/linux-pci/20240814220338.1969668-1-quic_pyarlaga@quicinc.com
Signed-off-by: Prudhvi Yarlagadda <quic_pyarlaga@quicinc.com>
Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: Mayank Rana <quic_mrana@quicinc.com>
Signed-off-by: Myron Stowe <mstowe@redhat.com>
JIRA: https://issues.redhat.com/browse/RHEL-67693
Upstream Status: 4581403f67929d02c197cb187c4e1e811c9e762a
commit 4581403f67929d02c197cb187c4e1e811c9e762a
Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Date: Wed Aug 28 21:16:21 2024 +0530
PCI: qcom: Enumerate endpoints based on Link up event in 'global_irq' interrupt
Historically, Qcom PCIe RC controllers lacked standard hotplug support. So
when an endpoint is attached to the SoC, users have to rescan the bus
manually to enumerate the device. But this can be avoided by using the Link
up event exposed by the Qcom specific 'global_irq' interrupt.
Qcom PCIe RC controllers are capable of generating the 'global' SPI
interrupt to the host CPUs. The device driver can use this interrupt to
identify events such as PCIe link specific events, safety events etc...
One such event is the PCIe Link up event generated when an endpoint is
detected on the bus and the Link is 'up'. This event can be used to
enumerate the PCIe endpoint devices without user intervention.
So add support for capturing the PCIe Link up event using the 'global'
interrupt in the driver. Once the Link up event is received, the bus
underneath the host bridge is scanned to enumerate PCIe endpoint devices.
All of the Qcom SoCs have only one Root Port per controller instance. So
only a single 'Link up' event is generated for the PCIe controller.
Link: https://lore.kernel.org/linux-pci/20240828-pci-qcom-hotplug-v4-11-263a385fbbcb@linaro.org
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Myron Stowe <mstowe@redhat.com>
JIRA: https://issues.redhat.com/browse/RHEL-67693
Upstream Status: bba1251edf8501f85304b7d65ae2aac309f2d0a1
commit bba1251edf8501f85304b7d65ae2aac309f2d0a1
Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Date: Wed Aug 28 21:16:16 2024 +0530
PCI: qcom-ep: Modify 'global_irq' and 'perst_irq' IRQ device names
Currently, the IRQ device name for both of these IRQs doesn't have Qcom
specific prefix and PCIe domain number. This causes 2 issues:
1. Pollutes the global IRQ namespace since 'global' is a common name.
2. When more than one EP controller instance is present in the SoC, naming
conflict will occur.
Hence, add 'qcom_pcie_ep_' prefix and PCIe domain number suffix to the IRQ
names to uniquely identify the IRQs and also to fix the above mentioned
issues.
Link: https://lore.kernel.org/linux-pci/20240828-pci-qcom-hotplug-v4-6-263a385fbbcb@linaro.org
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Myron Stowe <mstowe@redhat.com>
JIRA: https://issues.redhat.com/browse/RHEL-67693
Upstream Status: 95bebcbd657cf8eb86025a2b20961e43d2e433f5
commit 95bebcbd657cf8eb86025a2b20961e43d2e433f5
Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Date: Wed Aug 28 21:16:12 2024 +0530
PCI: qcom-ep: Reword the error message for receiving unknown global IRQ event
Current error message just prints the contents of PARF_INT_ALL_STATUS
register as if like the IRQ event number. It could mislead the users.
Reword it to make it clear that the error message is actually showing the
interrupt status register to help debug spurious IRQ events.
While at it, let's also switch over to dev_WARN_ONCE() so that any IRQ
storm won't flood the kernel log buffer.
Link: https://lore.kernel.org/linux-pci/20240828-pci-qcom-hotplug-v4-2-263a385fbbcb@linaro.org
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Myron Stowe <mstowe@redhat.com>
JIRA: https://issues.redhat.com/browse/RHEL-67693
Upstream Status: 3858e8a5ea719411d6682e2218c41eff27092463
commit 3858e8a5ea719411d6682e2218c41eff27092463
Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Date: Wed Aug 28 21:16:11 2024 +0530
PCI: qcom-ep: Drop the redundant masking of global IRQ events
Once the events are disabled in PARF_INT_ALL_MASK register, only the
enabled events will generate global IRQ. So there is no need to do the
masking again in the IRQ handler, drop it.
If there are any spurious IRQs getting generated, they will be reported
using the existing dev_err() in the handler.
Link: https://lore.kernel.org/linux-pci/20240828-pci-qcom-hotplug-v4-1-263a385fbbcb@linaro.org
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Myron Stowe <mstowe@redhat.com>
JIRA: https://issues.redhat.com/browse/RHEL-67693
Upstream Status: ee9eabbe3f0f0c7458d89840add97e54d4e0bccf
commit ee9eabbe3f0f0c7458d89840add97e54d4e0bccf
Author: Lorenzo Bianconi <lorenzo@kernel.org>
Date: Wed Jul 3 18:12:43 2024 +0200
PCI: mediatek-gen3: Rely on reset_bulk APIs for PHY reset lines
Use reset_bulk APIs to manage PHY reset lines.
This is a preliminary patch in order to add Airoha EN7581 PCIe support.
Link: https://lore.kernel.org/linux-pci/3ceb83bc0defbcf868521f8df4b9100e55ec2614.1720022580.git.lorenzo@kernel.org
Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>
Tested-by: Zhengping Zhang <zhengping.zhang@airoha.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Acked-by: Jianjun Wang <jianjun.wang@mediatek.com>
Signed-off-by: Myron Stowe <mstowe@redhat.com>
JIRA: https://issues.redhat.com/browse/RHEL-67693
Upstream Status: dc869a40d73ee6e9f47d683690ae507e30e56044
commit dc869a40d73ee6e9f47d683690ae507e30e56044
Author: Lorenzo Bianconi <lorenzo@kernel.org>
Date: Wed Jul 3 18:12:42 2024 +0200
PCI: mediatek-gen3: Add mtk_gen3_pcie_pdata data structure
Introduce mtk_gen3_pcie_pdata data structure in order to define
multiple callbacks for each supported SoC.
This is a preliminary patch to introduce EN7581 PCIe support.
Link: https://lore.kernel.org/linux-pci/c193d1a87505d045e2e0ef33317bce17012ee095.1720022580.git.lorenzo@kernel.org
Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>
Tested-by: Zhengping Zhang <zhengping.zhang@airoha.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Acked-by: Jianjun Wang <jianjun.wang@mediatek.com>
Signed-off-by: Myron Stowe <mstowe@redhat.com>
JIRA: https://issues.redhat.com/browse/RHEL-67693
Upstream Status: c500a86693a126c9393e602741e348f80f1b0fc5
commit c500a86693a126c9393e602741e348f80f1b0fc5
Author: Alexandra Diupina <adiupina@astralinux.ru>
Date: Tue Sep 3 14:58:23 2024 +0300
PCI: kirin: Fix buffer overflow in kirin_pcie_parse_port()
Within kirin_pcie_parse_port(), the pcie->num_slots is compared to
pcie->gpio_id_reset size (MAX_PCI_SLOTS) which is correct and would lead
to an overflow.
Thus, fix condition to pcie->num_slots + 1 >= MAX_PCI_SLOTS and move
pcie->num_slots increment below the if-statement to avoid out-of-bounds
array access.
Found by Linux Verification Center (linuxtesting.org) with SVACE.
Fixes: b22dbbb24571 ("PCI: kirin: Support PERST# GPIOs for HiKey970 external PEX 8606 bridge")
Link: https://lore.kernel.org/linux-pci/20240903115823.30647-1-adiupina@astralinux.ru
Signed-off-by: Alexandra Diupina <adiupina@astralinux.ru>
[kwilczynski: commit log]
Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>
Reviewed-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
Signed-off-by: Myron Stowe <mstowe@redhat.com>
JIRA: https://issues.redhat.com/browse/RHEL-67693
Upstream Status: c538d40f365b5b6d7433d371710f58e8b266fb19
commit c538d40f365b5b6d7433d371710f58e8b266fb19
Author: Théo Lebrun <theo.lebrun@bootlin.com>
Date: Wed Jun 19 12:15:15 2024 +0200
PCI: j721e: Add suspend and resume support
Add suspend and resume support. Only the Root Complex mode is supported.
During the suspend stage PERST# is asserted, then deasserted during the
resume stage.
Link: https://lore.kernel.org/linux-pci/20240102-j7200-pcie-s2r-v7-7-a2f9156da6c3@bootlin.com
Signed-off-by: Théo Lebrun <theo.lebrun@bootlin.com>
Signed-off-by: Thomas Richard <thomas.richard@bootlin.com>
[kwilczynski: commit log, update references to the PCI SIG specification]
Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>
Reviewed-by: Siddharth Vadapalli <s-vadapalli@ti.com>
Signed-off-by: Myron Stowe <mstowe@redhat.com>
JIRA: https://issues.redhat.com/browse/RHEL-67693
Upstream Status: f96b6971373382855bc964f1c067bd6dc41cf0ab
commit f96b6971373382855bc964f1c067bd6dc41cf0ab
Author: Thomas Richard <thomas.richard@bootlin.com>
Date: Wed Jun 19 12:15:14 2024 +0200
PCI: j721e: Use T_PERST_CLK_US macro
Use the T_PERST_CLK_US macro, and the fsleep() function instead of
usleep_range().
Link: https://lore.kernel.org/linux-pci/20240102-j7200-pcie-s2r-v7-6-a2f9156da6c3@bootlin.com
Signed-off-by: Thomas Richard <thomas.richard@bootlin.com>
Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>
Signed-off-by: Myron Stowe <mstowe@redhat.com>
JIRA: https://issues.redhat.com/browse/RHEL-67693
Upstream Status: b8600b8791cb2b7c8be894846b1ecddba7291680
commit b8600b8791cb2b7c8be894846b1ecddba7291680
Author: Théo Lebrun <theo.lebrun@bootlin.com>
Date: Wed Jun 19 12:15:12 2024 +0200
PCI: j721e: Add reset GPIO to struct j721e_pcie
Add reset GPIO to struct j721e_pcie, so it can be used at suspend and
resume stages.
Link: https://lore.kernel.org/linux-pci/20240102-j7200-pcie-s2r-v7-4-a2f9156da6c3@bootlin.com
Signed-off-by: Théo Lebrun <theo.lebrun@bootlin.com>
Signed-off-by: Thomas Richard <thomas.richard@bootlin.com>
Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>
Signed-off-by: Myron Stowe <mstowe@redhat.com>
JIRA: https://issues.redhat.com/browse/RHEL-67693
Upstream Status: 7d7ce746a9e109ab0aa30ad3c6107e601cf17045
commit 7d7ce746a9e109ab0aa30ad3c6107e601cf17045
Author: Thomas Richard <thomas.richard@bootlin.com>
Date: Wed Jun 19 12:15:11 2024 +0200
PCI: j721e: Use dev_err_probe() in the probe() function
Use dev_err_probe() instead of dev_err() in the probe() function to
simplify the code and standardize the error output.
Link: https://lore.kernel.org/linux-pci/20240102-j7200-pcie-s2r-v7-3-a2f9156da6c3@bootlin.com
Signed-off-by: Thomas Richard <thomas.richard@bootlin.com>
Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>
Reviewed-by: Francesco Dolcini <francesco.dolcini@toradex.com>
Signed-off-by: Myron Stowe <mstowe@redhat.com>
JIRA: https://issues.redhat.com/browse/RHEL-67693
Upstream Status: 063c938928dc80c2bfd66f34df48344db22e009b
commit 063c938928dc80c2bfd66f34df48344db22e009b
Author: Thomas Richard <thomas.richard@bootlin.com>
Date: Wed Jun 19 12:15:10 2024 +0200
PCI: cadence: Set cdns_pcie_host_init() global
During the resume sequence of the host, cdns_pcie_host_init() needs to be
called, so set it global.
The dev function parameter is removed, as it isn't used.
Link: https://lore.kernel.org/linux-pci/20240102-j7200-pcie-s2r-v7-2-a2f9156da6c3@bootlin.com
Signed-off-by: Thomas Richard <thomas.richard@bootlin.com>
Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>
Reviewed-by: Siddharth Vadapalli <s-vadapalli@ti.com>
Signed-off-by: Myron Stowe <mstowe@redhat.com>
JIRA: https://issues.redhat.com/browse/RHEL-67693
Upstream Status: d1b6f2e2ce4d8b17d9f3558c98a1517b864bfd03
commit d1b6f2e2ce4d8b17d9f3558c98a1517b864bfd03
Author: Thomas Richard <thomas.richard@bootlin.com>
Date: Wed Jun 19 12:15:09 2024 +0200
PCI: cadence: Extract link setup sequence from cdns_pcie_host_setup()
The function cdns_pcie_host_setup() mixes probe structure and link setup.
The link setup must be done during the resume sequence. So extract it from
cdns_pcie_host_setup() and create a dedicated function.
Link: https://lore.kernel.org/linux-pci/20240102-j7200-pcie-s2r-v7-1-a2f9156da6c3@bootlin.com
Signed-off-by: Thomas Richard <thomas.richard@bootlin.com>
Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>
Reviewed-by: Siddharth Vadapalli <s-vadapalli@ti.com>
Signed-off-by: Myron Stowe <mstowe@redhat.com>
JIRA: https://issues.redhat.com/browse/RHEL-67693
Upstream Status: 82c4be4168e26a5593aaa1002b5678128a638824
commit 82c4be4168e26a5593aaa1002b5678128a638824
Author: Siddharth Vadapalli <s-vadapalli@ti.com>
Date: Thu Aug 29 16:23:16 2024 +0530
PCI: j721e: Enable ACSPCIE Refclk if "ti,syscon-acspcie-proxy-ctrl" exists
The ACSPCIE module is capable of driving the reference clock required by
the PCIe Endpoint device. It is an alternative to on-board and external
reference clock generators. Enabling the output from the ACSPCIE module's
PAD IO Buffers requires clearing the "PAD IO disable" bits of the
ACSPCIE_PROXY_CTRL register in the CTRL_MMR register space.
Add support to enable the ACSPCIE reference clock output using the optional
device-tree property "ti,syscon-acspcie-proxy-ctrl".
Link: https://lore.kernel.org/linux-pci/20240829105316.1483684-3-s-vadapalli@ti.com
Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Myron Stowe <mstowe@redhat.com>
JIRA: https://issues.redhat.com/browse/RHEL-67693
Upstream Status: 4d60f6d4b8fa4d7bad4aeb2b3ee5c10425bc60a4
commit 4d60f6d4b8fa4d7bad4aeb2b3ee5c10425bc60a4
Author: Siddharth Vadapalli <s-vadapalli@ti.com>
Date: Tue Aug 27 17:54:22 2024 +0530
PCI: dra7xx: Fix error handling when IRQ request fails in probe
Commit d4c7d1a089 ("PCI: dwc: dra7xx: Push request_irq()
call to the bottom of probe") moved the IRQ request for
"dra7xx-pcie-main" towards the end of dra7xx_pcie_probe().
However, the error handling does not take into account the
initialization performed by either dra7xx_add_pcie_port() or
dra7xx_add_pcie_ep(), depending on the mode of operation.
Fix the error handling to address this.
Fixes: d4c7d1a089 ("PCI: dwc: dra7xx: Push request_irq() call to the bottom of probe")
Link: https://lore.kernel.org/linux-pci/20240827122422.985547-3-s-vadapalli@ti.com
Tested-by: Udit Kumar <u-kumar1@ti.com>
Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
[kwilczynski: commit log]
Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>
Reviewed-by: Kevin Hilman <khilman@baylibre.com>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Cc: stable@vger.kernel.org
Signed-off-by: Myron Stowe <mstowe@redhat.com>
JIRA: https://issues.redhat.com/browse/RHEL-67693
Upstream Status: 03f84b3baba7836bdfc162c19288d5ce1aa92890
commit 03f84b3baba7836bdfc162c19288d5ce1aa92890
Author: Siddharth Vadapalli <s-vadapalli@ti.com>
Date: Tue Aug 27 17:54:21 2024 +0530
PCI: dra7xx: Fix threaded IRQ request for "dra7xx-pcie-main" IRQ
Commit da87d35a6e51 ("PCI: dra7xx: Use threaded IRQ handler for
"dra7xx-pcie-main" IRQ") switched from devm_request_irq() to
devm_request_threaded_irq() for the "dra7xx-pcie-main" interrupt.
Since the primary handler was set to NULL, the "IRQF_ONESHOT" flag
should have also been set. Fix this.
Fixes: da87d35a6e51 ("PCI: dra7xx: Use threaded IRQ handler for "dra7xx-pcie-main" IRQ")
Suggested-by: Vignesh Raghavendra <vigneshr@ti.com>
Link: https://lore.kernel.org/linux-pci/20240827122422.985547-2-s-vadapalli@ti.com
Reported-by: Udit Kumar <u-kumar1@ti.com>
Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>
Reviewed-by: Kevin Hilman <khilman@baylibre.com>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Cc: stable@vger.kernel.org
Signed-off-by: Myron Stowe <mstowe@redhat.com>
JIRA: https://issues.redhat.com/browse/RHEL-67693
Upstream Status: c3d95aa93fd8549588097b0701b3835920fd8533
commit c3d95aa93fd8549588097b0701b3835920fd8533
Author: Bjorn Helgaas <bhelgaas@google.com>
Date: Tue Sep 3 15:31:33 2024 -0500
PCI: cadence: Drop excess cdns_pcie_rc.dev kerneldoc description
Struct cdns_pcie_rc once had a .dev member, but it was removed by
bd22885aa1 ("PCI: cadence: Refactor driver to use as a core library").
Drop the extra kerneldoc for it.
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: Myron Stowe <mstowe@redhat.com>
JIRA: https://issues.redhat.com/browse/RHEL-67693
Upstream Status: 91e5d15c7b198ecea27407e04cff2fed2d4c2c75
commit 91e5d15c7b198ecea27407e04cff2fed2d4c2c75
Author: Jim Quinlan <james.quinlan@broadcom.com>
Date: Thu Aug 15 18:57:26 2024 -0400
PCI: brcmstb: Enable 7712 SoCs
The Broadcom STB 7712 is the sibling chip of the RPi 5 (2712). It has
one PCIe controller with a single port, supports gen2 and one lane only.
The current revision of the chip is "C0" or "C1".
Link: https://lore.kernel.org/linux-pci/20240815225731.40276-14-james.quinlan@broadcom.com
Signed-off-by: Jim Quinlan <james.quinlan@broadcom.com>
[kwilczynski: commit log]
Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>
Reviewed-by: Florian Fainelli <florian.fainelli@broadcom.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: Stanimir Varbanov <svarbanov@suse.de>
Signed-off-by: Myron Stowe <mstowe@redhat.com>
JIRA: https://issues.redhat.com/browse/RHEL-67693
Upstream Status: 8215851c74f9eb5a9e028834db0ab03d3a6e47e4
commit 8215851c74f9eb5a9e028834db0ab03d3a6e47e4
Author: Jim Quinlan <james.quinlan@broadcom.com>
Date: Thu Aug 15 18:57:25 2024 -0400
PCI: brcmstb: Change field name from 'type' to 'soc_base'
The 'type' field used in the driver to discern SoC differences is
confusing; change it to the more apt 'soc_base'.
The 'base' is because some SoCs have the same characteristics as
previous SoCs so it is convenient to classify them in the same group.
Link: https://lore.kernel.org/linux-pci/20240815225731.40276-13-james.quinlan@broadcom.com
Signed-off-by: Jim Quinlan <james.quinlan@broadcom.com>
[kwilczynski: commit log]
Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>
Reviewed-by: Florian Fainelli <florian.fainelli@broadcom.com>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Myron Stowe <mstowe@redhat.com>
JIRA: https://issues.redhat.com/browse/RHEL-67693
Upstream Status: 6f61062fce866e2ff1f3300b278e93d939a846a0
commit 6f61062fce866e2ff1f3300b278e93d939a846a0
Author: Jim Quinlan <james.quinlan@broadcom.com>
Date: Thu Aug 15 18:57:24 2024 -0400
PCI: brcmstb: Check return value of all reset_control_* calls
Always check the return value for invocations of reset_control_xxx() and
propagate the error to the next level.
Although the current functions in reset-brcmstb.c cannot fail, this may
someday change.
Link: https://lore.kernel.org/linux-pci/20240815225731.40276-12-james.quinlan@broadcom.com
Signed-off-by: Jim Quinlan <james.quinlan@broadcom.com>
[kwilczynski: commit log]
Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>
Reviewed-by: Florian Fainelli <florian.fainelli@broadcom.com>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: Stanimir Varbanov <svarbanov@suse.de>
Signed-off-by: Myron Stowe <mstowe@redhat.com>
JIRA: https://issues.redhat.com/browse/RHEL-67693
Upstream Status: ae6476c6de187bea90c729e3e0188143300fa671
commit ae6476c6de187bea90c729e3e0188143300fa671
Author: Jim Quinlan <james.quinlan@broadcom.com>
Date: Thu Aug 15 18:57:23 2024 -0400
PCI: brcmstb: Refactor for chips with many regular inbound windows
Provide support for new chips with multiple inbound windows while
keeping the legacy support for the older chips.
In existing chips there are three inbound windows with fixed purposes:
the first was for mapping SoC internal registers, the second was for
memory, and the third was for memory but with the endian swapped.
Typically, only one window was used.
Complicating the inbound window usage was the fact that the PCIe HW
would do a baroque internal mapping of system memory, and concatenate
the regions of multiple memory controllers.
Newer chips such as the 7712 and Cable Modem SoCs take a step forward
and drop the internal mapping while providing for multiple inbound
windows. This works in concert with the dma-ranges property, where each
provided range becomes an inbound window.
Link: https://lore.kernel.org/linux-pci/20240815225731.40276-11-james.quinlan@broadcom.com
Co-developed-by: Riyan Dhiman <riyandhiman14@gmail.com>
Signed-off-by: Riyan Dhiman <riyandhiman14@gmail.com>
Signed-off-by: Jim Quinlan <james.quinlan@broadcom.com>
[kwilczynski: commit log, wrap code comments to 80 columns]
Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>
Reviewed-by: Florian Fainelli <florian.fainelli@broadcom.com>
Reviewed-by: Stanimir Varbanov <svarbanov@suse.de>
Acked-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Myron Stowe <mstowe@redhat.com>
JIRA: https://issues.redhat.com/browse/RHEL-67693
Upstream Status: e1c88956e200e225f2712de4b5e2be923cf559fc
commit e1c88956e200e225f2712de4b5e2be923cf559fc
Author: Jim Quinlan <james.quinlan@broadcom.com>
Date: Thu Aug 15 18:57:22 2024 -0400
PCI: brcmstb: Don't conflate the reset rescal with PHY ctrl
Add a "has_phy" field indicating that the internal PHY has SW control
that requires configuration. Some previous chips only required the
firing of the "rescal" reset controller.
This change requires us to give the 7216 SoC its own cfg_data structure.
Link: https://lore.kernel.org/linux-pci/20240815225731.40276-10-james.quinlan@broadcom.com
Signed-off-by: Jim Quinlan <james.quinlan@broadcom.com>
[kwilczynski: commit log]
Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>
Tested-by: Florian Fainelli <florian.fainelli@broadcom.com>
Reviewed-by: Florian Fainelli <florian.fainelli@broadcom.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: Stanimir Varbanov <svarbanov@suse.de>
Signed-off-by: Myron Stowe <mstowe@redhat.com>
JIRA: https://issues.redhat.com/browse/RHEL-67693
Upstream Status: 30eb2080fe2043c3e61c1ae4bb6917800b10fb08
commit 30eb2080fe2043c3e61c1ae4bb6917800b10fb08
Author: Jim Quinlan <james.quinlan@broadcom.com>
Date: Thu Aug 15 18:57:20 2024 -0400
PCI: brcmstb: PCI: brcmstb: Make HARD_DEBUG, INTR2_CPU_BASE offsets SoC-specific
Do preparatory work for the 7712 SoC, which is introduced in a
future commit.
Our HW design has changed two register offsets for the 7712, where
previously it was a common value for all Broadcom SoCs with PCIe
cores.
Specifically, the two offsets are to the registers HARD_DEBUG and
INTR2_CPU_BASE.
Link: https://lore.kernel.org/linux-pci/20240815225731.40276-8-james.quinlan@broadcom.com
Signed-off-by: Jim Quinlan <james.quinlan@broadcom.com>
[kwilczynski: commit log]
Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>
Tested-by: Florian Fainelli <florian.fainelli@broadcom.com>
Reviewed-by: Florian Fainelli <florian.fainelli@broadcom.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: Stanimir Varbanov <svarbanov@suse.de>
Signed-off-by: Myron Stowe <mstowe@redhat.com>
JIRA: https://issues.redhat.com/browse/RHEL-67693
Upstream Status: 8201360218c6a42b3f7ff03d8908bd345e3620f4
commit 8201360218c6a42b3f7ff03d8908bd345e3620f4
Author: Jim Quinlan <james.quinlan@broadcom.com>
Date: Thu Aug 15 18:57:19 2024 -0400
PCI: brcmstb: Use swinit reset if available
The 7712 SoC adds a software init reset device for the PCIe HW.
If found in the DT node, use it.
Link: https://lore.kernel.org/linux-pci/20240815225731.40276-7-james.quinlan@broadcom.com
Signed-off-by: Jim Quinlan <james.quinlan@broadcom.com>
Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>
Reviewed-by: Florian Fainelli <florian.fainelli@broadcom.com>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Myron Stowe <mstowe@redhat.com>
JIRA: https://issues.redhat.com/browse/RHEL-67693
Upstream Status: 46cb27f671f2148005ee556b895d6372c6608e27
commit 46cb27f671f2148005ee556b895d6372c6608e27
Author: Jim Quinlan <james.quinlan@broadcom.com>
Date: Thu Aug 15 18:57:18 2024 -0400
PCI: brcmstb: Use bridge reset if available
The 7712 SoC has a bridge reset which can be described in the device
tree.
Use it if present. Otherwise, continue to use the legacy method to
reset the bridge.
Link: https://lore.kernel.org/linux-pci/20240815225731.40276-6-james.quinlan@broadcom.com
Signed-off-by: Jim Quinlan <james.quinlan@broadcom.com>
[kwilczynski: commit log, refactored function brcm_pcie_bridge_sw_init_set_generic()]
Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>
Reviewed-by: Florian Fainelli <florian.fainelli@broadcom.com>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: Stanimir Varbanov <svarbanov@suse.de>
Signed-off-by: Myron Stowe <mstowe@redhat.com>
JIRA: https://issues.redhat.com/browse/RHEL-67693
Upstream Status: 64706ba771f5e8f05b26a1293beed23e83a81b25
commit 64706ba771f5e8f05b26a1293beed23e83a81b25
Author: Jim Quinlan <james.quinlan@broadcom.com>
Date: Thu Aug 15 18:57:17 2024 -0400
PCI: brcmstb: Use common error handling code in brcm_pcie_probe()
Refactor the error handling in the bottom half of the probe function
for readability.
The invocation of clk_prepare_enable() is moved lower in the function
and this simplifies a couple of return paths. The dev_err_probe() is
also used when it is apt.
Link: https://lore.kernel.org/linux-pci/20240815225731.40276-5-james.quinlan@broadcom.com
Signed-off-by: Jim Quinlan <james.quinlan@broadcom.com>
[kwilczynski: commit log]
Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>
Reviewed-by: Florian Fainelli <florian.fainelli@broadcom.com>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Myron Stowe <mstowe@redhat.com>
Myron Stowe