Commit Graph

6 Commits

Author SHA1 Message Date
Al Stone cfb30e49b5 gpio: use raw spinlock for gpio chip shadowed data
Bugzilla: https://bugzilla.redhat.com/show_bug.cgi?id=2071835
Tested: This is one of a series of patch sets to enable Arm SystemReady IR
 support in the kernel for NXP i.MX8 platforms.  This set updates GPIO
 support.  It has been tested via simple boot tests and by using the
 kernel GPIO tools to verify pins are being identified and can be used.

Conflicts:
    drivers/gpio/gpio-mlxbf2.c

    Not a supported device, but made the spinlock changes in
    order to allow the module to compile.

commit 3c938cc5cebcbd2291fe97f523c0705a2c24c77d
Author: Schspa Shi <schspa@gmail.com>
Date:   Tue Apr 19 09:28:10 2022 +0800

    gpio: use raw spinlock for gpio chip shadowed data

    In case of PREEMPT_RT, there is a raw_spinlock -> spinlock dependency
    as the lockdep report shows.

    __irq_set_handler
      irq_get_desc_buslock
        __irq_get_desc_lock
          raw_spin_lock_irqsave(&desc->lock, *flags);  // raw spinlock get here
      __irq_do_set_handler
        mask_ack_irq
          dwapb_irq_ack
            spin_lock_irqsave(&gc->bgpio_lock, flags); // sleep able spinlock
      irq_put_desc_busunlock

    Replace with a raw lock to avoid BUGs. This lock is only used to access
    registers, and It's safe to replace with the raw lock without bad
    influence.

    [   15.090359][    T1] =============================
    [   15.090365][    T1] [ BUG: Invalid wait context ]
    [   15.090373][    T1] 5.10.59-rt52-00983-g186a6841c682-dirty #3 Not tainted
    [   15.090386][    T1] -----------------------------
    [   15.090392][    T1] swapper/0/1 is trying to lock:
    [   15.090402][    T1] 70ff00018507c188 (&gc->bgpio_lock){....}-{3:3}, at: _raw_spin_lock_irqsave+0x1c/0x28
    [   15.090470][    T1] other info that might help us debug this:
    [   15.090477][    T1] context-{5:5}
    [   15.090485][    T1] 3 locks held by swapper/0/1:
    [   15.090497][    T1]  #0: c2ff0001816de1a0 (&dev->mutex){....}-{4:4}, at: __device_driver_lock+0x98/0x104
    [   15.090553][    T1]  #1: ffff90001485b4b8 (irq_domain_mutex){+.+.}-{4:4}, at: irq_domain_associate+0xbc/0x6d4
    [   15.090606][    T1]  #2: 4bff000185d7a8e0 (lock_class){....}-{2:2}, at: _raw_spin_lock_irqsave+0x1c/0x28
    [   15.090654][    T1] stack backtrace:
    [   15.090661][    T1] CPU: 4 PID: 1 Comm: swapper/0 Not tainted 5.10.59-rt52-00983-g186a6841c682-dirty #3
    [   15.090682][    T1] Hardware name: Horizon Robotics Journey 5 DVB (DT)
    [   15.090692][    T1] Call trace:
    ......
    [   15.090811][    T1]  _raw_spin_lock_irqsave+0x1c/0x28
    [   15.090828][    T1]  dwapb_irq_ack+0xb4/0x300
    [   15.090846][    T1]  __irq_do_set_handler+0x494/0xb2c
    [   15.090864][    T1]  __irq_set_handler+0x74/0x114
    [   15.090881][    T1]  irq_set_chip_and_handler_name+0x44/0x58
    [   15.090900][    T1]  gpiochip_irq_map+0x210/0x644

    Signed-off-by: Schspa Shi <schspa@gmail.com>
    Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com>
    Acked-by: Linus Walleij <linus.walleij@linaro.org>
    Acked-by: Doug Berger <opendmb@gmail.com>
    Acked-by: Serge Semin <fancer.lancer@gmail.com>
    Signed-off-by: Bartosz Golaszewski <brgl@bgdev.pl>
    (cherry picked from commit 3c938cc5cebcbd2291fe97f523c0705a2c24c77d)

Signed-off-by: Al Stone <ahs3@redhat.com>
2022-08-24 13:31:38 -06:00
Al Stone 77777491c9 gpio: Bulk conversion to generic_handle_domain_irq()
Bugzilla: https://bugzilla.redhat.com/show_bug.cgi?id=2071835
Tested: This is one of a series of patch sets to enable Arm SystemReady IR
 support in the kernel for NXP i.MX8 platforms.  This set updates GPIO
 support.  It has been tested via simple boot tests and by using the
 kernel GPIO tools to verify pins are being identified and can be used.

commit dbd1c54fc82051bf7f3271b43517281f5b2cff51
Author: Marc Zyngier <maz@kernel.org>
Date:   Tue May 4 17:42:18 2021 +0100

    gpio: Bulk conversion to generic_handle_domain_irq()

    Wherever possible, replace constructs that match either
    generic_handle_irq(irq_find_mapping()) or
    generic_handle_irq(irq_linear_revmap()) to a single call to
    generic_handle_domain_irq().

    Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
    Acked-by: Linus Walleij <linus.walleij@linaro.org>
    Signed-off-by: Marc Zyngier <maz@kernel.org>
    (cherry picked from commit dbd1c54fc82051bf7f3271b43517281f5b2cff51)

Signed-off-by: Al Stone <ahs3@redhat.com>
2022-08-24 13:28:24 -06:00
Zou Wei 1e948b1752 gpio: cadence: Add missing MODULE_DEVICE_TABLE
This patch adds missing MODULE_DEVICE_TABLE definition which generates
correct modalias for automatic loading of this driver when it is built
as an external module.

Reported-by: Hulk Robot <hulkci@huawei.com>
Signed-off-by: Zou Wei <zou_wei@huawei.com>
Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>
2021-05-12 13:28:04 +02:00
Linus Walleij 607a0dcddb gpio: cadence: Pass irqchip when adding gpiochip
We need to convert all old gpio irqchips to pass the irqchip
setup along when adding the gpio_chip. For more info see
drivers/gpio/TODO.

For chained irqchips this is a pretty straight-forward
conversion.

Cc: Jan Kotas <jank@cadence.com>
Cc: Thierry Reding <treding@nvidia.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Tested-by: Jan Kotas <jank@cadence.com>
Link: https://lore.kernel.org/r/20190809131804.20352-1-linus.walleij@linaro.org
2019-08-15 09:44:19 +02:00
Enrico Weigelt, metux IT consult b2c09588f2 drivers: gpio: cadence: use devm_platform_ioremap_resource()
Use the new helper that wraps the calls to platform_get_resource()
and devm_ioremap_resource() together.

Signed-off-by: Enrico Weigelt, metux IT consult <info@metux.net>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-04-05 00:04:26 +07:00
Jan Kotas 72ab2f7631 gpio: Add Cadence GPIO driver
This patch adds a driver for Cadence GPIO controller.

It can be enabled with GPIO_CADENCE Kconfig option.
It uses generic GPIO infrastructure and works
as an interrupt controller.
At the moment it only supports level sensitive irqs.

Signed-off-by: Jan Kotas <jank@cadence.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2018-12-21 11:41:00 +01:00