JIRA: https://issues.redhat.com/browse/RHEL-5705
commit 7653a59be8af043adc4c09473975a860e6055ff9
Author: Peng Fan <peng.fan@nxp.com>
Date: Sun Jun 25 20:33:40 2023 +0800
clk: imx: imx8ulp: update SPLL2 type
The SPLL2 on iMX8ULP is different with other frac PLLs, it can
support VCO from 650Mhz to 1Ghz. Following the changes to pllv4,
use the new type IMX_PLLV4_IMX8ULP_1GHZ.
Fixes: c43a801a5789 ("clk: imx: Add clock driver for imx8ulp")
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Abel Vesa <abel.vesa@linaro.org>
Link: https://lore.kernel.org/r/20230625123340.4067536-2-peng.fan@oss.nxp.com
Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
Signed-off-by: Joel Slebodnick <jslebodn@redhat.com>
JIRA: https://issues.redhat.com/browse/RHEL-5705
commit 8a05f5cccdbe851265bf513643ada48c26b1267f
Author: Jacky Bai <ping.bai@nxp.com>
Date: Fri Mar 31 14:38:14 2023 +0800
clk: imx: imx8ulp: update clk flag for system critical clock
In order to support bus fabric clock frequency changed on the fly,
need to update some bus clocks'flags to make sure these clocks'frequency
and parent can be changed on the fly. For these clocks, HW can make sure
no glitch will be introduced when changing on the fly.
In order to support DDR DFS, the HW register bit for DDR_SEL
and DDR_DIV clock will be modified by TF-A. So need to update
these two clock's flag to make sure that the linux kernel side
can correct these clocks' SW state to reflect the actual HW state.
Reviewed-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Abel Vesa <abel.vesa@linaro.org>
Link: https://lore.kernel.org/r/20230331063814.2462059-6-peng.fan@oss.nxp.com
Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
Signed-off-by: Joel Slebodnick <jslebodn@redhat.com>
JIRA: https://issues.redhat.com/browse/RHEL-5705
commit 66d72c62d20eb571b7ab624813b1b98b626ab493
Author: Jacky Bai <ping.bai@nxp.com>
Date: Fri Mar 31 14:38:13 2023 +0800
clk: imx: imx8ulp: Add tpm5 clock as critical gate clock
The TPM5 is used for broadcast timer purpose and registered
with TIMER_OF_DECLARE. As the clock driver is not ready at
that stage, so the TPM5 clock is configured in bootloader(TF-A).
if we just remove the TPM5 clock from linux will introduce a
risk that the TPM5's parent clock will be gated, then lead to
TPM's channel control config can NOT be written into register
successfully.
Due to the above reason, we still need to add the TPM5 clock
into linux clock but register it as a simple critical gate
clock to make sure its parent is always on.
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Abel Vesa <abel.vesa@linaro.org>
Link: https://lore.kernel.org/r/20230331063814.2462059-5-peng.fan@oss.nxp.com
Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
Signed-off-by: Joel Slebodnick <jslebodn@redhat.com>
JIRA: https://issues.redhat.com/browse/RHEL-5705
commit 4883200d8c0b20cc3bf90fcd3b837a344a31ac66
Author: Jacky Bai <ping.bai@nxp.com>
Date: Fri Mar 31 14:38:12 2023 +0800
clk: imx: imx8ulp: keep MU0_B clock enabled always
Keep the A35<->M33 MU0_B clock enabled always for low power
communication.
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Abel Vesa <abel.vesa@linaro.org>
Link: https://lore.kernel.org/r/20230331063814.2462059-4-peng.fan@oss.nxp.com
Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
Signed-off-by: Joel Slebodnick <jslebodn@redhat.com>
JIRA: https://issues.redhat.com/browse/RHEL-5705
commit 335aee51ffc72149ddf99755ba629f981f20e6b6
Author: Jacky Bai <ping.bai@nxp.com>
Date: Fri Mar 31 14:38:11 2023 +0800
clk: imx: imx8ulp: Add divider closest support to get more accurate clock rate
If a divider's parent clock has fractional part, it will hard to round out a
more accurate clock rate for this divider, add the 'CLK_DIVIDER_ROUND_CLOSEST' flags
for such divider to get a more accurate clock rate.
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Abel Vesa <abel.vesa@linaro.org>
Link: https://lore.kernel.org/r/20230331063814.2462059-3-peng.fan@oss.nxp.com
Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
Signed-off-by: Joel Slebodnick <jslebodn@redhat.com>
JIRA: https://issues.redhat.com/browse/RHEL-5705
commit d608c18018c897b88d66f1340fe274b7181817fa
Author: Peng Fan <peng.fan@nxp.com>
Date: Fri Mar 31 14:38:10 2023 +0800
clk: imx: imx8ulp: Fix XBAR_DIVBUS and AD_SLOW clock parents
XBAR_DIVBUS and AD_SLOW should set parent to XBAR_AD_DIVPLAT and
XBAR_DIVBUS respectively, not the NIC_AD. otherwise we will get
wrong clock rate.
Fixes: c43a801a5789 ("clk: imx: Add clock driver for imx8ulp")
Reviewed-by: Jacky Bai <ping.bai@nxp.com>
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Abel Vesa <abel.vesa@linaro.org>
Link: https://lore.kernel.org/r/20230331063814.2462059-2-peng.fan@oss.nxp.com
Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
Signed-off-by: Joel Slebodnick <jslebodn@redhat.com>
JIRA: https://issues.redhat.com/browse/RHEL-5705
commit b5e29cf7617cfae70a5d8b850b26cd3cdd7deaa0
Author: Peng Fan <peng.fan@nxp.com>
Date: Fri Oct 22 21:15:13 2021 +0800
clk: imx: imx8ulp: set suppress_bind_attrs to true
The clock driver is registered as platform devices and
it is possible to reloading the driver at runtime.
But actually the clocks should never be removed to make system work,
attempting to bind again would result in a crash, because almost all
devices depends on clock to function well.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Abel Vesa <abel.vesa@nxp.com>
Link: https://lore.kernel.org/r/20211022131513.17381-1-peng.fan@oss.nxp.com
Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
Signed-off-by: Joel Slebodnick <jslebodn@redhat.com>
JIRA: https://issues.redhat.com/browse/RHEL-5705
commit 3fa36200a43f508ee49895e74d86b511fcd8ff3f
Author: Jacky Bai <ping.bai@nxp.com>
Date: Tue Sep 14 14:52:08 2021 +0800
clk: imx: Add the pcc reset controller support on imx8ulp
On i.MX8ULP, for some of the PCCs, it has a peripheral SW RST bit
resides in the same registers as the clock controller. So add this
SW RST controller support alongs with the pcc clock initialization.
the reset and clock shared the same register, to avoid accessing
the same register by reset control and clock control concurrently,
locking is necessary, so reuse the imx_ccm_lock spinlock to simplify
the code.
Suggested-by: Liu Ying <victor.liu@nxp.com>
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Abel Vesa <abel.vesa@nxp.com>
Link: https://lore.kernel.org/r/20210914065208.3582128-10-ping.bai@nxp.com
Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
Signed-off-by: Joel Slebodnick <jslebodn@redhat.com>
JIRA: https://issues.redhat.com/browse/RHEL-5705
Conflicts: due to e94fd130ce being
backported already
commit c43a801a57890b15e16a0502edf145d59c91baf7
Author: Jacky Bai <ping.bai@nxp.com>
Date: Tue Sep 14 14:52:07 2021 +0800
clk: imx: Add clock driver for imx8ulp
Add clock driver for i.MX8ULP.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Abel Vesa <abel.vesa@nxp.com>
Link: https://lore.kernel.org/r/20210914065208.3582128-9-ping.bai@nxp.com
Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
Signed-off-by: Joel Slebodnick <jslebodn@redhat.com>
Joel Slebodnick