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platform/x86/intel/tpmi: Use 32 bit aligned address for debugfs mem write
JIRA: https://redhat.atlassian.net/browse/RHEL-241103 Upstream status: v7.1 commit 8e0a2fc68ec369f2b6755994da1d318d0898a9d9 Author: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com> Date: Thu Mar 26 11:24:46 2026 -0700 platform/x86/intel/tpmi: Use 32 bit aligned address for debugfs mem write The memory write feature supports 32-bit writes to any TPMI offset. However, future hardware generations may not allow writes to non-32-bit aligned addresses due to hardware optimizations. Since all TPMI addresses are 64-bit aligned and correspond to 64-bit registers, enforce 32-bit alignment for write operations. Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com> Link: https://patch.msgid.link/20260326182446.3478672-1-srinivas.pandruvada@linux.intel.com Reviewed-by: Ilpo Järvinen <ilpo.jarvinen@linux.intel.com> Signed-off-by: Ilpo Järvinen <ilpo.jarvinen@linux.intel.com> Signed-off-by: Dennis Chen <dechen@redhat.com>
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@@ -46,6 +46,7 @@
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* provided by the Intel VSEC driver.
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* provided by the Intel VSEC driver.
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*/
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*/
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#include <linux/align.h>
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#include <linux/auxiliary_bus.h>
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#include <linux/auxiliary_bus.h>
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#include <linux/bitfield.h>
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#include <linux/bitfield.h>
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#include <linux/debugfs.h>
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#include <linux/debugfs.h>
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@@ -479,6 +480,9 @@ static ssize_t mem_write(struct file *file, const char __user *userbuf, size_t l
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addr = array[2];
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addr = array[2];
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value = array[3];
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value = array[3];
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if (!IS_ALIGNED(addr, sizeof(u32)))
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return -EINVAL;
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if (punit >= pfs->pfs_header.num_entries) {
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if (punit >= pfs->pfs_header.num_entries) {
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ret = -EINVAL;
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ret = -EINVAL;
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goto exit_write;
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goto exit_write;
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