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cpufreq: intel_pstate: EAS: Increase cost for CPUs using L3 cache 

JIRA: https://issues.redhat.com/browse/RHEL-112493
Conflicts: needed to add include of linux/cacheinfo.h as RHEL does not
	   have upstream c51a4f11e6d8246590b5e64908c1ed84b33e8ba2

commit 05cf8b8c5118479637efe281e5eb98972d3a3386
Author: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
Date:   Tue May 6 22:47:53 2025 +0200

    cpufreq: intel_pstate: EAS: Increase cost for CPUs using L3 cache

    On some hybrid platforms some efficient CPUs (E-cores) are not connected
    to the L3 cache, but there are no other differences between them and the
    other E-cores that use L3.  In that case, it is generally more efficient
    to run "light" workloads on the E-cores that do not use L3 and allow all
    of the cores using L3, including P-cores, to go into idle states.

    For this reason, slightly increase the cost for all CPUs sharing the L3
    cache to make EAS prefer CPUs that do not use it to the other CPUs of
    the same type (if any).

    Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
    Link: https://patch.msgid.link/2032776.usQuhbGJ8B@rjwysocki.net

Signed-off-by: David Arcari <darcari@redhat.com>
This commit is contained in:
David Arcari 2025-09-02 13:35:43 -04:00
parent b78543d803
commit dcc16669d1
1 changed files with 18 additions and 0 deletions
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18
drivers/cpufreq/intel_pstate.c
View File

@ -29,6 +29,7 @@
#include <linux/bitfield.h>
#include <trace/events/power.h>
#include <linux/units.h>
#include <linux/cacheinfo.h>
#include <asm/cpu.h>
#include <asm/div64.h>
@ -982,6 +983,7 @@ static int hybrid_get_cost(struct device *dev, unsigned long freq,
unsigned long *cost)
{
struct pstate_data *pstate = &all_cpu_data[dev->id]->pstate;
struct cpu_cacheinfo *cacheinfo = get_cpu_cacheinfo(dev->id);
/*
* The smaller the perf-to-frequency scaling factor, the larger the IPC
@ -994,6 +996,22 @@ static int hybrid_get_cost(struct device *dev, unsigned long freq,
* of the same type in different "utilization bins" is different.
*/
*cost = div_u64(100ULL * INTEL_PSTATE_CORE_SCALING, pstate->scaling) + freq;
/*
* Increase the cost slightly for CPUs able to access L3 to avoid
* touching it in case some other CPUs of the same type can do the work
* without it.
*/
if (cacheinfo) {
unsigned int i;
/* Check if L3 cache is there. */
for (i = 0; i < cacheinfo->num_leaves; i++) {
if (cacheinfo->info_list[i].level == 3) {
*cost += 2;
break;
}
}
}
return 0;
}