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PCI: qcom: Use bulk clock APIs for handling clocks for IP rev 2.3.2 

Bugzilla: https://bugzilla.redhat.com/show_bug.cgi?id=2228915
Upstream Status: 5329bcc4a1e7dc41fcdffaa55c73b17b527b804f

commit 5329bcc4a1e7dc41fcdffaa55c73b17b527b804f
Author: Manivannan Sadhasivam <mani@kernel.org>
Date:   Thu Mar 16 13:41:07 2023 +0530

    PCI: qcom: Use bulk clock APIs for handling clocks for IP rev 2.3.2

    All the clocks are enabled and disabled at the same time. So the bulk clock
    APIs can be used to handle them together. This simplifies the code a lot.

    Link: https://lore.kernel.org/r/20230316081117.14288-10-manivannan.sadhasivam@linaro.org
    Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
    Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org>

Signed-off-by: Myron Stowe <mstowe@redhat.com>
This commit is contained in:
Myron Stowe 2023-08-02 08:45:41 -06:00
parent 8d33dcd2bb
commit d32a814e5f
1 changed files with 15 additions and 57 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

72
drivers/pci/controller/dwc/pcie-qcom.c
View File

@ -162,12 +162,10 @@ struct qcom_pcie_resources_2_1_0 {
struct regulator_bulk_data supplies[QCOM_PCIE_2_1_0_MAX_SUPPLY];
};
#define QCOM_PCIE_2_3_2_MAX_SUPPLY 2
#define QCOM_PCIE_2_3_2_MAX_CLOCKS 4
#define QCOM_PCIE_2_3_2_MAX_SUPPLY 2
struct qcom_pcie_resources_2_3_2 {
struct clk *aux_clk;
struct clk *master_clk;
struct clk *slave_clk;
struct clk *cfg_clk;
struct clk_bulk_data clks[QCOM_PCIE_2_3_2_MAX_CLOCKS];
struct regulator_bulk_data supplies[QCOM_PCIE_2_3_2_MAX_SUPPLY];
};
@ -539,21 +537,14 @@ static int qcom_pcie_get_resources_2_3_2(struct qcom_pcie *pcie)
if (ret)
return ret;
res->aux_clk = devm_clk_get(dev, "aux");
if (IS_ERR(res->aux_clk))
return PTR_ERR(res->aux_clk);
res->clks[0].id = "aux";
res->clks[1].id = "cfg";
res->clks[2].id = "bus_master";
res->clks[3].id = "bus_slave";
res->cfg_clk = devm_clk_get(dev, "cfg");
if (IS_ERR(res->cfg_clk))
return PTR_ERR(res->cfg_clk);
res->master_clk = devm_clk_get(dev, "bus_master");
if (IS_ERR(res->master_clk))
return PTR_ERR(res->master_clk);
res->slave_clk = devm_clk_get(dev, "bus_slave");
if (IS_ERR(res->slave_clk))
return PTR_ERR(res->slave_clk);
ret = devm_clk_bulk_get(dev, ARRAY_SIZE(res->clks), res->clks);
if (ret < 0)
return ret;
return 0;
}
@ -562,11 +553,7 @@ static void qcom_pcie_deinit_2_3_2(struct qcom_pcie *pcie)
{
struct qcom_pcie_resources_2_3_2 *res = &pcie->res.v2_3_2;
clk_disable_unprepare(res->slave_clk);
clk_disable_unprepare(res->master_clk);
clk_disable_unprepare(res->cfg_clk);
clk_disable_unprepare(res->aux_clk);
clk_bulk_disable_unprepare(ARRAY_SIZE(res->clks), res->clks);
regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies);
}
@ -583,43 +570,14 @@ static int qcom_pcie_init_2_3_2(struct qcom_pcie *pcie)
return ret;
}
ret = clk_prepare_enable(res->aux_clk);
ret = clk_bulk_prepare_enable(ARRAY_SIZE(res->clks), res->clks);
if (ret) {
dev_err(dev, "cannot prepare/enable aux clock\n");
goto err_aux_clk;
}
ret = clk_prepare_enable(res->cfg_clk);
if (ret) {
dev_err(dev, "cannot prepare/enable cfg clock\n");
goto err_cfg_clk;
}
ret = clk_prepare_enable(res->master_clk);
if (ret) {
dev_err(dev, "cannot prepare/enable master clock\n");
goto err_master_clk;
}
ret = clk_prepare_enable(res->slave_clk);
if (ret) {
dev_err(dev, "cannot prepare/enable slave clock\n");
goto err_slave_clk;
dev_err(dev, "cannot prepare/enable clocks\n");
regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies);
return ret;
}
return 0;
err_slave_clk:
clk_disable_unprepare(res->master_clk);
err_master_clk:
clk_disable_unprepare(res->cfg_clk);
err_cfg_clk:
clk_disable_unprepare(res->aux_clk);
err_aux_clk:
regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies);
return ret;
}
static int qcom_pcie_post_init_2_3_2(struct qcom_pcie *pcie)